diff options
| author | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
| commit | 9e45ada1718b6df9310757fdc7cd78db4695516f (patch) | |
| tree | c5cc9f2173f36e38addd8ca08e32ac010e56ef73 /tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing | |
| parent | 12497284949cb5418e6bc403723c034aee655666 (diff) | |
| download | gem5-9e45ada1718b6df9310757fdc7cd78db4695516f.tar.xz | |
stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
Diffstat (limited to 'tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing')
| -rwxr-xr-x | tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout | 14 | ||||
| -rw-r--r-- | tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt | 840 |
2 files changed, 420 insertions, 434 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 849e6b2a1..8e80e0787 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,15 +7,15 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:04:38 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:17:19 +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:11:50 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 14406500 because target called exit() +Exiting @ tick 14139000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index b84cef0e7..f38e46afc 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 70938 # Simulator instruction rate (inst/s) -host_mem_usage 204908 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 79897622 # Simulator tick rate (ticks/s) +host_inst_rate 53800 # Simulator instruction rate (inst/s) +host_mem_usage 205552 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host +host_tick_rate 59488297 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14406500 # Number of ticks simulated +sim_ticks 14139000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 801 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 4845 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 916 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 4600 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 174 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1651 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 3171 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 5637 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 690 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 1521 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 3069 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 5341 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 654 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches::0 1051 # Number of branches committed system.cpu.commit.COM:branches::1 1051 # Number of branches committed system.cpu.commit.COM:branches::total 2102 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 135 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 132 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 23178 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.552550 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.284564 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 22158 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.577985 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.311672 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 17373 74.95% 74.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 2862 12.35% 87.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 1369 5.91% 93.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 536 2.31% 95.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 355 1.53% 97.05% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 284 1.23% 98.28% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 169 0.73% 99.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 95 0.41% 99.42% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 135 0.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 16375 73.90% 73.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 2877 12.98% 86.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 1274 5.75% 92.63% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 599 2.70% 95.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 362 1.63% 96.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 252 1.14% 98.11% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 188 0.85% 98.96% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 99 0.45% 99.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 132 0.60% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 23178 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 22158 # Number of insts commited each cycle system.cpu.commit.COM:count::0 6404 # Number of instructions committed system.cpu.commit.COM:count::1 6403 # Number of instructions committed system.cpu.commit.COM:count::total 12807 # Number of instructions committed @@ -55,118 +55,118 @@ system.cpu.commit.COM:refs::total 4100 # Nu system.cpu.commit.COM:swp_count::0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count::1 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count::total 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1214 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1116 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 11211 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10253 # The number of squashed insts skipped by commit system.cpu.committedInsts::0 6387 # Number of Instructions Simulated system.cpu.committedInsts::1 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.511351 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.512058 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.255852 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3953 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 35613.003096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35613.003096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36812.195122 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3630 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::0 11503000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11503000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081710 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 323 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::0 118 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::0 7546500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7546500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.051859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::0 205 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses +system.cpu.cpi::0 4.427587 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.428281 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.213967 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 36145.962733 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36145.962733 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36908.415842 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3474 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::0 11639000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11639000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.084826 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 322 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::0 120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::0 7455500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7455500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.053214 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053214 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::0 202 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 33528.289474 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33528.289474 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36083.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::0 25481500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25481500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::0 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::0 6278500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6278500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::0 174 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 174 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency::0 32784.604520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32784.604520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36119.863014 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1022 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::0 23211500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23211500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 708 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::0 562 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::0 5273500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5273500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13.282051 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.919540 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5683 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 34150.046168 # average overall miss latency +system.cpu.dcache.demand_accesses 5526 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 33835.436893 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34150.046168 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::0 36477.572559 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33835.436893 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::0 36577.586207 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits 4600 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::0 36984500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 4496 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::0 34850500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36984500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.190568 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1083 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::0 704 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_miss_latency::total 34850500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.186392 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1030 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::0 682 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 704 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::0 13825000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::total 682 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::0 12729000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13825000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.066690 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency::total 12729000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.062975 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.066690 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::0 379 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062975 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::0 348 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 379 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.054473 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 223.120996 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 5683 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 34150.046168 # average overall miss latency +system.cpu.dcache.occ_%::0 0.053836 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 220.510583 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 5526 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 33835.436893 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34150.046168 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::0 36477.572559 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33835.436893 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::0 36577.586207 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4600 # number of overall hits -system.cpu.dcache.overall_miss_latency::0 36984500 # number of overall miss cycles +system.cpu.dcache.overall_hits 4496 # number of overall hits +system.cpu.dcache.overall_miss_latency::0 34850500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36984500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.190568 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1083 # number of overall misses -system.cpu.dcache.overall_mshr_hits::0 704 # number of overall MSHR hits +system.cpu.dcache.overall_miss_latency::total 34850500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.186392 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1030 # number of overall misses +system.cpu.dcache.overall_mshr_hits::0 682 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 704 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::0 13825000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_hits::total 682 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::0 12729000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13825000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.066690 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency::total 12729000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.062975 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.066690 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::0 379 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062975 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::0 348 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 379 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -176,153 +176,153 @@ system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 223.120996 # Cycle average of tags in use -system.cpu.dcache.total_refs 4662 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 220.510583 # Cycle average of tags in use +system.cpu.dcache.total_refs 4496 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks::0 0 # number of writebacks system.cpu.dcache.writebacks::1 0 # number of writebacks system.cpu.dcache.writebacks::total 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 451 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 595 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 27842 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 34006 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 4930 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2198 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 677 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 6328 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 4667 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 414 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 569 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 26624 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 32585 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4771 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2039 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 734 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 167 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 6131 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 6178 # DTB hits -system.cpu.dtb.data_misses 150 # DTB misses +system.cpu.dtb.data_hits 5993 # DTB hits +system.cpu.dtb.data_misses 138 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 4160 # DTB read accesses +system.cpu.dtb.read_accesses 3997 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 4072 # DTB read hits -system.cpu.dtb.read_misses 88 # DTB read misses -system.cpu.dtb.write_accesses 2168 # DTB write accesses +system.cpu.dtb.read_hits 3913 # DTB read hits +system.cpu.dtb.read_misses 84 # DTB read misses +system.cpu.dtb.write_accesses 2134 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 2106 # DTB write hits -system.cpu.dtb.write_misses 62 # DTB write misses -system.cpu.fetch.Branches 5637 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4152 # Number of cache lines fetched -system.cpu.fetch.Cycles 9523 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 615 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 31429 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1766 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.195634 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4152 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1491 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.090754 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 23259 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.351262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.751825 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 2080 # DTB write hits +system.cpu.dtb.write_misses 54 # DTB write misses +system.cpu.fetch.Branches 5341 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 3993 # Number of cache lines fetched +system.cpu.fetch.Cycles 9162 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 611 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 29881 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1641 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.188868 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 3993 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1570 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.056650 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 22205 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.345688 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.736511 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17946 77.16% 77.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 425 1.83% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 330 1.42% 80.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 452 1.94% 82.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 406 1.75% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 353 1.52% 85.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 452 1.94% 87.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 273 1.17% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2622 11.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17092 76.97% 76.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 418 1.88% 78.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 346 1.56% 80.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 428 1.93% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 443 2.00% 84.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 320 1.44% 85.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 433 1.95% 87.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 283 1.27% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2442 11.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 23259 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 4152 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 35658.767773 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35658.767773 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35482.171799 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3308 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::0 30096000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30096000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.203276 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 844 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits::0 227 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency::0 21892500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21892500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.148603 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148603 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::0 617 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 617 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 22205 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 3993 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 35767.942584 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35767.942584 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35489.482201 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 3157 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::0 29902000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 29902000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.209366 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 836 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits::0 218 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency::0 21932500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21932500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.154771 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154771 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::0 618 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 618 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.361426 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.108414 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4152 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 35658.767773 # average overall miss latency +system.cpu.icache.demand_accesses 3993 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 35767.942584 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35658.767773 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::0 35482.171799 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency::total 35767.942584 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::0 35489.482201 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.icache.demand_hits 3308 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::0 30096000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_hits 3157 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::0 29902000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30096000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.203276 # miss rate for demand accesses -system.cpu.icache.demand_misses 844 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits::0 227 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_miss_latency::total 29902000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.209366 # miss rate for demand accesses +system.cpu.icache.demand_misses 836 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits::0 218 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency::0 21892500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_hits::total 218 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency::0 21932500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21892500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.148603 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency::total 21932500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.154771 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148603 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::0 617 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_rate::total 0.154771 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::0 618 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 617 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 618 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.156062 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 319.614812 # Average occupied blocks per context -system.cpu.icache.overall_accesses 4152 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 35658.767773 # average overall miss latency +system.cpu.icache.occ_%::0 0.155666 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 318.803897 # Average occupied blocks per context +system.cpu.icache.overall_accesses 3993 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 35767.942584 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35658.767773 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::0 35482.171799 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency::total 35767.942584 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::0 35489.482201 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3308 # number of overall hits -system.cpu.icache.overall_miss_latency::0 30096000 # number of overall miss cycles +system.cpu.icache.overall_hits 3157 # number of overall hits +system.cpu.icache.overall_miss_latency::0 29902000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30096000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.203276 # miss rate for overall accesses -system.cpu.icache.overall_misses 844 # number of overall misses -system.cpu.icache.overall_mshr_hits::0 227 # number of overall MSHR hits +system.cpu.icache.overall_miss_latency::total 29902000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.209366 # miss rate for overall accesses +system.cpu.icache.overall_misses 836 # number of overall misses +system.cpu.icache.overall_mshr_hits::0 218 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 227 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency::0 21892500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_hits::total 218 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency::0 21932500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21892500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.148603 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency::total 21932500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.154771 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148603 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::0 617 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_rate::total 0.154771 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::0 618 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 617 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 618 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -332,198 +332,198 @@ system.cpu.icache.overall_mshr_uncacheable_misses::total 0 system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.sampled_refs 617 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 618 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 319.614812 # Cycle average of tags in use -system.cpu.icache.total_refs 3308 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 318.803897 # Cycle average of tags in use +system.cpu.icache.total_refs 3157 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks::0 0 # number of writebacks system.cpu.icache.writebacks::1 0 # number of writebacks system.cpu.icache.writebacks::total 0 # number of writebacks -system.cpu.idleCycles 5555 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches::0 1592 # Number of branches executed -system.cpu.iew.EXEC:branches::1 1585 # Number of branches executed -system.cpu.iew.EXEC:branches::total 3177 # Number of branches executed -system.cpu.iew.EXEC:nop::0 69 # number of nop insts executed -system.cpu.iew.EXEC:nop::1 66 # number of nop insts executed -system.cpu.iew.EXEC:nop::total 135 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.670750 # Inst execution rate -system.cpu.iew.EXEC:refs::0 3218 # number of memory reference insts executed -system.cpu.iew.EXEC:refs::1 3132 # number of memory reference insts executed -system.cpu.iew.EXEC:refs::total 6350 # number of memory reference insts executed -system.cpu.iew.EXEC:stores::0 1105 # Number of stores executed -system.cpu.iew.EXEC:stores::1 1082 # Number of stores executed -system.cpu.iew.EXEC:stores::total 2187 # Number of stores executed +system.cpu.idleCycles 6074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches::0 1552 # Number of branches executed +system.cpu.iew.EXEC:branches::1 1552 # Number of branches executed +system.cpu.iew.EXEC:branches::total 3104 # Number of branches executed +system.cpu.iew.EXEC:nop::0 64 # number of nop insts executed +system.cpu.iew.EXEC:nop::1 70 # number of nop insts executed +system.cpu.iew.EXEC:nop::total 134 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.666325 # Inst execution rate +system.cpu.iew.EXEC:refs::0 3105 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::1 3045 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::total 6150 # number of memory reference insts executed +system.cpu.iew.EXEC:stores::0 1087 # Number of stores executed +system.cpu.iew.EXEC:stores::1 1064 # Number of stores executed +system.cpu.iew.EXEC:stores::total 2151 # Number of stores executed system.cpu.iew.EXEC:swp::0 0 # number of swp insts executed system.cpu.iew.EXEC:swp::1 0 # number of swp insts executed system.cpu.iew.EXEC:swp::total 0 # number of swp insts executed -system.cpu.iew.WB:consumers::0 6017 # num instructions consuming a value -system.cpu.iew.WB:consumers::1 5962 # num instructions consuming a value -system.cpu.iew.WB:consumers::total 11979 # num instructions consuming a value -system.cpu.iew.WB:count::0 9293 # cumulative count of insts written-back -system.cpu.iew.WB:count::1 9238 # cumulative count of insts written-back -system.cpu.iew.WB:count::total 18531 # cumulative count of insts written-back -system.cpu.iew.WB:fanout::0 0.773143 # average fanout of values written-back -system.cpu.iew.WB:fanout::1 0.773398 # average fanout of values written-back -system.cpu.iew.WB:fanout::total 1.546541 # average fanout of values written-back +system.cpu.iew.WB:consumers::0 5852 # num instructions consuming a value +system.cpu.iew.WB:consumers::1 5867 # num instructions consuming a value +system.cpu.iew.WB:consumers::total 11719 # num instructions consuming a value +system.cpu.iew.WB:count::0 9073 # cumulative count of insts written-back +system.cpu.iew.WB:count::1 9067 # cumulative count of insts written-back +system.cpu.iew.WB:count::total 18140 # cumulative count of insts written-back +system.cpu.iew.WB:fanout::0 0.775290 # average fanout of values written-back +system.cpu.iew.WB:fanout::1 0.774501 # average fanout of values written-back +system.cpu.iew.WB:fanout::total 1.549792 # average fanout of values written-back system.cpu.iew.WB:penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized::total 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers::0 4652 # num instructions producing a value -system.cpu.iew.WB:producers::1 4611 # num instructions producing a value -system.cpu.iew.WB:producers::total 9263 # num instructions producing a value -system.cpu.iew.WB:rate::0 0.322517 # insts written-back per cycle -system.cpu.iew.WB:rate::1 0.320608 # insts written-back per cycle -system.cpu.iew.WB:rate::total 0.643125 # insts written-back per cycle -system.cpu.iew.WB:sent::0 9430 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent::1 9343 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent::total 18773 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1399 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1055 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 5029 # Number of dispatched load instructions +system.cpu.iew.WB:producers::0 4537 # num instructions producing a value +system.cpu.iew.WB:producers::1 4544 # num instructions producing a value +system.cpu.iew.WB:producers::total 9081 # num instructions producing a value +system.cpu.iew.WB:rate::0 0.320839 # insts written-back per cycle +system.cpu.iew.WB:rate::1 0.320627 # insts written-back per cycle +system.cpu.iew.WB:rate::total 0.641465 # insts written-back per cycle +system.cpu.iew.WB:sent::0 9197 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::1 9165 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::total 18362 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1270 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 840 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4751 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 731 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2605 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 24098 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts::0 2113 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2050 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4163 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1224 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 19327 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 669 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2526 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 23137 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts::0 2018 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 1981 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 3999 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1059 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 18843 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2198 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 2039 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 62 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 71 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1385 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 471 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1198 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 429 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 58 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 64 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1274 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 404 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 135 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1143 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 256 # Number of branches that were predicted taken incorrectly -system.cpu.ipc::0 0.221663 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.221628 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.443291 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.1.squashedLoads 1183 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 367 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 131 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1010 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 260 # Number of branches that were predicted taken incorrectly +system.cpu.ipc::0 0.225857 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.225821 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.451678 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6901 66.76% 66.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 66.79% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 66.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 66.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 66.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 66.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 66.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2273 21.99% 88.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1158 11.20% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6654 67.06% 67.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2121 21.37% 88.48% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1143 11.52% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 10337 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 9923 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntAlu 6867 67.23% 67.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% 67.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% 67.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% 67.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::MemRead 2182 21.36% 88.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::MemWrite 1160 11.36% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntAlu 6748 67.62% 67.64% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% 67.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% 67.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemRead 2103 21.07% 88.75% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemWrite 1123 11.25% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::total 10214 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::total 9979 # Type of FU issued system.cpu.iq.ISSUE:FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntAlu 13768 66.99% 67.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% 67.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::MemRead 4455 21.68% 88.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::MemWrite 2318 11.28% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntAlu 13402 67.34% 67.36% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemRead 4224 21.22% 88.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemWrite 2266 11.39% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::total 20551 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt::0 79 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt::1 88 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt::total 167 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate::0 0.003844 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate::1 0.004282 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate::total 0.008126 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type::total 19902 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt::0 80 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::1 85 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::total 165 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate::0 0.004020 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::1 0.004271 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::total 0.008291 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 9 5.39% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 95 56.89% 62.28% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 63 37.72% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 16 9.70% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 89 53.94% 63.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 60 36.36% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 23259 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.883572 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.458526 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 22205 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.896285 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.439530 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 14576 62.67% 62.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 3197 13.75% 76.41% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 2342 10.07% 86.48% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 1327 5.71% 92.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 883 3.80% 95.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 568 2.44% 98.43% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 270 1.16% 99.59% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 71 0.31% 99.89% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 25 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 13672 61.57% 61.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 3186 14.35% 75.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 2211 9.96% 85.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 1439 6.48% 92.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 897 4.04% 96.40% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 509 2.29% 98.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 214 0.96% 99.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 56 0.25% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 21 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 23259 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.713230 # Inst issue rate -system.cpu.iq.iqInstsAdded 23917 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 20551 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 22205 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.703773 # Inst issue rate +system.cpu.iq.iqInstsAdded 22957 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 19902 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9939 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9000 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5669 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 5071 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 4210 # ITB accesses +system.cpu.itb.fetch_accesses 4049 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 4152 # ITB hits -system.cpu.itb.fetch_misses 58 # ITB misses +system.cpu.itb.fetch_hits 3993 # ITB hits +system.cpu.itb.fetch_misses 56 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -533,11 +533,11 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34623.287671 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34623.287671 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34643.835616 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31544.520548 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency::0 5055000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5055000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::0 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5058000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4605500 # number of ReadExReq MSHR miss cycles @@ -546,103 +546,89 @@ system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 822 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::0 34548.170732 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34548.170732 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31393.902439 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 820 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::0 34537.897311 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34537.897311 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31396.088020 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::0 28329500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28329500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997567 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 820 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25743000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25743000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997567 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997567 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::0 820 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34500 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34500 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31392.857143 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency::0 966000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 966000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 879000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 879000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses::0 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency::0 28252000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28252000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997561 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 818 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25682000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25682000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997561 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997561 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::0 818 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 818 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002525 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002445 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 968 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::0 34559.523810 # average overall miss latency +system.cpu.l2cache.demand_accesses 966 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::0 34553.941909 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34559.523810 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31416.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34553.941909 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31418.568465 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::0 33384500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::0 33310000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33384500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997934 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 966 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency::total 33310000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997930 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 964 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::0 30348500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::0 30287500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30348500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::0 0.997934 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_latency::total 30287500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::0 0.997930 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997934 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::0 966 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997930 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::0 964 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 964 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.013217 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 433.083390 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 968 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::0 34559.523810 # average overall miss latency +system.cpu.l2cache.occ_%::0 0.013480 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 441.702410 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 966 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::0 34553.941909 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34559.523810 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31416.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34553.941909 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31418.568465 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency::0 33384500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::0 33310000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33384500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997934 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 966 # number of overall misses +system.cpu.l2cache.overall_miss_latency::total 33310000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997930 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 964 # number of overall misses system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::0 30348500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::0 30287500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30348500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::0 0.997934 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_latency::total 30287500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::0 0.997930 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997934 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::0 966 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997930 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::0 964 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 966 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 964 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -652,43 +638,43 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.sampled_refs 792 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 818 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 433.083390 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 441.702410 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks::0 0 # number of writebacks system.cpu.l2cache.writebacks::1 0 # number of writebacks system.cpu.l2cache.writebacks::total 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2570 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1336 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 27 # Number of conflicting loads. -system.cpu.memDep1.conflictingStores 5 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2459 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1269 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 28814 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2841 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2383 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1294 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 22 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 7 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2368 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1232 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 28279 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2728 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 34469 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1383 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IdleCycles 33046 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1284 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 33146 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 26493 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 19854 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 4562 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2198 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1440 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 10688 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 847 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 3428 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.timesIdled 293 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:RenameLookups 31631 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 25294 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 18871 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4411 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2039 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1326 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 9705 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 679 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 50 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 3216 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed +system.cpu.timesIdled 276 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls |