diff options
| author | Nathan Binkert <nate@binkert.org> | 2008-07-24 16:31:54 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2008-07-24 16:31:54 -0700 |
| commit | 0622eec53ae87e008a8d5e0e685321c69ea401d3 (patch) | |
| tree | a11ed967728a45a162e601263db3c161fe3ec82d /tests/quick/01.hello-2T-smt/ref/alpha/linux | |
| parent | f3a3ab7f2cfdae687a1dc07dff10c7fa4bde921c (diff) | |
| download | gem5-0622eec53ae87e008a8d5e0e685321c69ea401d3.tar.xz | |
regress: update regressions for tty emulation fix.
Diffstat (limited to 'tests/quick/01.hello-2T-smt/ref/alpha/linux')
3 files changed, 393 insertions, 390 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index ca040dc25..fc5cea346 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 @@ -386,6 +387,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 4a5d707e1..28f9f7577 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,193 +1,193 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 722 # Number of BTB hits -global.BPredUnit.BTBLookups 3569 # Number of BTB lookups -global.BPredUnit.RASInCorrect 133 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1125 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2392 # Number of conditional branches predicted -global.BPredUnit.lookups 4127 # Number of BP lookups -global.BPredUnit.usedRAS 550 # Number of times the RAS was used to get a target. -host_inst_rate 41846 # Simulator instruction rate (inst/s) -host_mem_usage 152588 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host -host_tick_rate 23650670 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 18 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 33 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 36 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1975 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2036 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1163 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1158 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 817 # Number of BTB hits +global.BPredUnit.BTBLookups 4239 # Number of BTB lookups +global.BPredUnit.RASInCorrect 150 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1415 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2870 # Number of conditional branches predicted +global.BPredUnit.lookups 4960 # Number of BP lookups +global.BPredUnit.usedRAS 590 # Number of times the RAS was used to get a target. +host_inst_rate 59476 # Simulator instruction rate (inst/s) +host_mem_usage 210328 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 33433367 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 46 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 29 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 54 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2257 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 2354 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1267 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1298 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 11247 # Number of instructions simulated -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 6363000 # Number of ticks simulated -system.cpu.commit.COM:branches 1724 # Number of branches committed -system.cpu.commit.COM:branches_0 862 # Number of branches committed -system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 145 # number cycles where commit BW limit reached +sim_insts 12595 # Number of instructions simulated +sim_seconds 0.000007 # Number of seconds simulated +sim_ticks 7085500 # Number of ticks simulated +system.cpu.commit.COM:branches 2024 # Number of branches committed +system.cpu.commit.COM:branches_0 1012 # Number of branches committed +system.cpu.commit.COM:branches_1 1012 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 152 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 12623 +system.cpu.commit.COM:committed_per_cycle.samples 14074 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 7897 6256.04% - 1 2220 1758.69% - 2 993 786.66% - 3 507 401.65% - 4 332 263.01% - 5 219 173.49% - 6 199 157.65% - 7 111 87.93% - 8 145 114.87% + 0 8763 6226.37% + 1 2528 1796.22% + 2 1133 805.03% + 3 504 358.11% + 4 369 262.19% + 5 263 186.87% + 6 218 154.90% + 7 144 102.32% + 8 152 108.00% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 11281 # Number of instructions committed -system.cpu.commit.COM:count_0 5640 # Number of instructions committed -system.cpu.commit.COM:count_1 5641 # Number of instructions committed -system.cpu.commit.COM:loads 1958 # Number of loads committed -system.cpu.commit.COM:loads_0 979 # Number of loads committed -system.cpu.commit.COM:loads_1 979 # Number of loads committed +system.cpu.commit.COM:count 12629 # Number of instructions committed +system.cpu.commit.COM:count_0 6314 # Number of instructions committed +system.cpu.commit.COM:count_1 6315 # Number of instructions committed +system.cpu.commit.COM:loads 2336 # Number of loads committed +system.cpu.commit.COM:loads_0 1168 # Number of loads committed +system.cpu.commit.COM:loads_1 1168 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 3582 # Number of memory references committed -system.cpu.commit.COM:refs_0 1791 # Number of memory references committed -system.cpu.commit.COM:refs_1 1791 # Number of memory references committed +system.cpu.commit.COM:refs 4060 # Number of memory references committed +system.cpu.commit.COM:refs_0 2030 # Number of memory references committed +system.cpu.commit.COM:refs_1 2030 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 885 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions +system.cpu.commit.branchMispredicts 1036 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 12629 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8502 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 5623 # Number of Instructions Simulated -system.cpu.committedInsts_1 5624 # Number of Instructions Simulated -system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 2.263383 # CPI: Cycles Per Instruction -system.cpu.cpi_1 2.262980 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.131591 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3079 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3079 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 12116.724739 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10527.918782 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2792 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2792 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 3477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.093212 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 287 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 287 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 90 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2074000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 2074000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.063982 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 197 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 197 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 9139.837398 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 8686.781609 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1009 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1009 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5621000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 5621000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate_0 0.378695 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 615 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 615 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 441 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 441 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1511500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 1511500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.107143 # mshr miss rate for WriteReq accesses +system.cpu.commit.commitSquashedInsts 9674 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 6297 # Number of Instructions Simulated +system.cpu.committedInsts_1 6298 # Number of Instructions Simulated +system.cpu.committedInsts_total 12595 # Number of Instructions Simulated +system.cpu.cpi_0 2.250596 # CPI: Cycles Per Instruction +system.cpu.cpi_1 2.250238 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.125208 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3671 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 3671 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 12250.889680 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10641.025641 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3390 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 3390 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3442500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 3442500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.076546 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 281 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 86 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 86 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 2075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.053119 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 195 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 195 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1724 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 1724 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency_0 9093.800979 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 8701.149425 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1111 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1111 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5574500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 5574500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.355568 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 613 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 613 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 439 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 439 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1514000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 1514000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.266082 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.379412 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4703 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4703 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 5395 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 5395 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 10087.028825 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 10086.129754 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 9664.420485 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 9726.287263 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 3801 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3801 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 4501 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 4501 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9098500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 9098500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 9017000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 9017000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.191792 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.165709 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 902 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 902 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 894 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 894 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 531 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 531 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 525 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 525 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3585500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 3585500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3589000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 3589000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.078886 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.068397 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 371 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 371 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 369 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 369 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4703 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4703 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 5395 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 5395 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 10087.028825 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 10086.129754 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 9664.420485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 9726.287263 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3801 # number of overall hits -system.cpu.dcache.overall_hits_0 3801 # number of overall hits +system.cpu.dcache.overall_hits 4501 # number of overall hits +system.cpu.dcache.overall_hits_0 4501 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 9098500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 9098500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 9017000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 9017000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.191792 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.165709 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 902 # number of overall misses -system.cpu.dcache.overall_misses_0 902 # number of overall misses +system.cpu.dcache.overall_misses 894 # number of overall misses +system.cpu.dcache.overall_misses_0 894 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 531 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 531 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 525 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 525 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3585500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 3585500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3589000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 3589000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.078886 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.068397 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 371 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 371 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 369 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 369 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -207,161 +207,161 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 342 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 340 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 214.045910 # Cycle average of tags in use -system.cpu.dcache.total_refs 3853 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 223.357154 # Cycle average of tags in use +system.cpu.dcache.total_refs 4549 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 2156 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 253 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 362 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22792 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 17306 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3860 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1667 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 387 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BlockedCycles 2189 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 393 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 537 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 25750 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 19285 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4519 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1860 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 557 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 183 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 5201 # DTB accesses +system.cpu.dtb.accesses 5942 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 5076 # DTB hits +system.cpu.dtb.hits 5817 # DTB hits system.cpu.dtb.misses 125 # DTB misses -system.cpu.dtb.read_accesses 3261 # DTB read accesses +system.cpu.dtb.read_accesses 3857 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 3178 # DTB read hits -system.cpu.dtb.read_misses 83 # DTB read misses -system.cpu.dtb.write_accesses 1940 # DTB write accesses +system.cpu.dtb.read_hits 3775 # DTB read hits +system.cpu.dtb.read_misses 82 # DTB read misses +system.cpu.dtb.write_accesses 2085 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1898 # DTB write hits -system.cpu.dtb.write_misses 42 # DTB write misses -system.cpu.fetch.Branches 4127 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3105 # Number of cache lines fetched -system.cpu.fetch.Cycles 7305 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 481 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 25026 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1246 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.324271 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3105 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1272 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.966371 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 2042 # DTB write hits +system.cpu.dtb.write_misses 43 # DTB write misses +system.cpu.fetch.Branches 4960 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 3670 # Number of cache lines fetched +system.cpu.fetch.Cycles 8581 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 538 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 28943 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1537 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.349986 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 3670 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1407 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.042266 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 12676 +system.cpu.fetch.rateDist.samples 14126 system.cpu.fetch.rateDist.min_value 0 - 0 8531 6730.04% - 1 309 243.77% - 2 245 193.28% - 3 260 205.11% - 4 342 269.80% - 5 308 242.98% - 6 324 255.60% - 7 261 205.90% - 8 2096 1653.52% + 0 9265 6558.83% + 1 397 281.04% + 2 297 210.25% + 3 373 264.05% + 4 393 278.21% + 5 288 203.88% + 6 408 288.83% + 7 267 189.01% + 8 2438 1725.90% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 3105 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 3105 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 10171.875000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7742.694805 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2401 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2401 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 7161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.226731 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 3670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 3670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 10197.443182 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7726.171244 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2966 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2966 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7179000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 7179000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.191826 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 704 # number of ReadReq misses system.cpu.icache.ReadReq_misses_0 704 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4769500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 4769500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.198390 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 616 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 616 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_hits 85 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 85 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4782500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 4782500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.168665 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.897727 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.791599 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3105 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 3105 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 3670 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 3670 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 10171.875000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 10197.443182 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 7742.694805 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 7726.171244 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 2401 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2401 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2966 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2966 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7161000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 7161000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 7179000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 7179000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.226731 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.191826 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses system.cpu.icache.demand_misses 704 # number of demand (read+write) misses system.cpu.icache.demand_misses_0 704 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 88 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 88 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 85 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 85 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4769500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 4769500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 4782500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 4782500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.198390 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.168665 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 616 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 616 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 3105 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 3105 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 3670 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 3670 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 10171.875000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 10197.443182 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 7742.694805 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 7726.171244 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2401 # number of overall hits -system.cpu.icache.overall_hits_0 2401 # number of overall hits +system.cpu.icache.overall_hits 2966 # number of overall hits +system.cpu.icache.overall_hits_0 2966 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 7161000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 7161000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 7179000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 7179000 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.226731 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.191826 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses system.cpu.icache.overall_misses 704 # number of overall misses system.cpu.icache.overall_misses_0 704 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 88 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 88 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 85 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 85 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4769500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 4769500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 4782500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 4782500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.198390 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.168665 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 616 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 616 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -378,107 +378,107 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 6 # number of replacements -system.cpu.icache.replacements_0 6 # number of replacements +system.cpu.icache.replacements 7 # number of replacements +system.cpu.icache.replacements_0 7 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 616 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 313.697202 # Cycle average of tags in use -system.cpu.icache.total_refs 2401 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 335.078862 # Cycle average of tags in use +system.cpu.icache.total_refs 2966 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 51 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2444 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1228 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1216 # Number of branches executed -system.cpu.iew.EXEC:nop 128 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 67 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 61 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.267070 # Inst execution rate -system.cpu.iew.EXEC:refs 5219 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2580 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2639 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1956 # Number of stores executed -system.cpu.iew.EXEC:stores_0 977 # Number of stores executed -system.cpu.iew.EXEC:stores_1 979 # Number of stores executed +system.cpu.idleCycles 46 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2896 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1452 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1444 # Number of branches executed +system.cpu.iew.EXEC:nop 125 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 66 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 59 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.282811 # Inst execution rate +system.cpu.iew.EXEC:refs 5961 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2937 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 3024 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2102 # Number of stores executed +system.cpu.iew.EXEC:stores_0 1047 # Number of stores executed +system.cpu.iew.EXEC:stores_1 1055 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10432 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5228 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5204 # num instructions consuming a value -system.cpu.iew.WB:count 15495 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7763 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7732 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 1.540838 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.769893 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.770945 # average fanout of values written-back +system.cpu.iew.WB:consumers 11655 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5835 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5820 # num instructions consuming a value +system.cpu.iew.WB:count 17454 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 8729 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 8725 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.541828 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.770865 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.770962 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 8037 # num instructions producing a value -system.cpu.iew.WB:producers_0 4025 # num instructions producing a value -system.cpu.iew.WB:producers_1 4012 # num instructions producing a value -system.cpu.iew.WB:rate 1.217490 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.609963 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.607527 # insts written-back per cycle -system.cpu.iew.WB:sent 15706 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7855 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7851 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1023 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 34 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4011 # Number of dispatched load instructions +system.cpu.iew.WB:producers 8985 # num instructions producing a value +system.cpu.iew.WB:producers_0 4498 # num instructions producing a value +system.cpu.iew.WB:producers_1 4487 # num instructions producing a value +system.cpu.iew.WB:rate 1.231583 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.615933 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.615651 # insts written-back per cycle +system.cpu.iew.WB:sent 17676 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 8819 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 8857 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1177 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 39 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4611 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 445 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2321 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 19928 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3263 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1603 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1660 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 892 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 16126 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 648 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2565 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 22432 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3859 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1890 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1969 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1127 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 18180 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 18 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1667 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1860 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 44 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 66 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 67 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 996 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 351 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1089 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 405 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 53 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 67 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 70 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1057 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 346 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 133 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 810 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 213 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.441817 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.441895 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.883712 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8497 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 1186 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 436 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 137 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 227 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.444327 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.444397 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.888724 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9630 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5747 67.64% # Type of FU issued + IntAlu 6491 67.40% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +487,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1738 20.45% # Type of FU issued - MemWrite 1007 11.85% # Type of FU issued + MemRead 2024 21.02% # Type of FU issued + MemWrite 1110 11.53% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8521 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 9677 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5702 66.92% # Type of FU issued + IntAlu 6446 66.61% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +504,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1797 21.09% # Type of FU issued - MemWrite 1017 11.94% # Type of FU issued + MemRead 2105 21.75% # Type of FU issued + MemWrite 1121 11.58% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 17018 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 19307 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist No_OpClass 4 0.02% # Type of FU issued - IntAlu 11449 67.28% # Type of FU issued + IntAlu 12937 67.01% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +521,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3535 20.77% # Type of FU issued - MemWrite 2024 11.89% # Type of FU issued + MemRead 4129 21.39% # Type of FU issued + MemWrite 2231 11.56% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 180 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 83 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 97 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010577 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.004877 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.005700 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 191 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 103 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009893 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.004558 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.005335 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 9 5.00% # attempts to use FU when none available + IntAlu 10 5.24% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,107 +543,107 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 107 59.44% # attempts to use FU when none available - MemWrite 64 35.56% # attempts to use FU when none available + MemRead 116 60.73% # attempts to use FU when none available + MemWrite 65 34.03% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 12676 +system.cpu.iq.ISSUE:issued_per_cycle.samples 14126 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 6060 4780.69% - 1 2068 1631.43% - 2 1684 1328.49% - 3 1173 925.37% - 4 835 658.73% - 5 514 405.49% - 6 255 201.17% - 7 73 57.59% - 8 14 11.04% + 0 6647 4705.51% + 1 2379 1684.13% + 2 1804 1277.08% + 3 1327 939.40% + 4 983 695.88% + 5 624 441.74% + 6 265 187.60% + 7 79 55.93% + 8 18 12.74% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.337157 # Inst issue rate -system.cpu.iq.iqInstsAdded 19755 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 17018 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.362334 # Inst issue rate +system.cpu.iq.iqInstsAdded 22262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 19307 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 7576 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8627 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4636 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 3160 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 5151 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 3720 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 3105 # ITB hits -system.cpu.itb.misses 55 # ITB misses +system.cpu.itb.hits 3670 # ITB hits +system.cpu.itb.misses 50 # ITB misses system.cpu.l2cache.ReadExReq_accesses 145 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses_0 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency_0 6844.827586 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 3844.827586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 992500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency_0 992500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency_0 6824.137931 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 3824.137931 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 989500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency_0 989500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 145 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses_0 145 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 557500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 557500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 554500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 554500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 145 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses_0 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 813 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 813 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency_0 6525.277435 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3525.277435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 5292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 5292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate_0 0.997540 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_accesses 814 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 814 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 6515.413070 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3515.413070 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 5284000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 5284000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.996314 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 811 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses_0 811 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2859000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2859000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997540 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency 2851000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2851000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.996314 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 811 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses_0 811 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 29 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses_0 29 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 6103.448276 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 3103.448276 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 177000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency_0 177000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 6344.827586 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 3344.827586 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 184000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency_0 184000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 29 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses_0 29 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 90000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 90000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 97000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 29 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses_0 29 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002558 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.003836 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 958 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 958 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 959 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 959 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 6573.744770 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 6562.238494 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3573.744770 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3562.238494 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6284500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 6284500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 6273500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 6273500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.997912 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.996872 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses system.cpu.l2cache.demand_misses 956 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_0 956 # number of demand (read+write) misses @@ -651,11 +651,11 @@ system.cpu.l2cache.demand_misses_1 0 # nu system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3416500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 3416500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 3405500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 3405500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.997912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.996872 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 956 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_0 956 # number of demand (read+write) MSHR misses @@ -665,26 +665,26 @@ system.cpu.l2cache.mshr_cap_events 0 # nu system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 958 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 958 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 959 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 959 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 6573.744770 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 6562.238494 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3573.744770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3562.238494 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_hits_0 2 # number of overall hits +system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_hits_0 3 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6284500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 6284500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 6273500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 6273500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.997912 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.996872 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses system.cpu.l2cache.overall_misses 956 # number of overall misses system.cpu.l2cache.overall_misses_0 956 # number of overall misses @@ -692,11 +692,11 @@ system.cpu.l2cache.overall_misses_1 0 # nu system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3416500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 3416500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3405500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 3405500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.997912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.996872 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 956 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_0 956 # number of overall MSHR misses @@ -723,29 +723,30 @@ system.cpu.l2cache.sampled_refs 782 # Sa system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 419.781607 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 444.416250 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 12727 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 743 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 17661 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 854 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 27553 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21741 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 16306 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3686 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1667 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 906 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8204 # Number of HB maps that are undone due to squashing +system.cpu.numCycles 14172 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 760 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 9074 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 19739 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 868 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 30813 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 24390 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 18197 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4242 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1860 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 926 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 9123 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 509 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2494 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 2524 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 15 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 1b77a8f81..1c27475d4 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:12:59 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 15:48:11 +M5 started Wed Jul 23 15:49:40 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! Hello world! -Exiting @ tick 6363000 because target called exit() +Exiting @ tick 7085500 because target called exit() |