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authorNathan Binkert <nate@binkert.org>2011-04-22 10:18:51 -0700
committerNathan Binkert <nate@binkert.org>2011-04-22 10:18:51 -0700
commita7e27f9a82300f213b268264e1dede222d26bd4d (patch)
tree905f84d6e06111d4a243c18a1899e932646bdced /tests/quick/01.hello-2T-smt/ref/alpha/linux
parent2342aa2ebbb9dfe232eafcd20f01a8dd95ebfcc0 (diff)
downloadgem5-a7e27f9a82300f213b268264e1dede222d26bd4d.tar.xz
tests: updates for stat name change
Diffstat (limited to 'tests/quick/01.hello-2T-smt/ref/alpha/linux')
-rwxr-xr-xtests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout4
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt48
2 files changed, 26 insertions, 26 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index 138b08408..5cdcc3460 100755
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 12:00:40
+M5 compiled Apr 21 2011 12:29:56
+M5 started Apr 21 2011 13:15:44
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 93b62df2d..fe96eb65d 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 136040 # Simulator instruction rate (inst/s)
-host_mem_usage 204288 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
-host_tick_rate 149415554 # Simulator tick rate (ticks/s)
+host_inst_rate 78127 # Simulator instruction rate (inst/s)
+host_mem_usage 207556 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
+host_tick_rate 85893759 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 12773 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
@@ -388,26 +388,26 @@ system.cpu.iew.iewIdleCycles 0 # Nu
system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1971 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 56 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 15 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1178 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 386 # Number of stores squashed
-system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.1.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.1.memOrderViolation 13 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.1.squashedLoads 1143 # Number of loads squashed
-system.cpu.iew.lsq.thread.1.squashedStores 334 # Number of stores squashed
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.forwLoads 56 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.squashedLoads 1178 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedStores 386 # Number of stores squashed
+system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads 55 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread1.squashedLoads 1143 # Number of loads squashed
+system.cpu.iew.lsq.thread1.squashedStores 334 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1056 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 257 # Number of branches that were predicted taken incorrectly