diff options
| author | Nathan Binkert <nate@binkert.org> | 2009-04-22 10:25:17 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-04-22 10:25:17 -0700 |
| commit | 567cab685965e4e627ac1541a9fdacb93fd6e5fe (patch) | |
| tree | d79f8cfd677dfc314ccb48630b77785412a9f1bd /tests/quick/01.hello-2T-smt/ref/alpha/linux | |
| parent | ca3d82b38ab92114f5056a35bacf0dceb8b6d4a6 (diff) | |
| download | gem5-567cab685965e4e627ac1541a9fdacb93fd6e5fe.tar.xz | |
stats: update reference outputs now that compatibility is gone
Because of the initialization bug, it wasn't consistent anyway.
Diffstat (limited to 'tests/quick/01.hello-2T-smt/ref/alpha/linux')
| -rwxr-xr-x | tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt | 1072 |
2 files changed, 536 insertions, 544 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index a796d7912..7545f2cff 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:39:11 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:17:23 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 06def78dc..3a5ef660d 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 75551 # Simulator instruction rate (inst/s) -host_mem_usage 201440 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 84168035 # Simulator tick rate (ticks/s) +host_inst_rate 105048 # Simulator instruction rate (inst/s) +host_mem_usage 203136 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 116961296 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -16,13 +16,13 @@ system.cpu.BPredUnit.condIncorrect 1595 # Nu system.cpu.BPredUnit.condPredicted 3153 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 5548 # Number of BP lookups system.cpu.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 2102 # Number of branches committed -system.cpu.commit.COM:branches_0 1051 # Number of branches committed -system.cpu.commit.COM:branches_1 1051 # Number of branches committed +system.cpu.commit.COM:branches::0 1051 # Number of branches committed +system.cpu.commit.COM:branches::1 1051 # Number of branches committed +system.cpu.commit.COM:branches::total 2102 # Number of branches committed system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited::0 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited::1 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited::total 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle::samples 22838 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle @@ -40,168 +40,168 @@ system.cpu.commit.COM:committed_per_cycle::total 22838 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::mean 0.560776 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 1.272228 # Number of insts commited each cycle -system.cpu.commit.COM:count 12807 # Number of instructions committed -system.cpu.commit.COM:count_0 6403 # Number of instructions committed -system.cpu.commit.COM:count_1 6404 # Number of instructions committed -system.cpu.commit.COM:loads 2370 # Number of loads committed -system.cpu.commit.COM:loads_0 1185 # Number of loads committed -system.cpu.commit.COM:loads_1 1185 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed -system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 4100 # Number of memory references committed -system.cpu.commit.COM:refs_0 2050 # Number of memory references committed -system.cpu.commit.COM:refs_1 2050 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed -system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed +system.cpu.commit.COM:count::0 6403 # Number of instructions committed +system.cpu.commit.COM:count::1 6404 # Number of instructions committed +system.cpu.commit.COM:count::total 12807 # Number of instructions committed +system.cpu.commit.COM:loads::0 1185 # Number of loads committed +system.cpu.commit.COM:loads::1 1185 # Number of loads committed +system.cpu.commit.COM:loads::total 2370 # Number of loads committed +system.cpu.commit.COM:membars::0 0 # Number of memory barriers committed +system.cpu.commit.COM:membars::1 0 # Number of memory barriers committed +system.cpu.commit.COM:membars::total 0 # Number of memory barriers committed +system.cpu.commit.COM:refs::0 2050 # Number of memory references committed +system.cpu.commit.COM:refs::1 2050 # Number of memory references committed +system.cpu.commit.COM:refs::total 4100 # Number of memory references committed +system.cpu.commit.COM:swp_count::0 0 # Number of s/w prefetches committed +system.cpu.commit.COM:swp_count::1 0 # Number of s/w prefetches committed +system.cpu.commit.COM:swp_count::total 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 6386 # Number of Instructions Simulated -system.cpu.committedInsts_1 6387 # Number of Instructions Simulated +system.cpu.committedInsts::0 6386 # Number of Instructions Simulated +system.cpu.committedInsts::1 6387 # Number of Instructions Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi_0 4.463514 # CPI: Cycles Per Instruction -system.cpu.cpi_1 4.462815 # CPI: Cycles Per Instruction +system.cpu.cpi::0 4.463514 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.462815 # CPI: Cycles Per Instruction system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3925 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 35473.913043 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36849.514563 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3580 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 3580 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12238500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 12238500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.087898 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 345 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 345 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 7591000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052484 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 206 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 206 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_0 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 33703.947368 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36103.448276 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 970 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 25615000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 25615000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate_0 0.439306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 760 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 6282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_accesses::0 3925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 35473.913043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36849.514563 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::0 3580 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3580 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::0 12238500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12238500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.087898 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 345 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 345 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::0 139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::0 7591000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7591000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.052484 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::0 206 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 206 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 33703.947368 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36103.448276 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::0 970 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 970 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::0 25615000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25615000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.439306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 760 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 760 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::0 586 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 586 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::0 6282000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6282000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.100578 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::0 174 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 174 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 5655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 34256.561086 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 4550 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 4550 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 37853500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 37853500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.195402 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 1105 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 1105 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 725 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 725 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13873000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 13873000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.067197 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 380 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 380 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses::0 5655 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5655 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 34256.561086 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 4550 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4550 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::0 37853500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 37853500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.195402 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 1105 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1105 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::0 725 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 725 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::0 13873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.067197 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::0 380 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 5655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 5655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 34256.561086 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4550 # number of overall hits -system.cpu.dcache.overall_hits_0 4550 # number of overall hits -system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 37853500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 37853500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.195402 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 1105 # number of overall misses -system.cpu.dcache.overall_misses_0 1105 # number of overall misses -system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 725 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 725 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13873000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 13873000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.067197 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 380 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 380 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.replacements_0 0 # number of replacements -system.cpu.dcache.replacements_1 0 # number of replacements +system.cpu.dcache.overall_accesses::0 5655 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5655 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 34256.561086 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits::0 4550 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 4550 # number of overall hits +system.cpu.dcache.overall_miss_latency::0 37853500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 37853500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.195402 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 1105 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 1105 # number of overall misses +system.cpu.dcache.overall_mshr_hits::0 725 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 725 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::0 13873000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13873000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.067197 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::0 380 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 380 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements::0 0 # number of replacements +system.cpu.dcache.replacements::1 0 # number of replacements +system.cpu.dcache.replacements::total 0 # number of replacements system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.writebacks_0 0 # number of writebacks -system.cpu.dcache.writebacks_1 0 # number of writebacks +system.cpu.dcache.writebacks::0 0 # number of writebacks +system.cpu.dcache.writebacks::1 0 # number of writebacks +system.cpu.dcache.writebacks::total 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 5063 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch @@ -254,166 +254,166 @@ system.cpu.fetch.rateDist::total 22904 # Nu system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.351249 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.742840 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 4113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 35793.697979 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35516.155089 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3272 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 3272 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 30102500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 30102500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.204474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 841 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 841 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 222 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 21984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 21984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.150498 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.ReadReq_accesses::0 4113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 35793.697979 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35516.155089 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 3272 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3272 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::0 30102500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30102500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.204474 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 841 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 841 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits::0 222 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency::0 21984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.150498 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::0 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 619 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4113 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 4113 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 35793.697979 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 3272 # number of demand (read+write) hits -system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 30102500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 30102500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.204474 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 841 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 841 # number of demand (read+write) misses -system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 222 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 21984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 21984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.150498 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses::0 4113 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4113 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 35793.697979 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.icache.demand_hits::0 3272 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3272 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::0 30102500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30102500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.204474 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 841 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 841 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits::0 222 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 222 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency::0 21984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.150498 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::0 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 619 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated -system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 4113 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 35793.697979 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3272 # number of overall hits -system.cpu.icache.overall_hits_0 3272 # number of overall hits -system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 30102500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 30102500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.204474 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_misses 841 # number of overall misses -system.cpu.icache.overall_misses_0 841 # number of overall misses -system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 222 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 21984500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 21984500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.150498 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 6 # number of replacements -system.cpu.icache.replacements_0 6 # number of replacements -system.cpu.icache.replacements_1 0 # number of replacements +system.cpu.icache.overall_accesses::0 4113 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4113 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 35793.697979 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits::0 3272 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 3272 # number of overall hits +system.cpu.icache.overall_miss_latency::0 30102500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30102500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.204474 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 841 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 841 # number of overall misses +system.cpu.icache.overall_mshr_hits::0 222 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 222 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency::0 21984500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21984500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.150498 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::0 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements::0 6 # number of replacements +system.cpu.icache.replacements::1 0 # number of replacements +system.cpu.icache.replacements::total 6 # number of replacements system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use system.cpu.icache.total_refs 3272 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.writebacks_0 0 # number of writebacks -system.cpu.icache.writebacks_1 0 # number of writebacks +system.cpu.icache.writebacks::0 0 # number of writebacks +system.cpu.icache.writebacks::1 0 # number of writebacks +system.cpu.icache.writebacks::total 0 # number of writebacks system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3160 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1573 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1587 # Number of branches executed -system.cpu.iew.EXEC:nop 135 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 70 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 65 # number of nop insts executed +system.cpu.iew.EXEC:branches::0 1573 # Number of branches executed +system.cpu.iew.EXEC:branches::1 1587 # Number of branches executed +system.cpu.iew.EXEC:branches::total 3160 # Number of branches executed +system.cpu.iew.EXEC:nop::0 70 # number of nop insts executed +system.cpu.iew.EXEC:nop::1 65 # number of nop insts executed +system.cpu.iew.EXEC:nop::total 135 # number of nop insts executed system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate -system.cpu.iew.EXEC:refs 6321 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 3132 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 3189 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2175 # Number of stores executed -system.cpu.iew.EXEC:stores_0 1090 # Number of stores executed -system.cpu.iew.EXEC:stores_1 1085 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed -system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 11901 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5984 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5917 # num instructions consuming a value -system.cpu.iew.WB:count 18426 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 9221 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 9205 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 1.552811 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.776404 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.776407 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 9240 # num instructions producing a value -system.cpu.iew.WB:producers_0 4646 # num instructions producing a value -system.cpu.iew.WB:producers_1 4594 # num instructions producing a value -system.cpu.iew.WB:rate 0.646436 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.323498 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.322937 # insts written-back per cycle -system.cpu.iew.WB:sent 18664 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 9324 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 9340 # cumulative count of insts sent to commit +system.cpu.iew.EXEC:refs::0 3132 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::1 3189 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::total 6321 # number of memory reference insts executed +system.cpu.iew.EXEC:stores::0 1090 # Number of stores executed +system.cpu.iew.EXEC:stores::1 1085 # Number of stores executed +system.cpu.iew.EXEC:stores::total 2175 # Number of stores executed +system.cpu.iew.EXEC:swp::0 0 # number of swp insts executed +system.cpu.iew.EXEC:swp::1 0 # number of swp insts executed +system.cpu.iew.EXEC:swp::total 0 # number of swp insts executed +system.cpu.iew.WB:consumers::0 5984 # num instructions consuming a value +system.cpu.iew.WB:consumers::1 5917 # num instructions consuming a value +system.cpu.iew.WB:consumers::total 11901 # num instructions consuming a value +system.cpu.iew.WB:count::0 9221 # cumulative count of insts written-back +system.cpu.iew.WB:count::1 9205 # cumulative count of insts written-back +system.cpu.iew.WB:count::total 18426 # cumulative count of insts written-back +system.cpu.iew.WB:fanout::0 0.776404 # average fanout of values written-back +system.cpu.iew.WB:fanout::1 0.776407 # average fanout of values written-back +system.cpu.iew.WB:fanout::total 1.552811 # average fanout of values written-back +system.cpu.iew.WB:penalized::0 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized::1 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized::total 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers::0 4646 # num instructions producing a value +system.cpu.iew.WB:producers::1 4594 # num instructions producing a value +system.cpu.iew.WB:producers::total 9240 # num instructions producing a value +system.cpu.iew.WB:rate::0 0.323498 # insts written-back per cycle +system.cpu.iew.WB:rate::1 0.322937 # insts written-back per cycle +system.cpu.iew.WB:rate::total 0.646436 # insts written-back per cycle +system.cpu.iew.WB:sent::0 9324 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::1 9340 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::total 18664 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions @@ -421,9 +421,9 @@ system.cpu.iew.iewDispNonSpecInsts 44 # Nu system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 4146 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 2042 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 2104 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::0 2042 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2104 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4146 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall @@ -454,99 +454,91 @@ system.cpu.iew.lsq.thread.1.squashedStores 438 # system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.224039 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.224074 # IPC: Instructions Per Cycle +system.cpu.ipc::0 0.224039 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.224074 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 10179 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 2 0.02% # Type of FU issued - IntAlu 6830 67.10% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 2173 21.35% # Type of FU issued - MemWrite 1171 11.50% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 10211 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1.start_dist - No_OpClass 2 0.02% # Type of FU issued - IntAlu 6842 67.01% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 2230 21.84% # Type of FU issued - MemWrite 1134 11.11% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 20390 # Type of FU issued -system.cpu.iq.ISSUE:FU_type.start_dist - No_OpClass 4 0.02% # Type of FU issued - IntAlu 13672 67.05% # Type of FU issued - IntMult 2 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 4 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 4403 21.59% # Type of FU issued - MemWrite 2305 11.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 172 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 87 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 85 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.008436 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.004267 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.004169 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 13 7.56% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 96 55.81% # attempts to use FU when none available - MemWrite 63 36.63% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 22904 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 14156 61.81% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 3289 14.36% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 2351 10.26% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 1373 5.99% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 854 3.73% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 535 2.34% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 261 1.14% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 57 0.25% -system.cpu.iq.ISSUE:issued_per_cycle::8 28 0.12% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 22904 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.890238 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.446450 +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6830 67.10% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2173 21.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1171 11.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 10179 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::No_OpClass 2 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntAlu 6842 67.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemRead 2230 21.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemWrite 1134 11.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::total 10211 # Type of FU issued +system.cpu.iq.ISSUE:FU_type::No_OpClass 4 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntAlu 13672 67.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemRead 4403 21.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemWrite 2305 11.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::total 20390 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt::0 87 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::1 85 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::total 172 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate::0 0.004267 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::1 0.004169 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::total 0.008436 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 13 7.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 96 55.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 63 36.63% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 22904 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 14156 61.81% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 3289 14.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 2351 10.26% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 1373 5.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 854 3.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 535 2.34% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 261 1.14% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 57 0.25% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 28 0.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 22904 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.890238 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.446450 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued @@ -571,151 +563,151 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34643.835616 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31589.041096 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency_0 5058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4612000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4612000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 825 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency_0 34555.285541 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31414.337789 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 28439000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 28439000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate_0 0.997576 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 823 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 25854000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25854000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997576 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 823 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 823 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34482.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31357.142857 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 965500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency_0 965500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 878000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 878000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6750 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_accesses::0 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31589.041096 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency::0 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::0 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4612000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4612000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::0 825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::0 34555.285541 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31414.337789 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::0 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::0 28439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::0 0.997576 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::0 823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997576 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::0 823 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses::0 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34482.142857 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31357.142857 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency::0 965500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 965500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses::0 28 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 28 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 878000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 878000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses::0 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 4 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 27000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 971 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 34568.627451 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 33497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 33497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.997940 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 969 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 30466000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 30466000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.997940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 969 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 969 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses::0 971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::0 34568.627451 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.l2cache.demand_hits::0 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::0 33497000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33497000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::0 0.997940 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.l2cache.demand_misses::0 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::0 30466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::0 0.997940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::0 969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 969 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 971 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 34568.627451 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_hits_0 2 # number of overall hits -system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 33497000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 33497000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.997940 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_misses 969 # number of overall misses -system.cpu.l2cache.overall_misses_0 969 # number of overall misses -system.cpu.l2cache.overall_misses_1 0 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 30466000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 30466000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.997940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 969 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 969 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.replacements_0 0 # number of replacements -system.cpu.l2cache.replacements_1 0 # number of replacements +system.cpu.l2cache.overall_accesses::0 971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::0 34568.627451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits::0 2 # number of overall hits +system.cpu.l2cache.overall_hits::1 0 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency::0 33497000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33497000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::0 0.997940 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.l2cache.overall_misses::0 969 # number of overall misses +system.cpu.l2cache.overall_misses::1 0 # number of overall misses +system.cpu.l2cache.overall_misses::total 969 # number of overall misses +system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency::0 30466000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30466000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::0 0.997940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::0 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements::0 0 # number of replacements +system.cpu.l2cache.replacements::1 0 # number of replacements +system.cpu.l2cache.replacements::total 0 # number of replacements system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.writebacks_0 0 # number of writebacks -system.cpu.l2cache.writebacks_1 0 # number of writebacks +system.cpu.l2cache.writebacks::0 0 # number of writebacks +system.cpu.l2cache.writebacks::1 0 # number of writebacks +system.cpu.l2cache.writebacks::total 0 # number of writebacks system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. |