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authorKevin Lim <ktlim@umich.edu>2007-03-25 01:05:48 -0400
committerKevin Lim <ktlim@umich.edu>2007-03-25 01:05:48 -0400
commit4e0ec56868d313d21385c5550e5ceba79268151f (patch)
tree212c45ccb5db25c9fac78d4f58f5d893c59312dd /tests/quick/01.hello-2T-smt/ref
parent5c044cf1f63a2b6c280a2f479f6264b89662d0d5 (diff)
downloadgem5-4e0ec56868d313d21385c5550e5ceba79268151f.tar.xz
Update stats for changes.
--HG-- extra : convert_revision : a24c4cd7e2fcd732f5da5679f0c0fbf205f22815
Diffstat (limited to 'tests/quick/01.hello-2T-smt/ref')
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini53
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out54
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt746
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr6
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout11
5 files changed, 387 insertions, 483 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 6eef745b4..e75a10c54 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -1,48 +1,7 @@
[root]
type=Root
children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
+dummy=0
[system]
type=System
@@ -70,6 +29,7 @@ commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
+cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
@@ -433,12 +393,3 @@ range=0:134217727
zero=false
port=system.membus.port[0]
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out
index f36f666af..9489e27c0 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out
@@ -1,9 +1,6 @@
[root]
type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
+dummy=0
[system.physmem]
type=PhysicalMemory
@@ -189,6 +186,7 @@ type=DerivO3CPU
clock=1
phase=0
numThreads=1
+cpu_id=0
activity=0
workload=system.cpu.workload0 system.cpu.workload1
checker=null
@@ -383,51 +381,3 @@ clock=1000
width=64
responder_set=false
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
index bb9e9360c..74e8f8d83 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
@@ -1,48 +1,48 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 1334 # Number of BTB hits
-global.BPredUnit.BTBLookups 6012 # Number of BTB lookups
+global.BPredUnit.BTBHits 1320 # Number of BTB hits
+global.BPredUnit.BTBLookups 6181 # Number of BTB lookups
global.BPredUnit.RASInCorrect 173 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 1201 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 4031 # Number of conditional branches predicted
-global.BPredUnit.lookups 12370 # Number of BP lookups
-global.BPredUnit.usedRAS 6337 # Number of times the RAS was used to get a target.
-host_inst_rate 11366 # Simulator instruction rate (inst/s)
-host_mem_usage 178064 # Number of bytes of host memory used
-host_seconds 0.99 # Real time elapsed on the host
-host_tick_rate 2259917 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 27 # Number of conflicting loads.
-memdepunit.memDep.conflictingLoads 20 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 97 # Number of conflicting stores.
-memdepunit.memDep.conflictingStores 3 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 5749 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedLoads 2822 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 4490 # Number of stores inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1747 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.condIncorrect 1181 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 4228 # Number of conditional branches predicted
+global.BPredUnit.lookups 12535 # Number of BP lookups
+global.BPredUnit.usedRAS 6333 # Number of times the RAS was used to get a target.
+host_inst_rate 6990 # Simulator instruction rate (inst/s)
+host_mem_usage 156628 # Number of bytes of host memory used
+host_seconds 1.61 # Real time elapsed on the host
+host_tick_rate 1386962 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads.
+memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 4 # Number of conflicting stores.
+memdepunit.memDep.conflictingStores 1 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 3657 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 5285 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1780 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 4439 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 11247 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated
-sim_ticks 2237162 # Number of ticks simulated
+sim_ticks 2232164 # Number of ticks simulated
system.cpu.commit.COM:branches 1724 # Number of branches committed
system.cpu.commit.COM:branches_0 862 # Number of branches committed
system.cpu.commit.COM:branches_1 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 128 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 123 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 188940
+system.cpu.commit.COM:committed_per_cycle.samples 189138
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 183303 9701.65%
- 1 3121 165.18%
- 2 1239 65.58%
- 3 531 28.10%
- 4 275 14.55%
- 5 154 8.15%
- 6 128 6.77%
+ 0 183476 9700.64%
+ 1 3161 167.13%
+ 2 1212 64.08%
+ 3 544 28.76%
+ 4 279 14.75%
+ 5 155 8.20%
+ 6 127 6.71%
7 61 3.23%
- 8 128 6.77%
+ 8 123 6.50%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -61,97 +61,97 @@ system.cpu.commit.COM:refs_1 1791 # Nu
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 943 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 938 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 28509 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 29588 # The number of squashed insts skipped by commit
system.cpu.committedInsts_0 5624 # Number of Instructions Simulated
system.cpu.committedInsts_1 5623 # Number of Instructions Simulated
system.cpu.committedInsts_total 11247 # Number of Instructions Simulated
-system.cpu.cpi_0 397.788407 # CPI: Cycles Per Instruction
-system.cpu.cpi_1 397.859150 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 198.911888 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 3186 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses_0 3186 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 9969.378125 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency_0 9969.378125 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10500.608040 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10500.608040 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 2866 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits_0 2866 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3190201 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency_0 3190201 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.100439 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate_0 0.100439 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 320 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses_0 320 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits_0 121 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2089621 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency_0 2089621 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.062461 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.062461 # mshr miss rate for ReadReq accesses
+system.cpu.cpi_0 396.899716 # CPI: Cycles Per Instruction
+system.cpu.cpi_1 396.970301 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 198.467502 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 3176 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses_0 3176 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 9976.257143 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency_0 9976.257143 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10425.356784 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10425.356784 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 2861 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits_0 2861 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3142521 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency_0 3142521 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.099181 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate_0 0.099181 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses_0 315 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 116 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits_0 116 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2074646 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency_0 2074646 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.062657 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.062657 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 199 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses_0 199 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 6540.875740 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency_0 6540.875740 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7803.746575 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 7803.746575 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 6512.846154 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency_0 6512.846154 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7776.006849 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 7776.006849 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 1117 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits_0 1117 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3316224 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency_0 3316224 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 3302013 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency_0 3302013 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.312192 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate_0 0.312192 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 507 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses_0 507 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 361 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits_0 361 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 1139347 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency_0 1139347 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 1135297 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency_0 1135297 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.089901 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 146 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses_0 146 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 3973 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 3625.380952 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.544928 # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles_no_targets 3613.488095 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 11.563953 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 84 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 3973 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 304532 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 303533 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 4810 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses_0 4810 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 4800 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses_0 4800 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 7867.503023 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency_0 7867.503023 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency 7840.065693 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency_0 7840.065693 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 9359.327536 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency_0 9359.327536 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 9304.182609 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency_0 9304.182609 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_hits 3983 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits_0 3983 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits 3978 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits_0 3978 # number of demand (read+write) hits
system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 6506425 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency_0 6506425 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 6444534 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency_0 6444534 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.171933 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate_0 0.171933 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate 0.171250 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate_0 0.171250 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.dcache.demand_misses 827 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses_0 827 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses 822 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses_0 822 # number of demand (read+write) misses
system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 482 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits_0 482 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits 477 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits_0 477 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3228968 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency_0 3228968 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 3209943 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency_0 3209943 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.071726 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate_0 0.071726 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.071875 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate_0 0.071875 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses_0 345 # number of demand (read+write) MSHR misses
@@ -161,38 +161,38 @@ system.cpu.dcache.mshr_cap_events 0 # nu
system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 4810 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses_0 4810 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses 4800 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses_0 4800 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 7867.503023 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency_0 7867.503023 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 7840.065693 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency_0 7840.065693 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 9359.327536 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency_0 9359.327536 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 9304.182609 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency_0 9304.182609 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 3983 # number of overall hits
-system.cpu.dcache.overall_hits_0 3983 # number of overall hits
+system.cpu.dcache.overall_hits 3978 # number of overall hits
+system.cpu.dcache.overall_hits_0 3978 # number of overall hits
system.cpu.dcache.overall_hits_1 0 # number of overall hits
-system.cpu.dcache.overall_miss_latency 6506425 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency_0 6506425 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 6444534 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency_0 6444534 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.171933 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate_0 0.171933 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate 0.171250 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate_0 0.171250 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.dcache.overall_misses 827 # number of overall misses
-system.cpu.dcache.overall_misses_0 827 # number of overall misses
+system.cpu.dcache.overall_misses 822 # number of overall misses
+system.cpu.dcache.overall_misses_0 822 # number of overall misses
system.cpu.dcache.overall_misses_1 0 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 482 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits_0 482 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits 477 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits_0 477 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3228968 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency_0 3228968 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 3209943 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency_0 3209943 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.071726 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate_0 0.071726 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.071875 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate_0 0.071875 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 345 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses_0 345 # number of overall MSHR misses
@@ -215,153 +215,153 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.replacements_0 0 # number of replacements
system.cpu.dcache.replacements_1 0 # number of replacements
-system.cpu.dcache.sampled_refs 345 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 344 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 198.670475 # Cycle average of tags in use
-system.cpu.dcache.total_refs 3983 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 198.340517 # Cycle average of tags in use
+system.cpu.dcache.total_refs 3978 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.writebacks_0 0 # number of writebacks
system.cpu.dcache.writebacks_1 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 97618 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 267 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 390 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 67048 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 262280 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 12122 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 5552 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 680 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 155 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 12370 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 13012 # Number of cache lines fetched
-system.cpu.fetch.Cycles 27804 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 800 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 79582 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 4833 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.065467 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 52787 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 7671 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.421180 # Number of inst fetches per cycle
+system.cpu.decode.DECODE:BlockedCycles 95932 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 257 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 378 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 68233 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 264032 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 12255 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 5733 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 618 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 167 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 12535 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 13184 # Number of cache lines fetched
+system.cpu.fetch.Cycles 28123 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 886 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 80687 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 4911 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.066271 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 53960 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 7653 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.426584 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 188950
+system.cpu.fetch.rateDist.samples 189147
system.cpu.fetch.rateDist.min_value 0
- 0 174142 9216.30%
- 1 378 20.01%
- 2 298 15.77%
- 3 3656 193.49%
- 4 2200 116.43%
- 5 1017 53.82%
- 6 974 51.55%
- 7 2369 125.38%
- 8 3916 207.25%
+ 0 174193 9209.40%
+ 1 369 19.51%
+ 2 281 14.86%
+ 3 3638 192.34%
+ 4 2283 120.70%
+ 5 1005 53.13%
+ 6 984 52.02%
+ 7 2371 125.35%
+ 8 4023 212.69%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 13010 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses_0 13010 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 7746.912281 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency_0 7746.912281 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 7155.055556 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7155.055556 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 12098 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits_0 12098 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 7065184 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency_0 7065184 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.070100 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate_0 0.070100 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_accesses 13182 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses_0 13182 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 7732.322368 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency_0 7732.322368 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 7128.205742 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7128.205742 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 12270 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits_0 12270 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 7051878 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency_0 7051878 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.069185 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate_0 0.069185 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 912 # number of ReadReq misses
system.cpu.icache.ReadReq_misses_0 912 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 282 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits_0 282 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 4507685 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency_0 4507685 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.048424 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate_0 0.048424 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 630 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses_0 630 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_hits 285 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits_0 285 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 4469385 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency_0 4469385 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.047565 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate_0 0.047565 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 627 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses_0 627 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 5648.647059 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 19.203175 # Average number of references to valid blocks.
+system.cpu.icache.avg_blocked_cycles_no_targets 5603.944444 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 19.569378 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 17 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 18 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 96027 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 100871 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 13010 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses_0 13010 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 13182 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses_0 13182 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 7746.912281 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency_0 7746.912281 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency 7732.322368 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency_0 7732.322368 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 7155.055556 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency_0 7155.055556 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 7128.205742 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency_0 7128.205742 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_hits 12098 # number of demand (read+write) hits
-system.cpu.icache.demand_hits_0 12098 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 12270 # number of demand (read+write) hits
+system.cpu.icache.demand_hits_0 12270 # number of demand (read+write) hits
system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 7065184 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency_0 7065184 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 7051878 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency_0 7051878 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.070100 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate_0 0.070100 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate 0.069185 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate_0 0.069185 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
system.cpu.icache.demand_misses 912 # number of demand (read+write) misses
system.cpu.icache.demand_misses_0 912 # number of demand (read+write) misses
system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits_0 282 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits 285 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits_0 285 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 4507685 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency_0 4507685 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 4469385 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency_0 4469385 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.048424 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate_0 0.048424 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate 0.047565 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate_0 0.047565 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 630 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses_0 630 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 627 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses_0 627 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 13010 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses_0 13010 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 13182 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses_0 13182 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 7746.912281 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency_0 7746.912281 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 7732.322368 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency_0 7732.322368 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 7155.055556 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency_0 7155.055556 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 7128.205742 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency_0 7128.205742 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 12098 # number of overall hits
-system.cpu.icache.overall_hits_0 12098 # number of overall hits
+system.cpu.icache.overall_hits 12270 # number of overall hits
+system.cpu.icache.overall_hits_0 12270 # number of overall hits
system.cpu.icache.overall_hits_1 0 # number of overall hits
-system.cpu.icache.overall_miss_latency 7065184 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency_0 7065184 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 7051878 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency_0 7051878 # number of overall miss cycles
system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.070100 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate_0 0.070100 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate 0.069185 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate_0 0.069185 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
system.cpu.icache.overall_misses 912 # number of overall misses
system.cpu.icache.overall_misses_0 912 # number of overall misses
system.cpu.icache.overall_misses_1 0 # number of overall misses
-system.cpu.icache.overall_mshr_hits 282 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits_0 282 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits 285 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits_0 285 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 4507685 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency_0 4507685 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 4469385 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency_0 4469385 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.048424 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate_0 0.048424 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate 0.047565 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate_0 0.047565 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 630 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses_0 630 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 627 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses_0 627 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
@@ -381,138 +381,138 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 6 # number of replacements
system.cpu.icache.replacements_0 6 # number of replacements
system.cpu.icache.replacements_1 0 # number of replacements
-system.cpu.icache.sampled_refs 630 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 289.377534 # Cycle average of tags in use
-system.cpu.icache.total_refs 12098 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 288.361956 # Cycle average of tags in use
+system.cpu.icache.total_refs 12270 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.writebacks_0 0 # number of writebacks
system.cpu.icache.writebacks_1 0 # number of writebacks
-system.cpu.idleCycles 2048213 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 4035 # Number of branches executed
-system.cpu.iew.EXEC:branches_0 2458 # Number of branches executed
-system.cpu.iew.EXEC:branches_1 1577 # Number of branches executed
+system.cpu.idleCycles 2043018 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 4024 # Number of branches executed
+system.cpu.iew.EXEC:branches_0 1569 # Number of branches executed
+system.cpu.iew.EXEC:branches_1 2455 # Number of branches executed
system.cpu.iew.EXEC:nop 84 # number of nop insts executed
system.cpu.iew.EXEC:nop_0 42 # number of nop insts executed
system.cpu.iew.EXEC:nop_1 42 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.142196 # Inst execution rate
-system.cpu.iew.EXEC:refs 10960 # number of memory reference insts executed
-system.cpu.iew.EXEC:refs_0 7253 # number of memory reference insts executed
-system.cpu.iew.EXEC:refs_1 3707 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 3812 # Number of stores executed
-system.cpu.iew.EXEC:stores_0 2509 # Number of stores executed
-system.cpu.iew.EXEC:stores_1 1303 # Number of stores executed
+system.cpu.iew.EXEC:rate 0.144523 # Inst execution rate
+system.cpu.iew.EXEC:refs 11361 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_0 4575 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_1 6786 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 3833 # Number of stores executed
+system.cpu.iew.EXEC:stores_0 1337 # Number of stores executed
+system.cpu.iew.EXEC:stores_1 2496 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed
system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 12377 # num instructions consuming a value
-system.cpu.iew.WB:consumers_0 6652 # num instructions consuming a value
-system.cpu.iew.WB:consumers_1 5725 # num instructions consuming a value
-system.cpu.iew.WB:count 22520 # cumulative count of insts written-back
-system.cpu.iew.WB:count_0 12790 # cumulative count of insts written-back
-system.cpu.iew.WB:count_1 9730 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.808516 # average fanout of values written-back
-system.cpu.iew.WB:fanout_0 0.819753 # average fanout of values written-back
-system.cpu.iew.WB:fanout_1 0.795459 # average fanout of values written-back
+system.cpu.iew.WB:consumers 12385 # num instructions consuming a value
+system.cpu.iew.WB:consumers_0 5750 # num instructions consuming a value
+system.cpu.iew.WB:consumers_1 6635 # num instructions consuming a value
+system.cpu.iew.WB:count 22604 # cumulative count of insts written-back
+system.cpu.iew.WB:count_0 10240 # cumulative count of insts written-back
+system.cpu.iew.WB:count_1 12364 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.811385 # average fanout of values written-back
+system.cpu.iew.WB:fanout_0 0.800522 # average fanout of values written-back
+system.cpu.iew.WB:fanout_1 0.820799 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 10007 # num instructions producing a value
-system.cpu.iew.WB:producers_0 5453 # num instructions producing a value
-system.cpu.iew.WB:producers_1 4554 # num instructions producing a value
-system.cpu.iew.WB:rate 0.119185 # insts written-back per cycle
-system.cpu.iew.WB:rate_0 0.067690 # insts written-back per cycle
-system.cpu.iew.WB:rate_1 0.051495 # insts written-back per cycle
-system.cpu.iew.WB:sent 22674 # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent_0 12874 # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent_1 9800 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 1030 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 62040 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 8571 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 5358 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 6237 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 39780 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 7148 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts_0 4744 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts_1 2404 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 26868 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 10049 # num instructions producing a value
+system.cpu.iew.WB:producers_0 4603 # num instructions producing a value
+system.cpu.iew.WB:producers_1 5446 # num instructions producing a value
+system.cpu.iew.WB:rate 0.119505 # insts written-back per cycle
+system.cpu.iew.WB:rate_0 0.054138 # insts written-back per cycle
+system.cpu.iew.WB:rate_1 0.065367 # insts written-back per cycle
+system.cpu.iew.WB:sent 22763 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_0 10322 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_1 12441 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 1027 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 60103 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 8942 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 5344 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 6219 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 40858 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 7528 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_0 3238 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_1 4290 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 872 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 27336 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 5552 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 117 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 3088 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 64 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 5733 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 122 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 1584 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 65 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 34 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 56 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 4770 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 3678 # Number of stores squashed
-system.cpu.iew.lsq.thread.1.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.1.cacheBlocked 756 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.1.forwLoads 64 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 2678 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 968 # Number of stores squashed
+system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.1.cacheBlocked 2643 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.1.forwLoads 67 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.1.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.1.memOrderViolation 29 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.1.memOrderViolation 54 # Number of memory ordering violations
system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.1.squashedLoads 1843 # Number of loads squashed
-system.cpu.iew.lsq.thread.1.squashedStores 935 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 798 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc_0 0.002514 # IPC: Instructions Per Cycle
-system.cpu.ipc_1 0.002513 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.005027 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 16536 # Type of FU issued
+system.cpu.iew.lsq.thread.1.squashedLoads 4306 # Number of loads squashed
+system.cpu.iew.lsq.thread.1.squashedStores 3627 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 110 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 796 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 231 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc_0 0.002520 # IPC: Instructions Per Cycle
+system.cpu.ipc_1 0.002519 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.005039 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 12578 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.01% # Type of FU issued
- IntAlu 9136 55.25% # Type of FU issued
+ (null) 2 0.02% # Type of FU issued
+ IntAlu 7865 62.53% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.01% # Type of FU issued
+ FloatAdd 2 0.02% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 4850 29.33% # Type of FU issued
- MemWrite 2545 15.39% # Type of FU issued
+ MemRead 3344 26.59% # Type of FU issued
+ MemWrite 1364 10.84% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:FU_type_1 11235 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_1 15630 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 7383 65.71% # Type of FU issued
+ (null) 2 0.01% # Type of FU issued
+ IntAlu 8707 55.71% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
+ FloatAdd 2 0.01% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 2518 22.41% # Type of FU issued
- MemWrite 1329 11.83% # Type of FU issued
+ MemRead 4394 28.11% # Type of FU issued
+ MemWrite 2524 16.15% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.end_dist
-system.cpu.iq.ISSUE:FU_type 27771 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type 28208 # Type of FU issued
system.cpu.iq.ISSUE:FU_type.start_dist
(null) 4 0.01% # Type of FU issued
- IntAlu 16519 59.48% # Type of FU issued
+ IntAlu 16572 58.75% # Type of FU issued
IntMult 2 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 4 0.01% # Type of FU issued
@@ -521,20 +521,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 7368 26.53% # Type of FU issued
- MemWrite 3874 13.95% # Type of FU issued
+ MemRead 7738 27.43% # Type of FU issued
+ MemWrite 3888 13.78% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 146 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt_0 73 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt_1 73 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.005257 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate_0 0.002629 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate_1 0.002629 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 149 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt_0 72 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt_1 77 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.005282 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_0 0.002552 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_1 0.002730 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 0 0.00% # attempts to use FU when none available
+ IntAlu 1 0.67% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -543,52 +543,52 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 83 56.85% # attempts to use FU when none available
- MemWrite 63 43.15% # attempts to use FU when none available
+ MemRead 83 55.70% # attempts to use FU when none available
+ MemWrite 65 43.62% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 188950
+system.cpu.iq.ISSUE:issued_per_cycle.samples 189147
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 174613 9241.23%
- 1 6958 368.25%
- 2 3428 181.42%
- 3 2696 142.68%
- 4 636 33.66%
- 5 439 23.23%
- 6 143 7.57%
- 7 24 1.27%
- 8 13 0.69%
+ 0 174626 9232.29%
+ 1 7072 373.89%
+ 2 3403 179.91%
+ 3 2709 143.22%
+ 4 713 37.70%
+ 5 443 23.42%
+ 6 143 7.56%
+ 7 26 1.37%
+ 8 12 0.63%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.146975 # Inst issue rate
-system.cpu.iq.iqInstsAdded 39654 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 27771 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 27426 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 20011 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 973 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses_0 973 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 6750.932169 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency_0 6750.932169 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 3603.773895 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3603.773895 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 6568657 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency_0 6568657 # number of ReadReq miss cycles
+system.cpu.iq.ISSUE:rate 0.149133 # Inst issue rate
+system.cpu.iq.iqInstsAdded 40733 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 28208 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 41 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 28495 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 192 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 21369 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 970 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses_0 970 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 6748.795876 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency_0 6748.795876 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 3604.818557 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3604.818557 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 6546332 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency_0 6546332 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate_0 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 973 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses_0 973 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 3506472 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency_0 3506472 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_misses 970 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses_0 970 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 3496674 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency_0 3496674 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate_0 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 973 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses_0 973 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses 970 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses_0 970 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
@@ -597,52 +597,52 @@ system.cpu.l2cache.blocked_no_targets 0 # nu
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 973 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses_0 973 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 970 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses_0 970 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 6750.932169 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency_0 6750.932169 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 6748.795876 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency_0 6748.795876 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 3603.773895 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3603.773895 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 3604.818557 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3604.818557 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits_0 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 6568657 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency_0 6568657 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 6546332 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency_0 6546332 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate_0 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 973 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses_0 973 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses 970 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses_0 970 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 3506472 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency_0 3506472 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 3496674 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency_0 3496674 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate_0 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 973 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses_0 973 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses 970 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses_0 970 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 973 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses_0 973 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses 970 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses_0 970 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 6750.932169 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency_0 6750.932169 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 6748.795876 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency_0 6748.795876 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 3603.773895 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3603.773895 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 3604.818557 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3604.818557 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
@@ -650,26 +650,26 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0>
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_hits_0 0 # number of overall hits
system.cpu.l2cache.overall_hits_1 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 6568657 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency_0 6568657 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 6546332 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency_0 6546332 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate_0 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 973 # number of overall misses
-system.cpu.l2cache.overall_misses_0 973 # number of overall misses
+system.cpu.l2cache.overall_misses 970 # number of overall misses
+system.cpu.l2cache.overall_misses_0 970 # number of overall misses
system.cpu.l2cache.overall_misses_1 0 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 3506472 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency_0 3506472 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 3496674 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency_0 3496674 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate_0 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 973 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses_0 973 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses 970 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses_0 970 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
@@ -689,35 +689,35 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.replacements_0 0 # number of replacements
system.cpu.l2cache.replacements_1 0 # number of replacements
-system.cpu.l2cache.sampled_refs 973 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 969 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 489.113488 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 487.752870 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.writebacks_0 0 # number of writebacks
system.cpu.l2cache.writebacks_1 0 # number of writebacks
-system.cpu.numCycles 188950 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 74870 # Number of cycles rename is blocking
+system.cpu.numCycles 189147 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 73147 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 21 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 263382 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 2455 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:IQFullEvents 24 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 265134 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 2520 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 31 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 72755 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 60875 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 44048 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 11047 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 5552 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 2536 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 35946 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 20340 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 51 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 4990 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed
-system.cpu.timesIdled 690 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:RenameLookups 74254 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 61970 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 45003 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 11202 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 5733 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 2584 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 36901 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 20319 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 5114 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed
+system.cpu.timesIdled 691 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr
index c36de0b79..d8ccd6207 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr
@@ -1,3 +1,5 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-0: system.remote_gdb.listener: listening for remote gdb on port 7001
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
warn: Entering event queue @ 0. Starting simulation...
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
index f07a960f8..30a45522d 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
@@ -7,8 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 22 2007 23:06:52
-M5 started Mon Jan 22 23:07:23 2007
-M5 executing on ewok
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
-Exiting @ tick 2237162 because target called exit()
+M5 compiled Mar 24 2007 13:51:02
+M5 started Sat Mar 24 13:51:16 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+Exiting @ tick 2232164 because target called exit()