diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-15 19:25:35 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-15 19:25:35 -0400 |
| commit | b85690e239616b703881b7734b0559f61f9eb75e (patch) | |
| tree | f144325bc982177a8ff0d87ba87cc9e840bfb301 /tests/quick/01.hello-2T-smt | |
| parent | c30e615689148c6e5ecd06e86069cba716dec5e0 (diff) | |
| download | gem5-b85690e239616b703881b7734b0559f61f9eb75e.tar.xz | |
update all the regresstion tests for release
--HG--
extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2
Diffstat (limited to 'tests/quick/01.hello-2T-smt')
4 files changed, 390 insertions, 408 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 5e1ced152..5380fc831 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -379,6 +377,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out index f04ad4ffd..c8129d10d 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload0] type=LiveProcess @@ -265,7 +266,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -296,14 +297,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -334,14 +334,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -372,7 +371,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -380,4 +378,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index b44194dff..484bdcca9 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 687 # Number of BTB hits -global.BPredUnit.BTBLookups 3480 # Number of BTB lookups -global.BPredUnit.RASInCorrect 113 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1086 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2328 # Number of conditional branches predicted -global.BPredUnit.lookups 4062 # Number of BP lookups -global.BPredUnit.usedRAS 562 # Number of times the RAS was used to get a target. -host_inst_rate 49679 # Simulator instruction rate (inst/s) -host_mem_usage 154724 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host -host_tick_rate 20293608 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 21 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 59 # Number of conflicting stores. +global.BPredUnit.BTBHits 674 # Number of BTB hits +global.BPredUnit.BTBLookups 3410 # Number of BTB lookups +global.BPredUnit.RASInCorrect 118 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1115 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2318 # Number of conditional branches predicted +global.BPredUnit.lookups 3964 # Number of BP lookups +global.BPredUnit.usedRAS 532 # Number of times the RAS was used to get a target. +host_inst_rate 56668 # Simulator instruction rate (inst/s) +host_mem_usage 154692 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 27618195 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 18 # Number of conflicting loads. memdepunit.memDep.conflictingStores 54 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1911 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 1833 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1079 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1058 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.conflictingStores 59 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1925 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1898 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1088 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1090 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 4600500 # Number of ticks simulated +sim_ticks 5490000 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 179 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 165 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 9158 +system.cpu.commit.COM:committed_per_cycle.samples 10929 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 4902 5352.70% - 1 1725 1883.60% - 2 937 1023.15% - 3 472 515.40% - 4 355 387.64% - 5 234 255.51% - 6 234 255.51% - 7 120 131.03% - 8 179 195.46% + 0 6410 5865.13% + 1 2019 1847.38% + 2 999 914.08% + 3 454 415.41% + 4 300 274.50% + 5 246 225.09% + 6 200 183.00% + 7 136 124.44% + 8 165 150.97% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -61,141 +61,133 @@ system.cpu.commit.COM:refs_1 1791 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 843 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 874 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 7371 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 7769 # The number of squashed insts skipped by commit system.cpu.committedInsts_0 5623 # Number of Instructions Simulated system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 1.636671 # CPI: Cycles Per Instruction -system.cpu.cpi_1 1.636380 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.818263 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2909 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 2909 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 6520.912548 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency_0 6520.912548 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6121.212121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 6121.212121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2646 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2646 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1715000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 1715000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.090409 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate_0 0.090409 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 263 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 263 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 1212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.068065 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.068065 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses +system.cpu.cpi_0 1.952516 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.952169 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.976171 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 7072.992701 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 6972.361809 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2695 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2695 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 1938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.092287 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 274 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 274 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.067026 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 199 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 199 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4509.846827 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency_0 4509.846827 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4681.506849 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 4681.506849 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1167 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1167 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2061000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 2061000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.281404 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate_0 0.281404 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 457 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 457 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 311 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 311 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 683500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 683500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency_0 5352.409639 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 5859.589041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1126 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1126 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2665500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 2665500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.306650 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 498 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 498 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 855500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 855500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 146 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.084302 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.075362 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4533 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4533 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4593 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4593 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 5244.444444 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 5244.444444 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 5963.082902 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5510.174419 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 5510.174419 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 6501.449275 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 3813 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3813 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 3821 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 3821 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3776000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 3776000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 4603500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 4603500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.158835 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.158835 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.168082 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 720 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 720 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 772 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 772 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 427 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 427 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1895500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 1895500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2243000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 2243000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.075888 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.075888 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.075114 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 344 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 345 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4533 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4533 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4593 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4593 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 5244.444444 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 5244.444444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 5963.082902 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5510.174419 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 5510.174419 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 6501.449275 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3813 # number of overall hits -system.cpu.dcache.overall_hits_0 3813 # number of overall hits +system.cpu.dcache.overall_hits 3821 # number of overall hits +system.cpu.dcache.overall_hits_0 3821 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 3776000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 3776000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 4603500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 4603500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.158835 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.158835 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.168082 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 720 # number of overall misses -system.cpu.dcache.overall_misses_0 720 # number of overall misses +system.cpu.dcache.overall_misses 772 # number of overall misses +system.cpu.dcache.overall_misses_0 772 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 376 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 427 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 427 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1895500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 1895500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2243000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 2243000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.075888 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.075888 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.075114 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 345 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 345 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -215,153 +207,149 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 344 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 345 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 218.590181 # Cycle average of tags in use -system.cpu.dcache.total_refs 3813 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 221.724795 # Cycle average of tags in use +system.cpu.dcache.total_refs 3821 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1876 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 260 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 354 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22033 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 11054 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3598 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1407 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 337 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 284 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4062 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2946 # Number of cache lines fetched -system.cpu.fetch.Cycles 6973 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 278 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 24430 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1145 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.441378 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2946 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1249 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.654569 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 1857 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 251 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 346 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 21806 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 14535 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3658 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1498 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 351 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 145 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 3964 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2983 # Number of cache lines fetched +system.cpu.fetch.Cycles 6940 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 525 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 24033 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1178 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.361053 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2983 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1206 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.188997 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 9203 +system.cpu.fetch.rateDist.samples 10979 system.cpu.fetch.rateDist.min_value 0 - 0 5177 5625.34% - 1 291 316.20% - 2 234 254.26% - 3 263 285.78% - 4 314 341.19% - 5 294 319.46% - 6 311 337.93% - 7 262 284.69% - 8 2057 2235.14% + 0 7023 6396.76% + 1 285 259.59% + 2 224 204.03% + 3 248 225.89% + 4 335 305.13% + 5 281 255.94% + 6 301 274.16% + 7 251 228.62% + 8 2031 1849.90% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 2946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 2946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4950.682853 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency_0 4950.682853 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4079.838710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 4079.838710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2287 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2287 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3262500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 3262500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.223693 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate_0 0.223693 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 659 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 659 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 39 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2529500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 2529500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.210455 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.210455 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 620 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 620 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 2983 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2983 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 5910.313901 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 5152.173913 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2314 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2314 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 3954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.224271 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 669 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 669 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 3199500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 3199500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.208180 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 621 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 621 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.688710 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.726248 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2946 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 2946 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2983 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2983 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4950.682853 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 4950.682853 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 5910.313901 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4079.838710 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 4079.838710 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 5152.173913 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 2287 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2287 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2314 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2314 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3262500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 3262500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3954000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 3954000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.223693 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.223693 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.224271 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 659 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 659 # number of demand (read+write) misses +system.cpu.icache.demand_misses 669 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 669 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 39 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 39 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 48 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2529500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 2529500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3199500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 3199500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.210455 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.210455 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.208180 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 620 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 620 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 621 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 621 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2946 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 2946 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2983 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2983 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4950.682853 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 4950.682853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 5910.313901 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4079.838710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 4079.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 5152.173913 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2287 # number of overall hits -system.cpu.icache.overall_hits_0 2287 # number of overall hits +system.cpu.icache.overall_hits 2314 # number of overall hits +system.cpu.icache.overall_hits_0 2314 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 3262500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 3262500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3954000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 3954000 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.223693 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.223693 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.224271 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_misses 659 # number of overall misses -system.cpu.icache.overall_misses_0 659 # number of overall misses +system.cpu.icache.overall_misses 669 # number of overall misses +system.cpu.icache.overall_misses_0 669 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 39 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 39 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 48 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2529500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 2529500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3199500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 3199500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.210455 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.210455 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.208180 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 620 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 620 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 621 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 621 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -381,104 +369,104 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 9 # number of replacements system.cpu.icache.replacements_0 9 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 620 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 621 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 315.428279 # Cycle average of tags in use -system.cpu.icache.total_refs 2287 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 322.894952 # Cycle average of tags in use +system.cpu.icache.total_refs 2314 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles -1 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2339 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1175 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1164 # Number of branches executed -system.cpu.iew.EXEC:nop 72 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 36 # number of nop insts executed +system.cpu.idleCycles 1998 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2367 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1185 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1182 # Number of branches executed +system.cpu.iew.EXEC:nop 73 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 37 # number of nop insts executed system.cpu.iew.EXEC:nop_1 36 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.666196 # Inst execution rate -system.cpu.iew.EXEC:refs 4928 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2490 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2438 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1865 # Number of stores executed +system.cpu.iew.EXEC:rate 1.416158 # Inst execution rate +system.cpu.iew.EXEC:refs 4978 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2514 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2464 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1867 # Number of stores executed system.cpu.iew.EXEC:stores_0 938 # Number of stores executed -system.cpu.iew.EXEC:stores_1 927 # Number of stores executed +system.cpu.iew.EXEC:stores_1 929 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10157 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5143 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5014 # num instructions consuming a value -system.cpu.iew.WB:count 14949 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7544 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7405 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.769912 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.768229 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.771639 # average fanout of values written-back +system.cpu.iew.WB:consumers 10219 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5113 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5106 # num instructions consuming a value +system.cpu.iew.WB:count 14974 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7532 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7442 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.526960 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.762957 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.764003 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7820 # num instructions producing a value -system.cpu.iew.WB:producers_0 3951 # num instructions producing a value -system.cpu.iew.WB:producers_1 3869 # num instructions producing a value -system.cpu.iew.WB:rate 1.624362 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.819733 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.804629 # insts written-back per cycle -system.cpu.iew.WB:sent 15070 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7606 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7464 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 927 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 6 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3744 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 587 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2137 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 18669 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3063 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1552 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1511 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1008 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 15334 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 7802 # num instructions producing a value +system.cpu.iew.WB:producers_0 3901 # num instructions producing a value +system.cpu.iew.WB:producers_1 3901 # num instructions producing a value +system.cpu.iew.WB:rate 1.363876 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.686037 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.677840 # insts written-back per cycle +system.cpu.iew.WB:sent 15105 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7590 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7515 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 941 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 7 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3823 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 501 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2178 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19078 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3111 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1576 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1535 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 864 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15548 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1407 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1498 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 42 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 56 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 932 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 267 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 946 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 276 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 49 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 38 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 57 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 54 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 854 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 246 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 113 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 753 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 174 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.610996 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.611105 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.222101 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8271 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 919 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 278 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 117 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 761 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 180 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.512160 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.512251 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.024410 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8232 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5600 67.71% # Type of FU issued + IntAlu 5551 67.43% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +475,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1701 20.57% # Type of FU issued - MemWrite 965 11.67% # Type of FU issued + MemRead 1704 20.70% # Type of FU issued + MemWrite 972 11.81% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8071 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 8180 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5485 67.96% # Type of FU issued + IntAlu 5536 67.68% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +492,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1640 20.32% # Type of FU issued - MemWrite 941 11.66% # Type of FU issued + MemRead 1681 20.55% # Type of FU issued + MemWrite 958 11.71% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 16342 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 16412 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist (null) 4 0.02% # Type of FU issued - IntAlu 11085 67.83% # Type of FU issued + IntAlu 11087 67.55% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +509,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3341 20.44% # Type of FU issued - MemWrite 1906 11.66% # Type of FU issued + MemRead 3385 20.63% # Type of FU issued + MemWrite 1930 11.76% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 184 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 95 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 89 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011259 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.005813 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.005446 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 180 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 92 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010968 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.005606 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.005362 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 11 5.98% # attempts to use FU when none available + IntAlu 16 8.89% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,108 +531,104 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 108 58.70% # attempts to use FU when none available - MemWrite 65 35.33% # attempts to use FU when none available + MemRead 97 53.89% # attempts to use FU when none available + MemWrite 67 37.22% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 9203 +system.cpu.iq.ISSUE:issued_per_cycle.samples 10979 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3452 3750.95% - 1 1399 1520.16% - 2 1479 1607.08% - 3 1070 1162.66% - 4 845 918.18% - 5 528 573.73% - 6 290 315.11% - 7 105 114.09% - 8 35 38.03% + 0 4788 4361.05% + 1 1816 1654.07% + 2 1657 1509.24% + 3 1039 946.35% + 4 774 704.98% + 5 501 456.33% + 6 289 263.23% + 7 90 81.97% + 8 25 22.77% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.775725 # Inst issue rate -system.cpu.iq.iqInstsAdded 18557 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 16342 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 6288 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3616 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 960 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 960 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4143.899896 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency_0 4143.899896 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2323.820647 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2323.820647 # average ReadReq mshr miss latency +system.cpu.iq.ISSUE:rate 1.494854 # Inst issue rate +system.cpu.iq.iqInstsAdded 18963 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16412 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 6896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 34 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 963 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 963 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 5220.374220 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2725.051975 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits_0 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3974000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 3974000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.998958 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate_0 0.998958 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 959 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 959 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2228544 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2228544 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.998958 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.998958 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 5022000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 5022000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.998962 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 2621500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2621500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.998962 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 962 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 962 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.001043 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.001040 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 960 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 960 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 963 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 963 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4143.899896 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 4143.899896 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 5220.374220 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2323.820647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2323.820647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2725.051975 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_0 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3974000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 3974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5022000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 5022000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.998958 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.998958 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.998962 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_misses 959 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 959 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 962 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 962 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2228544 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 2228544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2621500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 2621500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.998958 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.998958 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.998962 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 959 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 962 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 960 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 960 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 963 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 963 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4143.899896 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 4143.899896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 5220.374220 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2323.820647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2323.820647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2725.051975 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency @@ -652,26 +636,26 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> system.cpu.l2cache.overall_hits 1 # number of overall hits system.cpu.l2cache.overall_hits_0 1 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3974000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 3974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5022000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 5022000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.998958 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.998958 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.998962 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_misses 959 # number of overall misses -system.cpu.l2cache.overall_misses_0 959 # number of overall misses +system.cpu.l2cache.overall_misses 962 # number of overall misses +system.cpu.l2cache.overall_misses_0 962 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2228544 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 2228544 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2621500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 2621500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.998958 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.998958 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.998962 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 959 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 962 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -691,33 +675,33 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 959 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 962 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 534.228654 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 545.133409 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 9203 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 514 # Number of cycles rename is blocking +system.cpu.numCycles 10979 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 614 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 11467 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 762 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 26335 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 20742 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 15622 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3447 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1407 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 876 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7520 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 508 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 14840 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 684 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26359 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 20748 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15612 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3480 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1498 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 744 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7510 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 517 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2622 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:skidInsts 2147 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index ea08dc448..ef617d5ef 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:11 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:42 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4600500 because target called exit() +Exiting @ tick 5490000 because target called exit() |