diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
| commit | a51e2fd8bd581d45f8a87874c9a6680f99d11e24 (patch) | |
| tree | 8de4626b115b234de0962cc04d32e15b6eb0fa3a /tests/quick/01.hello-2T-smt | |
| parent | e7e2d5ce9072808d94d5fe399e6c4262d92b7923 (diff) | |
| download | gem5-a51e2fd8bd581d45f8a87874c9a6680f99d11e24.tar.xz | |
Stats: Update the stats.
--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
Diffstat (limited to 'tests/quick/01.hello-2T-smt')
3 files changed, 423 insertions, 397 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 5a35877e6..71b1480ab 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus tracer workload0 workload1 +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload0 workload1 BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -36,6 +36,7 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -53,6 +54,7 @@ iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 +itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 @@ -130,6 +132,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 @@ -303,6 +309,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 5a48eb9ba..e76204a83 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 691 # Number of BTB hits -global.BPredUnit.BTBLookups 3468 # Number of BTB lookups -global.BPredUnit.RASInCorrect 112 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1111 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2334 # Number of conditional branches predicted -global.BPredUnit.lookups 4040 # Number of BP lookups -global.BPredUnit.usedRAS 559 # Number of times the RAS was used to get a target. -host_inst_rate 99825 # Simulator instruction rate (inst/s) -host_mem_usage 197616 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 48783081 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 44 # Number of conflicting stores. +global.BPredUnit.BTBHits 706 # Number of BTB hits +global.BPredUnit.BTBLookups 3499 # Number of BTB lookups +global.BPredUnit.RASInCorrect 117 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1092 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2350 # Number of conditional branches predicted +global.BPredUnit.lookups 4075 # Number of BP lookups +global.BPredUnit.usedRAS 561 # Number of times the RAS was used to get a target. +host_inst_rate 76336 # Simulator instruction rate (inst/s) +host_mem_usage 181020 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +host_tick_rate 38800813 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 35 # Number of conflicting stores. memdepunit.memDep.conflictingStores 38 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1952 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 1960 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1112 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1121 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1959 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1940 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1118 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1140 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5506000 # Number of ticks simulated +sim_ticks 5727000 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 153 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 161 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 10938 +system.cpu.commit.COM:committed_per_cycle.samples 11403 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 6318 5776.19% - 1 2129 1946.43% - 2 954 872.19% - 3 501 458.04% - 4 328 299.87% - 5 233 213.02% - 6 214 195.65% - 7 108 98.74% - 8 153 139.88% + 0 6781 5946.68% + 1 2144 1880.21% + 2 950 833.11% + 3 495 434.10% + 4 331 290.27% + 5 216 189.42% + 6 215 188.55% + 7 110 96.47% + 8 161 141.19% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:count 11281 # Number of instructions committed -system.cpu.commit.COM:count_0 5641 # Number of instructions committed -system.cpu.commit.COM:count_1 5640 # Number of instructions committed +system.cpu.commit.COM:count_0 5640 # Number of instructions committed +system.cpu.commit.COM:count_1 5641 # Number of instructions committed system.cpu.commit.COM:loads 1958 # Number of loads committed system.cpu.commit.COM:loads_0 979 # Number of loads committed system.cpu.commit.COM:loads_1 979 # Number of loads committed @@ -61,133 +61,133 @@ system.cpu.commit.COM:refs_1 1791 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 859 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 854 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8029 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 5624 # Number of Instructions Simulated -system.cpu.committedInsts_1 5623 # Number of Instructions Simulated +system.cpu.commit.commitSquashedInsts 8053 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 5623 # Number of Instructions Simulated +system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 1.952703 # CPI: Cycles Per Instruction -system.cpu.cpi_1 1.953050 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.976438 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2963 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 2963 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 12228.855721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 7833.333333 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2762 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2762 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2458000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 2458000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.067837 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 201 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 201 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1574500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 1574500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.067837 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 201 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 201 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1252 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_0 1252 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 21841.954023 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 6695.402299 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1078 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1078 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3800500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 3800500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate_0 0.138978 # miss rate for WriteReq accesses +system.cpu.cpi_0 2.035568 # CPI: Cycles Per Instruction +system.cpu.cpi_1 2.035206 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.017694 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2934 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2934 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 12119.897959 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 7403.061224 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2738 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2738 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2375500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 2375500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.066803 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 196 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 196 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1451000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 1451000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.066803 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 196 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 196 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1240 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 1240 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency_0 21692.528736 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 6310.344828 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1066 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1066 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3774500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 3774500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.140323 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 174 # number of WriteReq misses system.cpu.dcache.WriteReq_misses_0 174 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 372 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 372 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1165000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 1165000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.138978 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_hits 384 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 384 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1098000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 1098000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.140323 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.146974 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.276471 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4215 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4215 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4174 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4174 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 16689.333333 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 16621.621622 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 7305.333333 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 6889.189189 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 3840 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3840 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 3804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 3804 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 6258500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 6258500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 6150000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 6150000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.088968 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.088644 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 375 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 375 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 370 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 370 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 447 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 447 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 465 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 465 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 2739500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 2739500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2549000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 2549000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.088968 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.088644 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 375 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 375 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 370 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 370 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4215 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4215 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4174 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4174 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 16689.333333 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 16621.621622 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 7305.333333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 6889.189189 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3840 # number of overall hits -system.cpu.dcache.overall_hits_0 3840 # number of overall hits +system.cpu.dcache.overall_hits 3804 # number of overall hits +system.cpu.dcache.overall_hits_0 3804 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 6258500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 6258500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 6150000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 6150000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.088968 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.088644 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 375 # number of overall misses -system.cpu.dcache.overall_misses_0 375 # number of overall misses +system.cpu.dcache.overall_misses 370 # number of overall misses +system.cpu.dcache.overall_misses_0 370 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 447 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 447 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 465 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 465 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 2739500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 2739500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2549000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 2549000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.088968 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.088644 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 375 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 375 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 370 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 370 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -207,149 +207,161 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 340 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 219.667658 # Cycle average of tags in use -system.cpu.dcache.total_refs 3868 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 215.589336 # Cycle average of tags in use +system.cpu.dcache.total_refs 3834 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1907 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 262 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 358 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22173 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 14421 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3707 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1515 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 340 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 183 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4040 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2997 # Number of cache lines fetched -system.cpu.fetch.Cycles 7042 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 442 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 24368 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1175 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.367875 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2997 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1250 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.218904 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 1981 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 247 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 354 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 22591 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 15034 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3799 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1569 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 329 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 215 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 5095 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 4970 # DTB hits +system.cpu.dtb.misses 125 # DTB misses +system.cpu.dtb.read_accesses 3183 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 3106 # DTB read hits +system.cpu.dtb.read_misses 77 # DTB read misses +system.cpu.dtb.write_accesses 1912 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 1864 # DTB write hits +system.cpu.dtb.write_misses 48 # DTB write misses +system.cpu.fetch.Branches 4075 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 3019 # Number of cache lines fetched +system.cpu.fetch.Cycles 7174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 439 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 24770 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1207 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.356020 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 3019 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1267 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.164075 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 10982 +system.cpu.fetch.rateDist.samples 11446 system.cpu.fetch.rateDist.min_value 0 - 0 6938 6317.61% - 1 305 277.73% - 2 235 213.99% - 3 261 237.66% - 4 343 312.33% - 5 297 270.44% - 6 304 276.82% - 7 263 239.48% - 8 2036 1853.94% + 0 7343 6415.34% + 1 306 267.34% + 2 243 212.30% + 3 264 230.65% + 4 343 299.67% + 5 290 253.36% + 6 316 276.08% + 7 260 227.15% + 8 2081 1818.10% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 2933 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 2933 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 8509.630819 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 6073.033708 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2310 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2310 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 5301500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 5301500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.212411 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 623 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 623 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 64 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 64 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 3783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 3783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.212411 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 623 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 623 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 2953 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2953 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 8345.528455 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 5903.252033 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2338 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2338 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 5132500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 5132500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.208263 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 615 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 615 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 66 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 3630500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 3630500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.208263 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 615 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 615 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.707865 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.801626 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2933 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 2933 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2953 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2953 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 8509.630819 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 8345.528455 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 6073.033708 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 5903.252033 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 2310 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2310 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2338 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2338 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 5301500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 5301500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 5132500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 5132500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.212411 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.208263 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 623 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 623 # number of demand (read+write) misses +system.cpu.icache.demand_misses 615 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 615 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 64 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 64 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 66 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 3783500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 3783500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3630500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 3630500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.212411 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.208263 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 623 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 623 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 615 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 615 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2933 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 2933 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2953 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2953 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 8509.630819 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 8345.528455 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 6073.033708 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 5903.252033 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2310 # number of overall hits -system.cpu.icache.overall_hits_0 2310 # number of overall hits +system.cpu.icache.overall_hits 2338 # number of overall hits +system.cpu.icache.overall_hits_0 2338 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 5301500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 5301500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 5132500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 5132500 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.212411 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.208263 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_misses 623 # number of overall misses -system.cpu.icache.overall_misses_0 623 # number of overall misses +system.cpu.icache.overall_misses 615 # number of overall misses +system.cpu.icache.overall_misses_0 615 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 64 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 64 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 66 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 3783500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 3783500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3630500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 3630500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.212411 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.208263 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 623 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 623 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 615 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 615 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -366,107 +378,107 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 9 # number of replacements -system.cpu.icache.replacements_0 9 # number of replacements +system.cpu.icache.replacements 7 # number of replacements +system.cpu.icache.replacements_0 7 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 623 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 615 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 319.917416 # Cycle average of tags in use -system.cpu.icache.total_refs 2310 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 319.122278 # Cycle average of tags in use +system.cpu.icache.total_refs 2338 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 18494 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2371 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1190 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1181 # Number of branches executed -system.cpu.iew.EXEC:nop 73 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 36 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.425514 # Inst execution rate -system.cpu.iew.EXEC:refs 5064 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2541 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2523 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1883 # Number of stores executed -system.cpu.iew.EXEC:stores_0 944 # Number of stores executed -system.cpu.iew.EXEC:stores_1 939 # Number of stores executed +system.cpu.idleCycles 6496 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2386 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1188 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1198 # Number of branches executed +system.cpu.iew.EXEC:nop 127 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 66 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 61 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.378123 # Inst execution rate +system.cpu.iew.EXEC:refs 5110 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2531 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2579 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1925 # Number of stores executed +system.cpu.iew.EXEC:stores_0 958 # Number of stores executed +system.cpu.iew.EXEC:stores_1 967 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10238 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5115 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5123 # num instructions consuming a value -system.cpu.iew.WB:count 15036 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7510 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7526 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 1.535845 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.766960 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.768885 # average fanout of values written-back +system.cpu.iew.WB:consumers 10281 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5147 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5134 # num instructions consuming a value +system.cpu.iew.WB:count 15145 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7584 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7561 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.539346 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.768992 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.770354 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7862 # num instructions producing a value -system.cpu.iew.WB:producers_0 3923 # num instructions producing a value -system.cpu.iew.WB:producers_1 3939 # num instructions producing a value -system.cpu.iew.WB:rate 1.369150 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.683846 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.685303 # insts written-back per cycle -system.cpu.iew.WB:sent 15186 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7583 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7603 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 992 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 8 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3912 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 367 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2233 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 19338 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3181 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1597 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1584 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 917 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 15655 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 7913 # num instructions producing a value +system.cpu.iew.WB:producers_0 3958 # num instructions producing a value +system.cpu.iew.WB:producers_1 3955 # num instructions producing a value +system.cpu.iew.WB:rate 1.323170 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.662590 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.660580 # insts written-back per cycle +system.cpu.iew.WB:sent 15343 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7675 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7668 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 991 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 60 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3899 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 435 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2258 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19501 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3185 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1573 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1612 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 923 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15774 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 16 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1515 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1569 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 44 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 39 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 70 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 62 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 973 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 300 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 980 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 306 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 45 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 50 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 61 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 981 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 309 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 131 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 807 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 185 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.512111 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.512020 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.024130 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8256 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 961 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 328 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 125 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 788 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 203 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.491263 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.491351 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.982614 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8365 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5550 67.22% # Type of FU issued + IntAlu 5650 67.54% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -475,15 +487,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1728 20.93% # Type of FU issued - MemWrite 973 11.79% # Type of FU issued + MemRead 1721 20.57% # Type of FU issued + MemWrite 989 11.82% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8316 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 8332 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5613 67.50% # Type of FU issued + IntAlu 5594 67.14% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -492,15 +504,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1726 20.76% # Type of FU issued - MemWrite 972 11.69% # Type of FU issued + MemRead 1734 20.81% # Type of FU issued + MemWrite 999 11.99% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 16572 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 16697 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist No_OpClass 4 0.02% # Type of FU issued - IntAlu 11163 67.36% # Type of FU issued + IntAlu 11244 67.34% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -509,20 +521,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3454 20.84% # Type of FU issued - MemWrite 1945 11.74% # Type of FU issued + MemRead 3455 20.69% # Type of FU issued + MemWrite 1988 11.91% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 198 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 95 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 103 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011948 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.005733 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.006215 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 193 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 105 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011559 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.005270 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.006289 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 14 7.07% # attempts to use FU when none available + IntAlu 13 6.74% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -531,159 +543,163 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 119 60.10% # attempts to use FU when none available - MemWrite 65 32.83% # attempts to use FU when none available + MemRead 111 57.51% # attempts to use FU when none available + MemWrite 69 35.75% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 10982 +system.cpu.iq.ISSUE:issued_per_cycle.samples 11446 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 4716 4294.30% - 1 1863 1696.41% - 2 1568 1427.79% - 3 1132 1030.78% - 4 836 761.25% - 5 492 448.01% - 6 274 249.50% - 7 79 71.94% - 8 22 20.03% + 0 5082 4439.98% + 1 1881 1643.37% + 2 1650 1441.55% + 3 1151 1005.59% + 4 829 724.27% + 5 503 439.45% + 6 239 208.81% + 7 90 78.63% + 8 21 18.35% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.509015 # Inst issue rate -system.cpu.iq.iqInstsAdded 19223 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 16572 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 7181 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4476 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency_0 4770.547945 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 2770.547945 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 696500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency_0 696500 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:rate 1.458763 # Inst issue rate +system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16697 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 7298 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4495 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 3071 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 3019 # ITB hits +system.cpu.itb.misses 52 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 144 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses_0 144 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency_0 4743.055556 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 2743.055556 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 683000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency_0 683000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 404500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 404500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 144 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses_0 144 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 395000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 395000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 824 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 824 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency_0 4751.219512 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2751.219512 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_0 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3896000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 3896000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate_0 0.995146 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 820 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 820 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2256000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2256000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.995146 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 820 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 820 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 4482.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 2482.142857 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 125500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency_0 125500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 144 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses_0 144 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 811 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 811 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 4691.831683 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2691.831683 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 3791000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 3791000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.996301 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 808 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 808 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 2175000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2175000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.996301 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 808 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 30 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses_0 30 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 4500 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 2500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 135000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency_0 135000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 69500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 69500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 30 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses_0 30 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 75000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 75000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 30 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses_0 30 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005051 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.003856 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 970 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 970 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 955 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 955 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 4754.140787 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 4699.579832 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2754.140787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2699.579832 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 4 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4592500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 4592500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 4474000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 4474000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.995876 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.996859 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_misses 966 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 966 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 952 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 952 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2660500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 2660500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2570000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 2570000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.995876 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.996859 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 966 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 966 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 952 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 952 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 970 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 970 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 955 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 955 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 4754.140787 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 4699.579832 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2754.140787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2699.579832 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_hits_0 4 # number of overall hits +system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_hits_0 3 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4592500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 4592500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 4474000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 4474000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.995876 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.996859 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_misses 966 # number of overall misses -system.cpu.l2cache.overall_misses_0 966 # number of overall misses +system.cpu.l2cache.overall_misses 952 # number of overall misses +system.cpu.l2cache.overall_misses_0 952 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2660500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 2660500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2570000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 2570000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.995876 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.996859 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 966 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 966 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 952 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 952 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -703,33 +719,33 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 792 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 778 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 429.647178 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 424.676856 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 10982 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 592 # Number of cycles rename is blocking +system.cpu.numCycles 11446 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 641 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 14764 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 762 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 26692 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21016 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 15806 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3542 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1515 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 817 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7704 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 503 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 15417 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 776 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 27043 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21312 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15958 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3623 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1569 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 844 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7856 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 504 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2234 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 2318 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.timesIdled 7 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 4 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 5b0ff582b..c45cb0224 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 00:26:55 -M5 started Sun Aug 12 00:29:42 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 15:45:23 +M5 started Tue Aug 14 15:45:27 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5506000 because target called exit() +Exiting @ tick 5727000 because target called exit() |