Update ref stats: ll/sc, cpu_id, new kernel (?)

--HG--
extra : convert_revision : 060cb7319c4474429917a6347a9a47f390208ec8

2 files changed, 24 insertions, 24 deletions

diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
index a249947ca..15172b43c 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                   1081                       # Nu
 global.BPredUnit.condPredicted                   2449                       # Number of conditional branches predicted
 global.BPredUnit.lookups                         4173                       # Number of BP lookups
 global.BPredUnit.usedRAS                          551                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  50082                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 161260                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
-host_tick_rate                                  37535                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  40630                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 161244                       # Number of bytes of host memory used
+host_seconds                                     0.28                       # Real time elapsed on the host
+host_tick_rate                                  30458                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 41                       # Number of conflicting loads.
 memdepunit.memDep.conflictingLoads                 39                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores               194                       # Number of conflicting stores.
@@ -115,7 +115,7 @@ system.cpu.dcache.WriteReq_mshr_miss_rate     0.088670                       # m
 system.cpu.dcache.WriteReq_mshr_miss_rate_0     0.088670                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses            144                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses_0          144                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets            1                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                  11.670554                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
@@ -476,20 +476,20 @@ system.cpu.ipc_1                             0.666272                       # IP
 system.cpu.ipc_total                         1.332425                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0                    8158                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
-                          (null)            2      0.02%            # Type of FU issued
-                          IntAlu         5514     67.59%            # Type of FU issued
-                         IntMult            1      0.01%            # Type of FU issued
-                          IntDiv            0      0.00%            # Type of FU issued
-                        FloatAdd            2      0.02%            # Type of FU issued
-                        FloatCmp            0      0.00%            # Type of FU issued
-                        FloatCvt            0      0.00%            # Type of FU issued
-                       FloatMult            0      0.00%            # Type of FU issued
-                        FloatDiv            0      0.00%            # Type of FU issued
-                       FloatSqrt            0      0.00%            # Type of FU issued
-                         MemRead         1662     20.37%            # Type of FU issued
-                        MemWrite          977     11.98%            # Type of FU issued
-                       IprAccess            0      0.00%            # Type of FU issued
-                    InstPrefetch            0      0.00%            # Type of FU issued
+(null)                                              2      0.02%            # Type of FU issued
+IntAlu                                           5514     67.59%            # Type of FU issued
+IntMult                                             1      0.01%            # Type of FU issued
+IntDiv                                              0      0.00%            # Type of FU issued
+FloatAdd                                            2      0.02%            # Type of FU issued
+FloatCmp                                            0      0.00%            # Type of FU issued
+FloatCvt                                            0      0.00%            # Type of FU issued
+FloatMult                                           0      0.00%            # Type of FU issued
+FloatDiv                                            0      0.00%            # Type of FU issued
+FloatSqrt                                           0      0.00%            # Type of FU issued
+MemRead                                          1662     20.37%            # Type of FU issued
+MemWrite                                          977     11.98%            # Type of FU issued
+IprAccess                                           0      0.00%            # Type of FU issued
+InstPrefetch                                        0      0.00%            # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.end_dist
 system.cpu.iq.ISSUE:FU_type_1                    8090                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_1.start_dist
@@ -610,7 +610,7 @@ system.cpu.l2cache.demand_avg_miss_latency_0     2.059561
 system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0>                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency            1                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency_0            1                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0>                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency_1     no value                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                      9                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits_0                    9                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits_1                    0                       # number of demand (read+write) hits
@@ -619,7 +619,7 @@ system.cpu.l2cache.demand_miss_latency_0         1971                       # nu
 system.cpu.l2cache.demand_miss_latency_1            0                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.990683                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate_0        0.990683                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate_1        no value                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate_1    <err: div-0>                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  957                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses_0                957                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses_1                  0                       # number of demand (read+write) misses
@@ -631,7 +631,7 @@ system.cpu.l2cache.demand_mshr_miss_latency_0          957
 system.cpu.l2cache.demand_mshr_miss_latency_1            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate     0.990683                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate_0     0.990683                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate_1     no value                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0>                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             957                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses_0           957                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses_1             0                       # number of demand (read+write) MSHR misses
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
index be25795fb..6b640d359 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  7 2006 12:38:12
-M5 started Sat Oct  7 12:38:47 2006
+M5 compiled Oct  8 2006 14:00:39
+M5 started Sun Oct  8 14:00:56 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
 Exiting @ tick 8441 because target called exit()