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author | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
commit | 28a2236ec18e3d5a82d6f7caffbf8285aec48b38 (patch) | |
tree | bfd2d8d78733f95b30e9f671229ce2f0f55f4d94 /tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt | |
parent | 649c239ceef2d107fae253b1008c6f214f242d73 (diff) | |
download | gem5-28a2236ec18e3d5a82d6f7caffbf8285aec48b38.tar.xz |
O3: Update stats for new ordering fix.
Diffstat (limited to 'tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt')
-rw-r--r-- | tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 44f3bc0f0..ea9aaaf42 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.000018 # Number of seconds simulated sim_ticks 18114000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40525 # Simulator instruction rate (inst/s) -host_tick_rate 50798832 # Simulator tick rate (ticks/s) -host_mem_usage 250076 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host +host_inst_rate 2357 # Simulator instruction rate (inst/s) +host_tick_rate 2955469 # Simulator tick rate (ticks/s) +host_mem_usage 210004 # Number of bytes of host memory used +host_seconds 6.13 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 36229 # number of cpu cycles simulated @@ -185,7 +185,7 @@ system.cpu.iew.lsq.thread0.forwLoads 26 # Nu system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 888 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 528 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding @@ -202,7 +202,7 @@ system.cpu.iew.iewDispStoreInsts 1976 # Nu system.cpu.iew.iewDispNonSpecInsts 615 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 371 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 944 # Number of branch mispredicts detected at execute |