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| author | Steve Reinhardt <stever@gmail.com> | 2009-04-22 01:55:52 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2009-04-22 01:55:52 -0400 |
| commit | 7b40c36fbd1c348e5ef43231325923aae1cd0809 (patch) | |
| tree | b1d142d10229a7ca68eff864aa9aae672230e41a /tests/quick/02.insttest/ref/sparc/linux/o3-timing | |
| parent | 6629d9b2bc58a885bfebce1517fd12483497b6e4 (diff) | |
| download | gem5-7b40c36fbd1c348e5ef43231325923aae1cd0809.tar.xz | |
Update stats for new single bad-address responder.
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.
Diffstat (limited to 'tests/quick/02.insttest/ref/sparc/linux/o3-timing')
3 files changed, 13 insertions, 16 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 95ee672cf..e7d27f8d6 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -313,11 +311,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -361,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 974c1f458..34998e971 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 14 2009 16:03:50 -M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update -M5 started Apr 14 2009 16:03:52 -M5 executing on phenom -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:05:07 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 3faf1f835..3e04b78ab 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 9495 # Simulator instruction rate (inst/s) -host_mem_usage 208836 # Number of bytes of host memory used -host_seconds 1.52 # Real time elapsed on the host -host_tick_rate 18237542 # Simulator tick rate (ticks/s) +host_inst_rate 47616 # Simulator instruction rate (inst/s) +host_mem_usage 201812 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 91393866 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000028 # Number of seconds simulated |