diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
| commit | 1114be4b78c0855d96004b9f71c61d4b6a050d3a (patch) | |
| tree | eb1e2047d27bd31626530cae97cd9224e1dbbb11 /tests/quick/02.insttest/ref/sparc/linux/o3-timing | |
| parent | 7dde557fdc51140988092962137e1006d1609bea (diff) | |
| download | gem5-1114be4b78c0855d96004b9f71c61d4b6a050d3a.tar.xz | |
O3: Update stats for memory order violation checking patch.
Diffstat (limited to 'tests/quick/02.insttest/ref/sparc/linux/o3-timing')
3 files changed, 233 insertions, 231 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 4c6ef2b94..4308ebe8c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index a2a0eb0e5..1c0d12619 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:13:49 -M5 executing on burrito +M5 compiled Mar 17 2011 23:04:27 +M5 started Mar 17 2011 23:04:36 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +22,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 18656000 because target called exit() +Exiting @ tick 18633000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 7ae6650a8..d6c8de2b4 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 30834 # Simulator instruction rate (inst/s) -host_mem_usage 224180 # Number of bytes of host memory used -host_seconds 0.47 # Real time elapsed on the host -host_tick_rate 39786625 # Simulator tick rate (ticks/s) +host_inst_rate 81712 # Simulator instruction rate (inst/s) +host_mem_usage 206196 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 105251575 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18656000 # Number of ticks simulated +sim_ticks 18633000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 2698 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 5085 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2697 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 5067 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 714 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 5172 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 5172 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 5154 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 5154 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 3359 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 84 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 86 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 27579 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.550237 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.187070 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 27481 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.552200 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.190718 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 19793 71.77% 71.77% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 4521 16.39% 88.16% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 1461 5.30% 93.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 765 2.77% 96.23% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 373 1.35% 97.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 256 0.93% 98.51% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 289 1.05% 99.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 37 0.13% 99.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 84 0.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 19704 71.70% 71.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 4516 16.43% 88.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 1458 5.31% 93.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 763 2.78% 96.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 370 1.35% 97.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 256 0.93% 98.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 290 1.06% 99.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 38 0.14% 99.69% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 86 0.31% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 27579 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 27481 # Number of insts commited each cycle system.cpu.commit.COM:count 15175 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -47,254 +47,254 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 714 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 5133 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5051 # The number of squashed insts skipped by commit system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.582393 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.582393 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2777 # number of ReadReq accesses(hits+misses) +system.cpu.cpi 2.579210 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.579210 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2764 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 33620.967742 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35563.492063 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2653 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 2640 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4169000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.044653 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.044863 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 124 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 2240500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.022686 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.022793 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35892.156863 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35843.373494 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35890.931373 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35837.349398 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 14644000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 14643500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2975000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2974500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 25.294521 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25.205479 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4219 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35362.781955 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35722.602740 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3687 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 18813000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.126096 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 4206 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35361.842105 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35719.178082 # average overall mshr miss latency +system.cpu.dcache.demand_hits 3674 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 18812500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.126486 # miss rate for demand accesses system.cpu.dcache.demand_misses 532 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 386 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5215500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.034605 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 5215000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.034712 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.024937 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 102.143173 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 4219 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35362.781955 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35722.602740 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.024936 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 102.139862 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 4206 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35361.842105 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35719.178082 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3687 # number of overall hits -system.cpu.dcache.overall_miss_latency 18813000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.126096 # miss rate for overall accesses +system.cpu.dcache.overall_hits 3674 # number of overall hits +system.cpu.dcache.overall_miss_latency 18812500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.126486 # miss rate for overall accesses system.cpu.dcache.overall_misses 532 # number of overall misses system.cpu.dcache.overall_mshr_hits 386 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5215500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.034605 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 5215000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.034712 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.143173 # Cycle average of tags in use -system.cpu.dcache.total_refs 3693 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.139862 # Cycle average of tags in use +system.cpu.dcache.total_refs 3680 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 7077 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 23586 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 13112 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 7266 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1178 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 7079 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 23444 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 13037 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 7241 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1159 # Number of cycles decode is squashing system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 5172 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4077 # Number of cache lines fetched -system.cpu.fetch.Cycles 7506 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 23982 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5154 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4051 # Number of cache lines fetched +system.cpu.fetch.Cycles 7481 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 377 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 23840 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 826 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.138611 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4077 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 2698 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.642725 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 28740 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.834447 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.949360 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 813 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.138299 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4051 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 2697 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.639708 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 28623 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.832897 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.946042 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21234 73.88% 73.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3581 12.46% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 587 2.04% 88.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 509 1.77% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 664 2.31% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 529 1.84% 94.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 246 0.86% 95.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 197 0.69% 95.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1193 4.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21142 73.86% 73.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3578 12.50% 86.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 587 2.05% 88.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 505 1.76% 90.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 662 2.31% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 528 1.84% 94.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 244 0.85% 95.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 195 0.68% 95.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1182 4.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28740 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 4077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 34819.301848 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 28623 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 4051 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35069.791667 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34975.988701 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3590 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16957000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.119451 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 487 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 133 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_hits 3571 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16833500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.118489 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 480 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 126 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 12381500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.086829 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.087386 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 354 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 10.141243 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 10.087571 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4077 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 34819.301848 # average overall miss latency +system.cpu.icache.demand_accesses 4051 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35069.791667 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency -system.cpu.icache.demand_hits 3590 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16957000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.119451 # miss rate for demand accesses -system.cpu.icache.demand_misses 487 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_hits 3571 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16833500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.118489 # miss rate for demand accesses +system.cpu.icache.demand_misses 480 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 126 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 12381500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.086829 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.087386 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 354 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.099779 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 204.347725 # Average occupied blocks per context -system.cpu.icache.overall_accesses 4077 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 34819.301848 # average overall miss latency +system.cpu.icache.occ_%::0 0.099792 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 204.373592 # Average occupied blocks per context +system.cpu.icache.overall_accesses 4051 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35069.791667 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3590 # number of overall hits -system.cpu.icache.overall_miss_latency 16957000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.119451 # miss rate for overall accesses -system.cpu.icache.overall_misses 487 # number of overall misses -system.cpu.icache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.icache.overall_hits 3571 # number of overall hits +system.cpu.icache.overall_miss_latency 16833500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.118489 # miss rate for overall accesses +system.cpu.icache.overall_misses 480 # number of overall misses +system.cpu.icache.overall_mshr_hits 126 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 12381500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.086829 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.087386 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 354 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 354 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 204.347725 # Cycle average of tags in use -system.cpu.icache.total_refs 3590 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 204.373592 # Cycle average of tags in use +system.cpu.icache.total_refs 3571 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8573 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3856 # Number of branches executed -system.cpu.iew.EXEC:nop 1087 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.470989 # Inst execution rate -system.cpu.iew.EXEC:refs 4619 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1763 # Number of stores executed +system.cpu.idleCycles 8644 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 3851 # Number of branches executed +system.cpu.iew.EXEC:nop 1086 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.469692 # Inst execution rate +system.cpu.iew.EXEC:refs 4584 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1742 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9338 # num instructions consuming a value -system.cpu.iew.WB:count 17128 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.855858 # average fanout of values written-back +system.cpu.iew.WB:consumers 9307 # num instructions consuming a value +system.cpu.iew.WB:count 17063 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.856022 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7992 # num instructions producing a value -system.cpu.iew.WB:rate 0.459036 # insts written-back per cycle -system.cpu.iew.WB:sent 17304 # cumulative count of insts sent to commit +system.cpu.iew.WB:producers 7967 # num instructions producing a value +system.cpu.iew.WB:rate 0.457858 # insts written-back per cycle +system.cpu.iew.WB:sent 17239 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 800 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 147 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3058 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 566 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispLoadInsts 3044 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 564 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 420 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1925 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 20324 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2856 # Number of load instructions executed +system.cpu.iew.iewDispStoreInsts 1894 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 20242 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2842 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 465 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 17574 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 17504 # Number of executed instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1178 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1159 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 31 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 54 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 30 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 832 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 477 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations +system.cpu.iew.lsq.thread.0.squashedLoads 818 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 446 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 560 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 28146 # number of integer regfile reads -system.cpu.int_regfile_writes 15679 # number of integer regfile writes -system.cpu.ipc 0.387238 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.387238 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28062 # number of integer regfile reads +system.cpu.int_regfile_writes 15640 # number of integer regfile writes +system.cpu.ipc 0.387716 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387716 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 13302 73.74% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2921 16.19% 89.93% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1816 10.07% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 13268 73.84% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2908 16.18% 90.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1793 9.98% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 18039 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 17969 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 125 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006929 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.006956 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 28 22.40% 22.40% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 22.40% # attempts to use FU when none available @@ -329,43 +329,43 @@ system.cpu.iq.ISSUE:fu_full::MemRead 29 23.20% 45.60% # at system.cpu.iq.ISSUE:fu_full::MemWrite 68 54.40% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 28740 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.627662 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.192852 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 28623 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.627782 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.193207 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 19886 69.19% 69.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 4262 14.83% 84.02% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 1894 6.59% 90.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 1722 5.99% 96.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 431 1.50% 98.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 279 0.97% 99.07% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 19805 69.19% 69.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 4241 14.82% 84.01% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 1891 6.61% 90.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 1717 6.00% 96.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 425 1.48% 98.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 278 0.97% 99.07% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::6 172 0.60% 99.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 80 0.28% 99.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 79 0.28% 99.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 28740 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.483451 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 28623 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.482169 # Inst issue rate system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 18164 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 65024 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 17128 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 23367 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 18671 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 18039 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 566 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4088 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.int_alu_accesses 18094 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 64767 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 17063 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 23189 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 18592 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 17969 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 564 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4009 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 89 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3563 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.385542 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34590.361446 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31451.807229 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2871500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2871000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2610500 # number of ReadExReq MSHR miss cycles @@ -390,10 +390,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 500 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34361.895161 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34360.887097 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 17043500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 17043000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.992000 # miss rate for demand accesses system.cpu.l2cache.demand_misses 496 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -403,14 +403,14 @@ system.cpu.l2cache.demand_mshr_misses 496 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.007282 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 238.619810 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.007283 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 238.651434 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 500 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34361.895161 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34360.887097 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 17043500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 17043000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.992000 # miss rate for overall accesses system.cpu.l2cache.overall_misses 496 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -422,38 +422,38 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 238.619810 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 238.651434 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 3058 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1925 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 6238 # number of misc regfile reads +system.cpu.memDep0.insertedLoads 3044 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1894 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 6202 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.numCycles 37313 # number of cpu cycles simulated +system.cpu.numCycles 37267 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 254 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 13569 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 13492 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 112 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 40450 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21815 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 19528 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 7042 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1178 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 40241 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21695 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19448 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 7019 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1159 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 421 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 5696 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:int_rename_lookups 40450 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 6276 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 617 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2691 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 583 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 46980 # The number of ROB reads -system.cpu.rob.rob_writes 41800 # The number of ROB writes -system.cpu.timesIdled 183 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:UndoneMaps 5616 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:int_rename_lookups 40241 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 6278 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 613 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2673 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 579 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 46798 # The number of ROB reads +system.cpu.rob.rob_writes 41616 # The number of ROB writes +system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- |