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authorGabe Black <gblack@eecs.umich.edu>2011-02-07 19:23:11 -0800
committerGabe Black <gblack@eecs.umich.edu>2011-02-07 19:23:11 -0800
commit1b64bfa933745294667158d0ce22180780b2a22e (patch)
tree11822ba69a5ec4c1c4b7ad72fcf08c87e143e4fe /tests/quick/02.insttest/ref/sparc/linux/simple-atomic
parent44e5e7e0533ba2544f2d37f8e051a0422966bd9b (diff)
downloadgem5-1b64bfa933745294667158d0ce22180780b2a22e.tar.xz
Stats: Back out broken update.
Diffstat (limited to 'tests/quick/02.insttest/ref/sparc/linux/simple-atomic')
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini11
-rwxr-xr-xtests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout8
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt24
3 files changed, 9 insertions, 34 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index d09523ca1..91a9c57a5 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -1,22 +1,13 @@
[root]
type=Root
children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
[system.cpu]
type=AtomicSimpleCPU
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
index e27e111a2..a758d34e6 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 6 2011 15:23:54
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb 6 2011 20:47:21
-M5 executing on SC2B0617
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:01
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index 8a0b232a8..970d208fc 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1374672 # Simulator instruction rate (inst/s)
-host_mem_usage 197224 # Number of bytes of host memory used
+host_inst_rate 1098364 # Simulator instruction rate (inst/s)
+host_mem_usage 182400 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 675458817 # Simulator tick rate (ticks/s)
+host_tick_rate 540894569 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 15175 # Number of instructions simulated
sim_seconds 0.000008 # Number of seconds simulated
@@ -11,24 +11,8 @@ sim_ticks 7618500 # Nu
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 15238 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 15238 # Number of busy cycles
-system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 15175 # Number of instructions executed
-system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses
-system.cpu.num_int_insts 12231 # number of integer instructions
-system.cpu.num_int_register_reads 29059 # number of times the integer registers were read
-system.cpu.num_int_register_writes 13832 # number of times the integer registers were written
-system.cpu.num_load_insts 2232 # Number of load instructions
-system.cpu.num_mem_refs 3684 # number of memory refs
-system.cpu.num_store_insts 1452 # Number of store instructions
+system.cpu.num_refs 3684 # Number of memory references
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
---------- End Simulation Statistics ----------