regress: update regressions for tty emulation fix.

3 files changed, 117 insertions, 116 deletions

diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
index fa313ad0d..d0972f695 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -166,6 +166,7 @@ cmd=insttest
 cwd=
 egid=100
 env=
+errout=cerr
 euid=100
 executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
index 882e0c177..27bd0c98d 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  23807                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194964                       # Number of bytes of host memory used
-host_seconds                                     0.46                       # Real time elapsed on the host
-host_tick_rate                               54716973                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  26211                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 210104                       # Number of bytes of host memory used
+host_seconds                                     0.58                       # Real time elapsed on the host
+host_tick_rate                               52105150                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                       10976                       # Number of instructions simulated
-sim_seconds                                  0.000025                       # Number of seconds simulated
-sim_ticks                                    25237000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses               1462                       # number of ReadReq accesses(hits+misses)
+sim_insts                                       15175                       # Number of instructions simulated
+sim_seconds                                  0.000030                       # Number of seconds simulated
+sim_ticks                                    30178000                       # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses               2226                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency        27000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency        24000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits                   1408                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        1458000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.036936                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                   54                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      1296000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.036936                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses              54                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_hits                   2173                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency        1431000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.023810                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                   53                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency      1272000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.023810                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses              53                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses                  6                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_hits                      6                       # number of SwapReq hits
-system.cpu.dcache.WriteReq_accesses              1292                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses              1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency        27000                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency        24000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits                  1187                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency       2835000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.081269                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                 105                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency      2520000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.081269                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses            105                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits                  1340                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency       2754000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.070735                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                 102                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency      2448000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.070735                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses            102                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  18.436620                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  25.623188                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses                2754                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses                3668                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_avg_miss_latency        27000                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency        24000                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                    2595                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         4293000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.057734                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                   159                       # number of demand (read+write) misses
+system.cpu.dcache.demand_hits                    3513                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency         4185000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.042257                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                   155                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      3816000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.057734                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses              159                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency      3720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.042257                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses              155                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses               2754                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses               3668                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency        27000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        24000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                   2595                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        4293000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.057734                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                  159                       # number of overall misses
+system.cpu.dcache.overall_hits                   3513                       # number of overall hits
+system.cpu.dcache.overall_miss_latency        4185000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.042257                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                  155                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      3816000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.057734                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses             159                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency      3720000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.042257                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses             155                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -76,56 +76,56 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.sampled_refs                    142                       # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 99.913779                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2618                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                102.837167                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     3536                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_accesses              11012                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 26908.127208                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23908.127208                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits                  10729                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency        7615000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.025699                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  283                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency      6766000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.025699                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             283                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses              15221                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 26907.142857                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23907.142857                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits                  14941                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency        7534000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.018396                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                  280                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency      6694000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.018396                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses             280                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  37.911661                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  53.360714                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses               11012                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 26908.127208                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23908.127208                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                   10729                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         7615000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.025699                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   283                       # number of demand (read+write) misses
+system.cpu.icache.demand_accesses               15221                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 26907.142857                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23907.142857                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                   14941                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency         7534000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.018396                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                   280                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency      6766000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.025699                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              283                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency      6694000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.018396                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses              280                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses              11012                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 26908.127208                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23908.127208                       # average overall mshr miss latency
+system.cpu.icache.overall_accesses              15221                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 26907.142857                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23907.142857                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits                  10729                       # number of overall hits
-system.cpu.icache.overall_miss_latency        7615000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.025699                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  283                       # number of overall misses
+system.cpu.icache.overall_hits                  14941                       # number of overall hits
+system.cpu.icache.overall_miss_latency        7534000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.018396                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                  280                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency      6766000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.025699                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             283                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency      6694000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.018396                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses             280                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -138,32 +138,32 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.sampled_refs                    283                       # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs                    280                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                154.924957                       # Cycle average of tags in use
-system.cpu.icache.total_refs                    10729                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                165.376172                       # Cycle average of tags in use
+system.cpu.icache.total_refs                    14941                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses              88                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses              85                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        23000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency      2024000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      1955000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses                88                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency       968000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses                85                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency       935000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses           88                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses               337                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_mshr_misses           85                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses               333                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        23000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency       7705000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.994065                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 335                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency      3685000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994065                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            335                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency       7613000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.993994                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                 331                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency      3641000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.993994                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses            331                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses             17                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_avg_miss_latency        23000                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
@@ -175,38 +175,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1
 system.cpu.l2cache.UpgradeReq_mshr_misses           17                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.006289                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.006369                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                425                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses                418                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        23000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency        9729000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.995294                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                  423                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency        9568000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.995215                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                  416                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency      4653000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.995294                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses             423                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency      4576000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.995215                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses             416                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses               425                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses               418                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        23000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency       9729000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.995294                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                 423                       # number of overall misses
+system.cpu.l2cache.overall_miss_latency       9568000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.995215                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                 416                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency      4653000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.995294                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses            423                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency      4576000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.995215                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses            416                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -219,16 +219,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                   318                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   314                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               176.975795                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               187.735043                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                            50474                       # number of cpu cycles simulated
-system.cpu.num_insts                            10976                       # Number of instructions executed
-system.cpu.num_refs                              2770                       # Number of memory references
-system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
+system.cpu.numCycles                            60356                       # number of cpu cycles simulated
+system.cpu.num_insts                            15175                       # Number of instructions executed
+system.cpu.num_refs                              3684                       # Number of memory references
+system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
index e7f5d2afa..2511a0e62 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul 21 2008 20:33:06
-M5 started Mon Jul 21 20:33:19 2008
-M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 compiled Jul 23 2008 16:00:51
+M5 started Wed Jul 23 16:03:20 2008
+M5 executing on blue
+M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
+M5 commit date Wed Jul 23 15:35:08 2008 -0700
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 Begining test of difficult SPARC instructions...
@@ -23,4 +23,4 @@ LDTX:		Passed
 LDTW:		Passed
 STTW:		Passed
 Done
-Exiting @ tick 25237000 because target called exit()
+Exiting @ tick 30178000 because target called exit()