Update refs for CPU clock changes and O3 CPI/IPC calculation updates.

tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/mips/linux/simple-timing/config.out:
tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/mips/linux/simple-timing/stdout:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out:
tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout:
    Update refs.

--HG--
extra : convert_revision : 34a0d18f213386700e2acdd1eb9ebc5fa6daa7f5

5 files changed, 56 insertions, 57 deletions

diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 85d14933a..394f564a5 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -12,7 +12,7 @@ physmem=system.physmem
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache icache l2cache toL2Bus workload
-clock=1
+clock=500
 cpu_id=0
 defer_registration=false
 function_trace=false
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out
index ec2d1886a..9d999c4c3 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out
@@ -47,7 +47,7 @@ progress_interval=0
 system=system
 cpu_id=0
 workload=system.cpu.workload
-clock=1
+clock=500
 phase=0
 defer_registration=false
 // width not specified
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
index a4396b3da..aef9433e6 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  39129                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 153232                       # Number of bytes of host memory used
-host_seconds                                     0.28                       # Real time elapsed on the host
-host_tick_rate                                6030675                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 285170                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 154424                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                              211576923                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       11001                       # Number of instructions simulated
-sim_seconds                                  0.000002                       # Number of seconds simulated
-sim_ticks                                     1698003                       # Number of ticks simulated
+sim_seconds                                  0.000008                       # Number of seconds simulated
+sim_ticks                                     8251500                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses               1462                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  3977.759259                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2977.759259                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency  3712.962963                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2712.962963                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits                   1408                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency         214799                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency         200500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.036936                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                   54                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency       160799                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency       146500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.036936                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses              54                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses                  6                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_hits                      6                       # number of SwapReq hits
 system.cpu.dcache.WriteReq_accesses              1292                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  3963.647727                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2963.647727                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency  3676.136364                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2676.136364                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits                  1204                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency        348801                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency        323500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.068111                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                  88                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency       260801                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency       235500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.068111                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses             88                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -39,29 +39,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses                2754                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  3969.014085                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  2969.014085                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency  3690.140845                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  2690.140845                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                    2612                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency          563600                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency          524000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.051561                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                   142                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency       421600                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency       382000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.051561                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses              142                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses               2754                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  3969.014085                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  2969.014085                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency  3690.140845                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  2690.140845                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                   2612                       # number of overall hits
-system.cpu.dcache.overall_miss_latency         563600                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency         524000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.051561                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                  142                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency       421600                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency       382000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.051561                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses             142                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -78,18 +78,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    142                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 86.872921                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                106.692969                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     2618                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
 system.cpu.icache.ReadReq_accesses              11002                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  3961.367491                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  2961.367491                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency  3743.816254                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  2743.816254                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits                  10719                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency        1121067                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency        1059500                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.025723                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  283                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency       838067                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency       776500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.025723                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             283                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -101,29 +101,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses               11002                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  3961.367491                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  2961.367491                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency  3743.816254                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  2743.816254                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                   10719                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         1121067                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency         1059500                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.025723                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   283                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency       838067                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency       776500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.025723                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              283                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses              11002                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  3961.367491                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  2961.367491                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency  3743.816254                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  2743.816254                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                  10719                       # number of overall hits
-system.cpu.icache.overall_miss_latency        1121067                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency        1059500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.025723                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  283                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency       838067                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency       776500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.025723                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             283                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -140,18 +140,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    283                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                125.297191                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                170.449932                       # Cycle average of tags in use
 system.cpu.icache.total_refs                    10719                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadReq_accesses               423                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  2968.515366                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1967.515366                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency       1255682                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_avg_miss_latency  2730.496454                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1729.496454                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency       1155000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate                1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                 423                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency       832259                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency       731577                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            423                       # number of ReadReq MSHR misses
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -163,29 +163,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses                423                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  2968.515366                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  1967.515366                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency  2730.496454                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  1729.496454                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                      0                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency        1255682                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency        1155000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate                 1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  423                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency       832259                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency       731577                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             423                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses               423                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  2968.515366                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  1967.515366                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency  2730.496454                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  1729.496454                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     0                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency       1255682                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency       1155000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 423                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency       832259                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency       731577                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_rate            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses            423                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -202,12 +202,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   423                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               211.742547                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               276.385948                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                          1698003                       # number of cpu cycles simulated
+system.cpu.numCycles                          8251500                       # number of cpu cycles simulated
 system.cpu.num_insts                            11001                       # Number of instructions executed
 system.cpu.num_refs                              2760                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr
index fce46c90e..7873672f2 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr
@@ -1,4 +1,3 @@
 warn: More than two loadable segments in ELF object.
 warn: Ignoring segment @ 0x0 length 0x0.
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
 warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
index 100a1ebce..dd4d8d282 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
@@ -16,9 +16,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr  8 2007 05:25:15
-M5 started Sun Apr  8 22:54:12 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Apr 22 2007 20:15:56
+M5 started Sun Apr 22 20:26:07 2007
+M5 executing on zamp.eecs.umich.edu
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 1698003 because target called exit()
+Exiting @ tick 8251500 because target called exit()