Update statistics for the last three revisions

--HG--
extra : convert_revision : 117e2a40bd6e0867d013a3a6076fb758ac526d24

5 files changed, 20 insertions, 26 deletions

diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
index eae7625e9..3c63b3005 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                   2012                       # Nu
 global.BPredUnit.condPredicted                   7659                       # Number of conditional branches predicted
 global.BPredUnit.lookups                         7659                       # Number of BP lookups
 global.BPredUnit.usedRAS                            0                       # Number of times the RAS was used to get a target.
-host_inst_rate                                   7502                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 186228                       # Number of bytes of host memory used
-host_seconds                                     1.39                       # Real time elapsed on the host
-host_tick_rate                               10800438                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  64485                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 198296                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
+host_tick_rate                               92733729                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 15                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                 0                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                  3077                       # Number of loads inserted to the mem dependence unit.
@@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls             329                       # Th
 system.cpu.commit.commitSquashedInsts           13198                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                       10411                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                 10411                       # Number of Instructions Simulated
-system.cpu.cpi                               2.871770                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.871770                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               2.879839                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.879839                       # CPI: Total CPI of All Threads
 system.cpu.dcache.ReadReq_accesses               2274                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency  9734.848485                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency  5560.606061                       # average ReadReq mshr miss latency
@@ -139,10 +139,10 @@ system.cpu.fetch.Cycles                         16219                       # Nu
 system.cpu.fetch.IcacheSquashes                   589                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.Insts                          42202                       # Number of instructions fetch has processed
 system.cpu.fetch.SquashCycles                    2099                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.256171                       # Number of branch fetches per cycle
+system.cpu.fetch.branchRate                  0.255453                       # Number of branch fetches per cycle
 system.cpu.fetch.icacheStallCycles               4927                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches               2711                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.411533                       # Number of inst fetches per cycle
+system.cpu.fetch.rate                        1.407578                       # Number of inst fetches per cycle
 system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist.samples               29898                      
 system.cpu.fetch.rateDist.min_value                 0                      
@@ -221,10 +221,10 @@ system.cpu.icache.tagsinuse                233.477311                       # Cy
 system.cpu.icache.total_refs                     4537                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                           51980                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                              84                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.iew.EXEC:branches                     3086                       # Number of branches executed
 system.cpu.iew.EXEC:nop                          1794                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.576995                       # Inst execution rate
+system.cpu.iew.EXEC:rate                     0.575379                       # Inst execution rate
 system.cpu.iew.EXEC:refs                         4543                       # number of memory reference insts executed
 system.cpu.iew.EXEC:stores                       2116                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
@@ -234,7 +234,7 @@ system.cpu.iew.WB:fanout                     0.827620                       # av
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.WB:producers                      7605                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.555823                       # insts written-back per cycle
+system.cpu.iew.WB:rate                       0.554266                       # insts written-back per cycle
 system.cpu.iew.WB:sent                          16830                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts                 2216                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewBlockCycles                       0                       # Number of cycles IEW is blocking
@@ -264,8 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores         1658                       #
 system.cpu.iew.memOrderViolationEvents             57                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          695                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect           1521                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               0.348217                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.348217                       # IPC: Total IPC of All Threads
+system.cpu.ipc                               0.347242                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.347242                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0                   20089                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
                       No_OpClass            0      0.00%            # Type of FU issued
@@ -316,7 +316,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
 
-system.cpu.iq.ISSUE:rate                     0.671918                       # Inst issue rate
+system.cpu.iq.ISSUE:rate                     0.670035                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                      21924                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                     20089                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 612                       # Number of non-speculative instructions added to the IQ
@@ -404,7 +404,7 @@ system.cpu.l2cache.tagsinuse               259.708792                       # Cy
 system.cpu.l2cache.total_refs                       4                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                            29898                       # number of cpu cycles simulated
+system.cpu.numCycles                            29982                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:CommittedMaps           9868                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IdleCycles             14192                       # Number of cycles rename is idle
 system.cpu.rename.RENAME:RenameLookups          51924                       # Number of register rename lookups that rename has made
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr
index 7873672f2..87866a2a5 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr
@@ -1,3 +1 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr
index 7873672f2..87866a2a5 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr
@@ -1,3 +1 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
index 4a899f629..49b40d3b8 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 343655                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 180816                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
-host_tick_rate                              753768067                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 472716                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197656                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                             1037354119                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       10976                       # Number of instructions simulated
 sim_seconds                                  0.000024                       # Number of seconds simulated
@@ -226,7 +226,7 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                         24355000                       # number of cpu cycles simulated
+system.cpu.numCycles                            48710                       # number of cpu cycles simulated
 system.cpu.num_insts                            10976                       # Number of instructions executed
 system.cpu.num_refs                              2770                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr
index 7873672f2..87866a2a5 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr
@@ -1,3 +1 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...