diff options
| author | Nathan Binkert <nate@binkert.org> | 2009-04-22 10:25:17 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-04-22 10:25:17 -0700 |
| commit | 567cab685965e4e627ac1541a9fdacb93fd6e5fe (patch) | |
| tree | d79f8cfd677dfc314ccb48630b77785412a9f1bd /tests/quick/02.insttest/ref/sparc/linux | |
| parent | ca3d82b38ab92114f5056a35bacf0dceb8b6d4a6 (diff) | |
| download | gem5-567cab685965e4e627ac1541a9fdacb93fd6e5fe.tar.xz | |
stats: update reference outputs now that compatibility is gone
Because of the initialization bug, it wasn't consistent anyway.
Diffstat (limited to 'tests/quick/02.insttest/ref/sparc/linux')
4 files changed, 104 insertions, 108 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 34998e971..4f7aebff8 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:05:07 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:32:52 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 3e04b78ab..a3713da81 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 47616 # Simulator instruction rate (inst/s) -host_mem_usage 201812 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 91393866 # Simulator tick rate (ticks/s) +host_inst_rate 75091 # Simulator instruction rate (inst/s) +host_mem_usage 203556 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host +host_tick_rate 144061639 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000028 # Number of seconds simulated @@ -73,13 +73,13 @@ system.cpu.dcache.WriteReq_mshr_hits 341 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 3634500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 32.229730 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 32057.347670 # average overall miss latency @@ -98,7 +98,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 4728 # number of overall hits system.cpu.dcache.overall_miss_latency 17888000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.105562 # miss rate for overall accesses @@ -160,13 +160,13 @@ system.cpu.icache.ReadReq_mshr_hits 176 # nu system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.048804 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 19.053073 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 7356 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 33620.560748 # average overall miss latency @@ -185,7 +185,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 6821 # number of overall hits system.cpu.icache.overall_miss_latency 17987000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.072730 # miss rate for overall accesses @@ -248,58 +248,54 @@ system.cpu.iew.predictedNotTakenIncorrect 758 # N system.cpu.iew.predictedTakenIncorrect 2453 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.260277 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.260277 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 29220 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 21395 73.22% # Type of FU issued - IntMult 0 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 0 0.00% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 4720 16.15% # Type of FU issued - MemWrite 3105 10.63% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 21395 73.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 4720 16.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 3105 10.63% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 29220 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.005921 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 40 23.12% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 20 11.56% # attempts to use FU when none available - MemWrite 113 65.32% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 47090 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 34112 72.44% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 5516 11.71% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 3070 6.52% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 2146 4.56% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 997 2.12% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 653 1.39% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 342 0.73% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 211 0.45% -system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 47090 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.620514 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.275912 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 40 23.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 20 11.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 113 65.32% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 47090 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 34112 72.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 5516 11.71% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 3070 6.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 2146 4.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 997 2.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 653 1.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 342 0.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 211 0.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 47090 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.620514 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.275912 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued @@ -336,13 +332,13 @@ system.cpu.l2cache.UpgradeReq_misses 19 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34252.485089 # average overall miss latency @@ -361,7 +357,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits system.cpu.l2cache.overall_miss_latency 17229000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout index 4ea7967d3..76cbb3c5f 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:15:57 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:32:53 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 43fac0d7a..5c475dff1 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 347867 # Simulator instruction rate (inst/s) -host_mem_usage 201056 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 973883913 # Simulator tick rate (ticks/s) +host_inst_rate 286976 # Simulator instruction rate (inst/s) +host_mem_usage 202788 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 804151064 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000043 # Number of seconds simulated @@ -30,13 +30,13 @@ system.cpu.dcache.WriteReq_misses 102 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 5406000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency @@ -55,7 +55,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 3513 # number of overall hits system.cpu.dcache.overall_miss_latency 8680000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses @@ -83,13 +83,13 @@ system.cpu.icache.ReadReq_misses 280 # nu system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency @@ -108,7 +108,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 14941 # number of overall hits system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses @@ -155,13 +155,13 @@ system.cpu.l2cache.UpgradeReq_misses 17 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 680000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.006369 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -180,7 +180,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses |