diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:11 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:11 -0800 |
| commit | 1b64bfa933745294667158d0ce22180780b2a22e (patch) | |
| tree | 11822ba69a5ec4c1c4b7ad72fcf08c87e143e4fe /tests/quick/02.insttest/ref/sparc/linux | |
| parent | 44e5e7e0533ba2544f2d37f8e051a0422966bd9b (diff) | |
| download | gem5-1b64bfa933745294667158d0ce22180780b2a22e.tar.xz | |
Stats: Back out broken update.
Diffstat (limited to 'tests/quick/02.insttest/ref/sparc/linux')
9 files changed, 33 insertions, 110 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index d70bc91f6..285549a9c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -1,22 +1,13 @@ [root] type=Root children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 +dummy=0 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -493,7 +484,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 41e283efb..7c5c285a5 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 6 2011 15:23:54 -M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates -M5 started Feb 6 2011 20:47:21 -M5 executing on SC2B0617 +M5 compiled Jan 17 2011 21:17:52 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 21:18:06 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index e3bbf84bb..5aa081cb3 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 112587 # Simulator instruction rate (inst/s) -host_mem_usage 205776 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 145080138 # Simulator tick rate (ticks/s) +host_inst_rate 91156 # Simulator instruction rate (inst/s) +host_mem_usage 203828 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 117504787 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000019 # Number of seconds simulated @@ -37,9 +37,6 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 27579 # Number of insts commited each cycle system.cpu.commit.COM:count 15175 # Number of instructions committed -system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 12186 # Number of committed integer instructions. system.cpu.commit.COM:loads 2226 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 3674 # Number of memory references committed @@ -254,8 +251,6 @@ system.cpu.iew.lsq.thread.0.squashedStores 477 # system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 560 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 28146 # number of integer regfile reads -system.cpu.int_regfile_writes 15679 # number of integer regfile writes system.cpu.ipc 0.387238 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.387238 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -347,14 +342,6 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 28740 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.483451 # Inst issue rate -system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 18164 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 65024 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 17128 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 23367 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 18671 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 18039 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 566 # Number of non-speculative instructions added to the IQ @@ -430,11 +417,7 @@ system.cpu.memDep0.conflictingLoads 13 # Nu system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 3058 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1925 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 6238 # number of misc regfile reads -system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.numCycles 37313 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 254 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 13569 # Number of cycles rename is idle @@ -446,13 +429,10 @@ system.cpu.rename.RENAME:RunCycles 7042 # Nu system.cpu.rename.RENAME:SquashCycles 1178 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 421 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 5696 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:int_rename_lookups 40450 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 6276 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 617 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 2691 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 583 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 46980 # The number of ROB reads -system.cpu.rob.rob_writes 41800 # The number of ROB writes system.cpu.timesIdled 183 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index d09523ca1..91a9c57a5 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -1,22 +1,13 @@ [root] type=Root children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 +dummy=0 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 [system.cpu] type=AtomicSimpleCPU diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout index e27e111a2..a758d34e6 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 6 2011 15:23:54 -M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates -M5 started Feb 6 2011 20:47:21 -M5 executing on SC2B0617 +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:38:01 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 8a0b232a8..970d208fc 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1374672 # Simulator instruction rate (inst/s) -host_mem_usage 197224 # Number of bytes of host memory used +host_inst_rate 1098364 # Simulator instruction rate (inst/s) +host_mem_usage 182400 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 675458817 # Simulator tick rate (ticks/s) +host_tick_rate 540894569 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000008 # Number of seconds simulated @@ -11,24 +11,8 @@ sim_ticks 7618500 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 15238 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 15238 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 15175 # Number of instructions executed -system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses -system.cpu.num_int_insts 12231 # number of integer instructions -system.cpu.num_int_register_reads 29059 # number of times the integer registers were read -system.cpu.num_int_register_writes 13832 # number of times the integer registers were written -system.cpu.num_load_insts 2232 # Number of load instructions -system.cpu.num_mem_refs 3684 # number of memory refs -system.cpu.num_store_insts 1452 # Number of store instructions +system.cpu.num_refs 3684 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index e0d239809..04665360b 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -1,22 +1,13 @@ [root] type=Root children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 +dummy=0 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -166,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout index e887d8fcb..27524a121 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simout +Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 6 2011 15:23:54 -M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates -M5 started Feb 6 2011 20:47:21 -M5 executing on SC2B0617 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing +M5 compiled Aug 26 2010 13:03:41 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:03:44 +M5 executing on zizzer +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 5e10ec9cc..6c8846c5d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 702644 # Simulator instruction rate (inst/s) -host_mem_usage 204952 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1909286073 # Simulator tick rate (ticks/s) +host_inst_rate 255958 # Simulator instruction rate (inst/s) +host_mem_usage 207264 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 701295215 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000042 # Number of seconds simulated @@ -197,24 +197,8 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 83600 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 83600 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 15175 # Number of instructions executed -system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses -system.cpu.num_int_insts 12231 # number of integer instructions -system.cpu.num_int_register_reads 29059 # number of times the integer registers were read -system.cpu.num_int_register_writes 13831 # number of times the integer registers were written -system.cpu.num_load_insts 2232 # Number of load instructions -system.cpu.num_mem_refs 3684 # number of memory refs -system.cpu.num_store_insts 1452 # Number of store instructions +system.cpu.num_refs 3684 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- |