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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:06 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:06 -0600 |
| commit | 9b67f3723e48efdd0a0b640ff82cfcf8aad3a659 (patch) | |
| tree | 79c5001cce6b9d92d1ad04d4a2cd4e442f56803c /tests/quick/02.insttest/ref/sparc/linux | |
| parent | 77853b9f529947c3a9db78ef3458289f387289ce (diff) | |
| download | gem5-9b67f3723e48efdd0a0b640ff82cfcf8aad3a659.tar.xz | |
Stats: Update stats for previous set of patches.
Diffstat (limited to 'tests/quick/02.insttest/ref/sparc/linux')
| -rwxr-xr-x | tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 11 |
2 files changed, 10 insertions, 9 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index f550d7f17..7c5c285a5 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 15 2011 04:38:18 -M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip -M5 started Jan 15 2011 04:38:23 -M5 executing on tater +M5 compiled Jan 17 2011 21:17:52 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 21:18:06 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index e87194a60..5aa081cb3 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 46971 # Simulator instruction rate (inst/s) -host_mem_usage 216748 # Number of bytes of host memory used -host_seconds 0.31 # Real time elapsed on the host -host_tick_rate 60590117 # Simulator tick rate (ticks/s) +host_inst_rate 91156 # Simulator instruction rate (inst/s) +host_mem_usage 203828 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 117504787 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000019 # Number of seconds simulated @@ -126,9 +126,10 @@ system.cpu.decode.DECODE:SquashCycles 1178 # Nu system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking system.cpu.fetch.Branches 5172 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 4077 # Number of cache lines fetched -system.cpu.fetch.Cycles 11611 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 7506 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 23982 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 826 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.138611 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 4077 # Number of cycles fetch is stalled on an Icache miss |