diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
| commit | a51e2fd8bd581d45f8a87874c9a6680f99d11e24 (patch) | |
| tree | 8de4626b115b234de0962cc04d32e15b6eb0fa3a /tests/quick/02.insttest/ref/sparc | |
| parent | e7e2d5ce9072808d94d5fe399e6c4262d92b7923 (diff) | |
| download | gem5-a51e2fd8bd581d45f8a87874c9a6680f99d11e24.tar.xz | |
Stats: Update the stats.
--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
Diffstat (limited to 'tests/quick/02.insttest/ref/sparc')
9 files changed, 329 insertions, 295 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index bfef15018..8c35e4da1 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -36,6 +36,7 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -53,6 +54,7 @@ iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 +itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 @@ -130,6 +132,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 @@ -303,6 +309,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=SparcITB +size=64 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index 0f88834b5..eae7625e9 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 2657 # Number of BTB hits -global.BPredUnit.BTBLookups 6786 # Number of BTB lookups +global.BPredUnit.BTBHits 2711 # Number of BTB hits +global.BPredUnit.BTBLookups 6964 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1999 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 7531 # Number of conditional branches predicted -global.BPredUnit.lookups 7531 # Number of BP lookups +global.BPredUnit.condIncorrect 2012 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 7659 # Number of conditional branches predicted +global.BPredUnit.lookups 7659 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 57578 # Simulator instruction rate (inst/s) -host_mem_usage 198128 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 76965798 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads. +host_inst_rate 7502 # Simulator instruction rate (inst/s) +host_mem_usage 186228 # Number of bytes of host memory used +host_seconds 1.39 # Real time elapsed on the host +host_tick_rate 10800438 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 3022 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 2929 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 3077 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 2956 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 10976 # Number of instructions simulated +sim_insts 10411 # Number of instructions simulated sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 14690000 # Number of ticks simulated +sim_ticks 14990500 # Number of ticks simulated system.cpu.commit.COM:branches 2152 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 93 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 87 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 26502 +system.cpu.commit.COM:committed_per_cycle.samples 26989 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 20989 7919.78% - 1 3011 1136.14% - 2 1202 453.55% - 3 588 221.87% - 4 307 115.84% - 5 82 30.94% - 6 195 73.58% - 7 35 13.21% - 8 93 35.09% + 0 21416 7935.08% + 1 3114 1153.80% + 2 1160 429.80% + 3 589 218.24% + 4 306 113.38% + 5 84 31.12% + 6 196 72.62% + 7 37 13.71% + 8 87 32.24% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 1462 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2760 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1999 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 2012 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 329 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 13065 # The number of squashed insts skipped by commit -system.cpu.committedInsts 10976 # Number of Instructions Simulated -system.cpu.committedInsts_total 10976 # Number of Instructions Simulated -system.cpu.cpi 2.675656 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.675656 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2253 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9417.910448 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5611.940299 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2186 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 631000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.029738 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 67 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.029738 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses +system.cpu.commit.commitSquashedInsts 13198 # The number of squashed insts skipped by commit +system.cpu.committedInsts 10411 # Number of Instructions Simulated +system.cpu.committedInsts_total 10411 # Number of Instructions Simulated +system.cpu.cpi 2.871770 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.871770 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2274 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 9734.848485 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5560.606061 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2208 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 642500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.029024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 66 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 367000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.029024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1171 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 16509.523810 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5709.523810 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 16414.285714 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5623.809524 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1066 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1733500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1723500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089667 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 121 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 599500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 590500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089667 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 21.418301 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 21.703947 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3424 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 13747.093023 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5671.511628 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3252 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2364500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.050234 # miss rate for demand accesses -system.cpu.dcache.demand_misses 172 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 141 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 975500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.050234 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 172 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 3445 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13836.257310 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5599.415205 # average overall mshr miss latency +system.cpu.dcache.demand_hits 3274 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2366000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.049637 # miss rate for demand accesses +system.cpu.dcache.demand_misses 171 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 146 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 957500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.049637 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 3424 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 13747.093023 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5671.511628 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 3445 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13836.257310 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5599.415205 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3252 # number of overall hits -system.cpu.dcache.overall_miss_latency 2364500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.050234 # miss rate for overall accesses -system.cpu.dcache.overall_misses 172 # number of overall misses -system.cpu.dcache.overall_mshr_hits 141 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 975500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.050234 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 172 # number of overall MSHR misses +system.cpu.dcache.overall_hits 3274 # number of overall hits +system.cpu.dcache.overall_miss_latency 2366000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.049637 # miss rate for overall accesses +system.cpu.dcache.overall_misses 171 # number of overall misses +system.cpu.dcache.overall_mshr_hits 146 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 957500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.049637 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 153 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 112.521037 # Cycle average of tags in use -system.cpu.dcache.total_refs 3277 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 111.288485 # Cycle average of tags in use +system.cpu.dcache.total_refs 3299 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 4038 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 37564 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 12395 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 10006 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2866 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 63 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 7531 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4872 # Number of cache lines fetched -system.cpu.fetch.Cycles 15997 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 41653 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2060 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.256436 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4872 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 2657 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.418312 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 3945 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 38084 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 12820 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 10159 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2909 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 65 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 7659 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4927 # Number of cache lines fetched +system.cpu.fetch.Cycles 16219 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 589 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 42202 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2099 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.256171 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4927 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 2711 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.411533 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 29368 +system.cpu.fetch.rateDist.samples 29898 system.cpu.fetch.rateDist.min_value 0 - 0 18244 6212.20% - 1 4822 1641.92% - 2 611 208.05% - 3 702 239.04% - 4 788 268.32% - 5 623 212.14% - 6 599 203.96% - 7 190 64.70% - 8 2789 949.67% + 0 18628 6230.52% + 1 4885 1633.89% + 2 619 207.04% + 3 712 238.14% + 4 788 263.56% + 5 640 214.06% + 6 611 204.36% + 7 195 65.22% + 8 2820 943.21% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 4851 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7514.784946 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5338.709677 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4479 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2795500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.076685 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 372 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 21 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1986000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.076685 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 372 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 4907 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7495.945946 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5325.675676 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 4537 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 2773500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.075402 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 370 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1970500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.075402 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 12.040323 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12.262162 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4851 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7514.784946 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5338.709677 # average overall mshr miss latency -system.cpu.icache.demand_hits 4479 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2795500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.076685 # miss rate for demand accesses -system.cpu.icache.demand_misses 372 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 21 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1986000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.076685 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 4907 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7495.945946 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5325.675676 # average overall mshr miss latency +system.cpu.icache.demand_hits 4537 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 2773500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.075402 # miss rate for demand accesses +system.cpu.icache.demand_misses 370 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 20 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1970500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.075402 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 370 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4851 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7514.784946 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5338.709677 # average overall mshr miss latency +system.cpu.icache.overall_accesses 4907 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7495.945946 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5325.675676 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4479 # number of overall hits -system.cpu.icache.overall_miss_latency 2795500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.076685 # miss rate for overall accesses -system.cpu.icache.overall_misses 372 # number of overall misses -system.cpu.icache.overall_mshr_hits 21 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1986000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.076685 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 372 # number of overall MSHR misses +system.cpu.icache.overall_hits 4537 # number of overall hits +system.cpu.icache.overall_miss_latency 2773500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.075402 # miss rate for overall accesses +system.cpu.icache.overall_misses 370 # number of overall misses +system.cpu.icache.overall_mshr_hits 20 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1970500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.075402 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 370 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,61 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 372 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 370 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 236.918934 # Cycle average of tags in use -system.cpu.icache.total_refs 4479 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 233.477311 # Cycle average of tags in use +system.cpu.icache.total_refs 4537 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8496 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3046 # Number of branches executed -system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.623842 # Inst execution rate -system.cpu.iew.EXEC:refs 4481 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2103 # Number of stores executed +system.cpu.idleCycles 51980 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 3086 # Number of branches executed +system.cpu.iew.EXEC:nop 1794 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.576995 # Inst execution rate +system.cpu.iew.EXEC:refs 4543 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2116 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9128 # num instructions consuming a value -system.cpu.iew.WB:count 17742 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.828330 # average fanout of values written-back +system.cpu.iew.WB:consumers 9189 # num instructions consuming a value +system.cpu.iew.WB:count 16618 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.827620 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7561 # num instructions producing a value -system.cpu.iew.WB:rate 0.604127 # insts written-back per cycle -system.cpu.iew.WB:sent 17903 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2179 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 7605 # num instructions producing a value +system.cpu.iew.WB:rate 0.555823 # insts written-back per cycle +system.cpu.iew.WB:sent 16830 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2216 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3022 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 611 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2901 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2929 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 24042 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2378 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3319 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 18321 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 3077 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 612 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2973 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2956 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 24330 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2427 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2838 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 17251 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2866 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 2909 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 57 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1560 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1631 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 60 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 684 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1495 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.373740 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.373740 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 21640 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 1615 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1658 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 57 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 695 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1521 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.348217 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.348217 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 20089 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 1766 8.16% # Type of FU issued - IntAlu 14389 66.49% # Type of FU issued + No_OpClass 0 0.00% # Type of FU issued + IntAlu 14535 72.35% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -278,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 2855 13.19% # Type of FU issued - MemWrite 2630 12.15% # Type of FU issued + MemRead 2907 14.47% # Type of FU issued + MemWrite 2647 13.18% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.008364 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 188 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009358 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 43 23.76% # attempts to use FU when none available + IntAlu 50 26.60% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,53 +296,53 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 23 12.71% # attempts to use FU when none available - MemWrite 115 63.54% # attempts to use FU when none available + MemRead 23 12.23% # attempts to use FU when none available + MemWrite 115 61.17% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 29368 +system.cpu.iq.ISSUE:issued_per_cycle.samples 29898 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 20067 6832.95% - 1 3826 1302.78% - 2 2129 724.94% - 3 1515 515.87% - 4 870 296.24% - 5 480 163.44% - 6 307 104.54% - 7 103 35.07% - 8 71 24.18% + 0 21040 7037.26% + 1 3621 1211.12% + 2 2127 711.42% + 3 1561 522.11% + 4 748 250.18% + 5 407 136.13% + 6 293 98.00% + 7 62 20.74% + 8 39 13.04% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.736856 # Inst issue rate -system.cpu.iq.iqInstsAdded 23431 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 21640 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 611 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 11038 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 7964 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:rate 0.671918 # Inst issue rate +system.cpu.iq.iqInstsAdded 21924 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 20089 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 612 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 10307 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 86 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4430.232558 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2430.232558 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 381000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 4424.418605 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2424.418605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 380500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 86 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 209000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 208500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 86 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 439 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4291.954023 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2291.954023 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4287.037037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2287.037037 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1867000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990888 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 435 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 997000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990888 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 435 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 1852000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990826 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 432 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 988000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990826 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 432 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 4421.052632 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2421.052632 # average UpgradeReq mshr miss latency @@ -354,38 +354,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.009615 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.009685 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 525 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4314.779271 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2314.779271 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 522 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4309.845560 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2309.845560 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2248000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992381 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 521 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 2232500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992337 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 518 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1206000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992381 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 521 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1196500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992337 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 518 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 525 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4314.779271 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2314.779271 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 522 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4309.845560 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2309.845560 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2248000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992381 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 521 # number of overall misses +system.cpu.l2cache.overall_miss_latency 2232500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992337 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 518 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1206000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992381 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 521 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1196500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992337 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 518 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -398,27 +398,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 263.558349 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 259.708792 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 29368 # number of cpu cycles simulated +system.cpu.numCycles 29898 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 13747 # Number of cycles rename is idle -system.cpu.rename.RENAME:RenameLookups 51214 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 29558 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 24111 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 8739 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2866 # Number of cycles rename is squashing +system.cpu.rename.RENAME:IdleCycles 14192 # Number of cycles rename is idle +system.cpu.rename.RENAME:RenameLookups 51924 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 30001 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 24487 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 8874 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2909 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 230 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 14243 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 3786 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 643 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4459 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 681 # count of temporary serializing insts renamed -system.cpu.timesIdled 4 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:UndoneMaps 14619 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 3693 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 648 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4472 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 685 # count of temporary serializing insts renamed +system.cpu.timesIdled 20 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index 9ba201750..82d7a93ac 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 00:08:15 -M5 started Tue Aug 14 00:08:28 2007 -M5 executing on zeep -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing +M5 compiled Aug 19 2007 19:19:06 +M5 started Sun Aug 19 19:19:36 2007 +M5 executing on nacho +command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 14690000 because target called exit() +Exiting @ tick 14990500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 5493b952f..f3afb96c0 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -25,11 +27,23 @@ phase=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu.tracer width=1 workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + +[system.cpu.itb] +type=SparcITB +size=64 + +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=insttest @@ -37,7 +51,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin output=cout @@ -53,7 +67,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt index 468b3f0a1..9a14dd885 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 563720 # Simulator instruction rate (inst/s) -host_mem_usage 149048 # Number of bytes of host memory used +host_inst_rate 464357 # Simulator instruction rate (inst/s) +host_mem_usage 173536 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 276035132 # Simulator tick rate (ticks/s) +host_tick_rate 229778722 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 11001 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5500000 # Number of ticks simulated +sim_insts 10976 # Number of instructions simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 5514000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11001 # number of cpu cycles simulated -system.cpu.num_insts 11001 # Number of instructions executed -system.cpu.num_refs 2760 # Number of memory references +system.cpu.numCycles 11029 # number of cpu cycles simulated +system.cpu.num_insts 10976 # Number of instructions executed +system.cpu.num_refs 2770 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout index 01c59e833..1641f2696 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 13:02:31 -M5 started Tue May 15 17:00:07 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 22:08:21 +M5 started Tue Aug 14 22:08:25 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5500000 because target called exit() +Exiting @ tick 5514000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index b2e950872..85d4c9288 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=SparcITB +size=64 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt index 351d5ef89..4a899f629 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 459524 # Simulator instruction rate (inst/s) -host_mem_usage 197560 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1004580342 # Simulator tick rate (ticks/s) +host_inst_rate 343655 # Simulator instruction rate (inst/s) +host_mem_usage 180816 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 753768067 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 11001 # Number of instructions simulated +sim_insts 10976 # Number of instructions simulated sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24345000 # Number of ticks simulated +sim_ticks 24355000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency @@ -78,53 +78,53 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 100.391376 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 100.373888 # Cycle average of tags in use system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 11002 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 11012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24915.194346 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22915.194346 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 10719 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 10729 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 7051000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.025723 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.025699 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 6485000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.025723 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.025699 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 37.876325 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 37.911661 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11002 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 11012 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 24915.194346 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 22915.194346 # average overall mshr miss latency -system.cpu.icache.demand_hits 10719 # number of demand (read+write) hits +system.cpu.icache.demand_hits 10729 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 7051000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.025723 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.025699 # miss rate for demand accesses system.cpu.icache.demand_misses 283 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 6485000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.025723 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.025699 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 11002 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 11012 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24915.194346 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22915.194346 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 10719 # number of overall hits +system.cpu.icache.overall_hits 10729 # number of overall hits system.cpu.icache.overall_miss_latency 7051000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.025723 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.025699 # miss rate for overall accesses system.cpu.icache.overall_misses 283 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 6485000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.025723 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.025699 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -140,8 +140,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 156.007276 # Cycle average of tags in use -system.cpu.icache.total_refs 10719 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 155.977710 # Cycle average of tags in use +system.cpu.icache.total_refs 10729 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,14 +221,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 318 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 178.142170 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.108320 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 24345000 # number of cpu cycles simulated -system.cpu.num_insts 11001 # Number of instructions executed -system.cpu.num_refs 2760 # Number of memory references +system.cpu.numCycles 24355000 # number of cpu cycles simulated +system.cpu.num_insts 10976 # Number of instructions executed +system.cpu.num_refs 2770 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout index e268ba0c6..838fa7706 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 00:08:15 -M5 started Tue Aug 14 00:08:29 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 22:08:21 +M5 started Tue Aug 14 22:08:25 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 24345000 because target called exit() +Exiting @ tick 24355000 because target called exit() |