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authorLisa Hsu <Lisa.Hsu@amd.com>2010-02-25 10:08:41 -0800
committerLisa Hsu <Lisa.Hsu@amd.com>2010-02-25 10:08:41 -0800
commitee20a7c0bddf1f2a1913ddb176910bdce4c13b9c (patch)
tree93b9bd8be890468c550b85eae4b467285b4d6811 /tests/quick/02.insttest/ref
parent7f3cd9a9fd636c1e48dcec20de3f6c14214d0ce4 (diff)
downloadgem5-ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c.tar.xz
stats: update stats for the changes I pushed re: shared cache occupancy
Diffstat (limited to 'tests/quick/02.insttest/ref')
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini8
-rwxr-xr-xtests/quick/02.insttest/ref/sparc/linux/o3-timing/simout8
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt14
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini2
-rwxr-xr-xtests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout8
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt8
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini8
-rwxr-xr-xtests/quick/02.insttest/ref/sparc/linux/simple-timing/simout8
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt14
9 files changed, 45 insertions, 33 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
index e7d27f8d6..0cc32d77e 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -109,7 +109,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -281,7 +281,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -316,7 +316,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -358,7 +358,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
index 6d075503d..a6f645c41 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 6 2009 11:07:18
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:24
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:00
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 4b0bc6800..d92dfc078 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1945 # Simulator instruction rate (inst/s)
-host_mem_usage 190344 # Number of bytes of host memory used
-host_seconds 7.43 # Real time elapsed on the host
-host_tick_rate 3735278 # Simulator tick rate (ticks/s)
+host_inst_rate 72869 # Simulator instruction rate (inst/s)
+host_mem_usage 190800 # Number of bytes of host memory used
+host_seconds 0.20 # Real time elapsed on the host
+host_tick_rate 139786869 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 14449 # Number of instructions simulated
sim_seconds 0.000028 # Number of seconds simulated
@@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses 167 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.026530 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 108.665251 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency
@@ -182,6 +184,8 @@ system.cpu.icache.demand_mshr_misses 359 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.110760 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 226.836007 # Average occupied blocks per context
system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
@@ -354,6 +358,8 @@ system.cpu.l2cache.demand_mshr_misses 503 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.007680 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 251.642612 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index 75d383c46..0d783c1db 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
index 3b6aca04c..a758d34e6 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 21 2009 18:04:32
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:05:08
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:01
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index bb032e871..970d208fc 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 587404 # Simulator instruction rate (inst/s)
-host_mem_usage 193520 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
-host_tick_rate 292299724 # Simulator tick rate (ticks/s)
+host_inst_rate 1098364 # Simulator instruction rate (inst/s)
+host_mem_usage 182400 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 540894569 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 15175 # Number of instructions simulated
sim_seconds 0.000008 # Number of seconds simulated
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
index ab1742f70..777caa173 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
@@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
index 76cbb3c5f..2c0f40a56 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:32:53
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:01
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 5c475dff1..07c8914c3 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 286976 # Simulator instruction rate (inst/s)
-host_mem_usage 202788 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
-host_tick_rate 804151064 # Simulator tick rate (ticks/s)
+host_inst_rate 227392 # Simulator instruction rate (inst/s)
+host_mem_usage 190044 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
+host_tick_rate 637540839 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 15175 # Number of instructions simulated
sim_seconds 0.000043 # Number of seconds simulated
@@ -52,6 +52,8 @@ system.cpu.dcache.demand_mshr_misses 155 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.023864 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 97.747327 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@@ -105,6 +107,8 @@ system.cpu.icache.demand_mshr_misses 280 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.074743 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 153.073222 # Average occupied blocks per context
system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency
@@ -177,6 +181,8 @@ system.cpu.l2cache.demand_mshr_misses 416 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.005323 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 174.433606 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency