merge

--HG--
extra : convert_revision : 5866eaa4008c4fa5da7fbb443132b8326955f71d

5 files changed, 129 insertions, 24 deletions

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index d3a9862e8..1f7fcb065 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -5,7 +5,7 @@ dummy=0
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
+children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 console=/dist/m5/system/binaries/console
@@ -22,8 +22,8 @@ system_type=34
 [system.bridge]
 type=Bridge
 delay=50000
-fix_partial_write_a=false
-fix_partial_write_b=true
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:8589934591
 nack_delay=4000
 req_size_a=16
 req_size_b=16
@@ -65,10 +65,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -103,10 +105,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -171,10 +175,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -209,10 +215,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -295,17 +303,55 @@ clock=1000
 responder_set=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+cpu_side_filter_ranges=549755813888:18446744073709551615
+hash_delay=1
+latency=50000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=0:18446744073709551615
+mshrs=20
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[2]
 
 [system.l2c]
 type=BaseCache
 addr_range=0:18446744073709551615
 assoc=8
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=10000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=92
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -329,7 +375,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[2]
+mem_side=system.membus.port[3]
 
 [system.membus]
 type=Bus
@@ -340,7 +386,7 @@ clock=1000
 responder_set=false
 width=64
 default=system.membus.responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
+port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.responder]
 type=IsaFake
@@ -474,8 +520,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[28]
-dma=system.iobus.port[29]
+config=system.iobus.port[29]
+dma=system.iobus.port[30]
 pio=system.iobus.port[27]
 
 [system.tsunami.ethernet.configdata]
@@ -840,8 +886,8 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
+config=system.iobus.port[31]
+dma=system.iobus.port[32]
 pio=system.iobus.port[26]
 
 [system.tsunami.ide.configdata]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
index 27adebb82..c2aeea3f1 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
@@ -38,7 +38,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
 
Mount-cache hash table entries: 512
 
SMP starting up secondaries.
-
Slave CPU 1 console command START
+
Slave CPU 1 console command START

 SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
 
Brought up 2 CPUs
 
SMP: Total of 2 processors activated (8000.15 BogoMIPS).
@@ -77,7 +77,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
hdb: M5 IDE Disk, ATA DISK drive
 
ide0 at 0x8410-0x8417,0x8422 on irq 31
 
hda: max request size: 128KiB
-
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
+
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
 
hda: cache flushes not supported
 
 hda: hda1
 
hdb: max request size: 128KiB
@@ -104,6 +104,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
All bugs added by David S. Miller <davem@redhat.com>
 
VFS: Mounted root (ext2 filesystem) readonly.
 
Freeing unused kernel memory: 224k freed
-

init started:  BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
-mounting filesystems...
-loading script...
+

init started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary

+mounting filesystems...

+EXT2-fs warning: checktime reached, running e2fsck is recommended
+
loading script...

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
index df780ee45..d9ba4afe5 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1258571                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 256444                       # Number of bytes of host memory used
-host_seconds                                    50.16                       # Real time elapsed on the host
-host_tick_rate                            37289409683                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2271343                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 326380                       # Number of bytes of host memory used
+host_seconds                                    27.79                       # Real time elapsed on the host
+host_tick_rate                            67296173797                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    63125943                       # Number of instructions simulated
 sim_seconds                                  1.870335                       # Number of seconds simulated
@@ -471,6 +471,64 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.iocache.ReadReq_accesses                   175                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses                     175                       # number of ReadReq misses
+system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
+system.iocache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs                     0                       # number of cycles access was blocked
+system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs              0                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.demand_accesses                  41727                       # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency              0                       # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
+system.iocache.demand_hits                          0                       # number of demand (read+write) hits
+system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
+system.iocache.demand_misses                    41727                       # number of demand (read+write) misses
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate                0                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_accesses                 41727                       # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency             0                       # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.iocache.overall_hits                         0                       # number of overall hits
+system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
+system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
+system.iocache.overall_misses                   41727                       # number of overall misses
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate               0                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements                     41695                       # number of replacements
+system.iocache.sampled_refs                     41711                       # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse                     0.435433                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.warmup_cycle              1685787165017                       # Cycle when the warmup percentage was hit.
+system.iocache.writebacks                       41520                       # number of writebacks
 system.l2c.ReadExReq_accesses                  306246                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_misses                    306246                       # number of ReadExReq misses
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
index 563ca3160..85bd66f32 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
@@ -1,5 +1,5 @@
-Listening for system connection on port 3457
+Listening for system connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
 0: system.remote_gdb.listener: listening for remote gdb on port 7001
-0: system.remote_gdb.listener: listening for remote gdb on port 7002
 warn: Entering event queue @ 0.  Starting simulation...
 warn: 97861500: Trying to launch CPU number 1!
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
index 1298154d9..b97e23c2a 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  3 2007 04:02:11
-M5 started Fri Aug  3 04:22:43 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 10 2007 16:03:34
+M5 started Fri Aug 10 16:04:07 2007
+M5 executing on zeep
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 1870335101500 because m5_exit instruction encountered