diff options
author | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
---|---|---|
committer | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
commit | 374ba9bae359e68c1496f8db25c38a817af2da19 (patch) | |
tree | 48fe4ae90f77f19aa6005fa5ec2426e836299bc9 /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual | |
parent | e0de2c34433be76eac7798e58e1ae02f5bffb732 (diff) | |
download | gem5-374ba9bae359e68c1496f8db25c38a817af2da19.tar.xz |
tests: update tests for TLB unification
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual')
3 files changed, 61 insertions, 29 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 56dec3815..ef33d965f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -97,7 +97,7 @@ cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.port[2] [system.cpu0.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu0.icache] @@ -136,7 +136,7 @@ mem_side=system.toL2Bus.port[1] type=AlphaInterrupts [system.cpu0.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu0.tracer] @@ -206,7 +206,7 @@ cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.port[4] [system.cpu1.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu1.icache] @@ -245,7 +245,7 @@ mem_side=system.toL2Bus.port[3] type=AlphaInterrupts [system.cpu1.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu1.tracer] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 8c40366bc..a95a79ffc 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:15:24 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:15:50 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +M5 compiled Apr 8 2009 12:30:02 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:30:04 +M5 executing on maize +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 8ed468432..a781e9d48 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2804596 # Simulator instruction rate (inst/s) -host_mem_usage 292704 # Number of bytes of host memory used -host_seconds 22.52 # Real time elapsed on the host -host_tick_rate 83058483755 # Simulator tick rate (ticks/s) +host_inst_rate 4473904 # Simulator instruction rate (inst/s) +host_mem_usage 294520 # Number of bytes of host memory used +host_seconds 14.12 # Real time elapsed on the host +host_tick_rate 132494065933 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated @@ -67,10 +67,14 @@ system.cpu0.dcache.tagsinuse 504.827058 # Cy system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 396793 # number of writebacks -system.cpu0.dtb.accesses 698037 # DTB accesses -system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15091429 # DTB hits -system.cpu0.dtb.misses 7805 # DTB misses +system.cpu0.dtb.data_accesses 698037 # DTB accesses +system.cpu0.dtb.data_acv 251 # DTB access violations +system.cpu0.dtb.data_hits 15091429 # DTB hits +system.cpu0.dtb.data_misses 7805 # DTB misses +system.cpu0.dtb.fetch_accesses 0 # ITB accesses +system.cpu0.dtb.fetch_acv 0 # ITB acv +system.cpu0.dtb.fetch_hits 0 # ITB hits +system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.read_accesses 508987 # DTB read accesses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_hits 9154530 # DTB read hits @@ -127,10 +131,22 @@ system.cpu0.icache.total_refs 56345132 # To system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles -system.cpu0.itb.accesses 3859041 # ITB accesses -system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3855556 # ITB hits -system.cpu0.itb.misses 3485 # ITB misses +system.cpu0.itb.data_accesses 0 # DTB accesses +system.cpu0.itb.data_acv 0 # DTB access violations +system.cpu0.itb.data_hits 0 # DTB hits +system.cpu0.itb.data_misses 0 # DTB misses +system.cpu0.itb.fetch_accesses 3859041 # ITB accesses +system.cpu0.itb.fetch_acv 127 # ITB acv +system.cpu0.itb.fetch_hits 3855556 # ITB hits +system.cpu0.itb.fetch_misses 3485 # ITB misses +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.read_acv 0 # DTB read access violations +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.write_acv 0 # DTB write access violations +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal 183291 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed @@ -283,10 +299,14 @@ system.cpu1.dcache.tagsinuse 391.951263 # Cy system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 30848 # number of writebacks -system.cpu1.dtb.accesses 323622 # DTB accesses -system.cpu1.dtb.acv 116 # DTB access violations -system.cpu1.dtb.hits 1914885 # DTB hits -system.cpu1.dtb.misses 3692 # DTB misses +system.cpu1.dtb.data_accesses 323622 # DTB accesses +system.cpu1.dtb.data_acv 116 # DTB access violations +system.cpu1.dtb.data_hits 1914885 # DTB hits +system.cpu1.dtb.data_misses 3692 # DTB misses +system.cpu1.dtb.fetch_accesses 0 # ITB accesses +system.cpu1.dtb.fetch_acv 0 # ITB acv +system.cpu1.dtb.fetch_hits 0 # ITB hits +system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.read_accesses 220342 # DTB read accesses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_hits 1163439 # DTB read hits @@ -343,10 +363,22 @@ system.cpu1.icache.total_refs 5832136 # To system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles -system.cpu1.itb.accesses 1469938 # ITB accesses -system.cpu1.itb.acv 57 # ITB acv -system.cpu1.itb.hits 1468399 # ITB hits -system.cpu1.itb.misses 1539 # ITB misses +system.cpu1.itb.data_accesses 0 # DTB accesses +system.cpu1.itb.data_acv 0 # DTB access violations +system.cpu1.itb.data_hits 0 # DTB hits +system.cpu1.itb.data_misses 0 # DTB misses +system.cpu1.itb.fetch_accesses 1469938 # ITB accesses +system.cpu1.itb.fetch_acv 57 # ITB acv +system.cpu1.itb.fetch_hits 1468399 # ITB hits +system.cpu1.itb.fetch_misses 1539 # ITB misses +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.read_acv 0 # DTB read access violations +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.write_acv 0 # DTB write access violations +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal 32131 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed |