stats: update stats for SC protocol change

Some subset of UpgradeReq messages shifted to the
new SCUpgradeReq type.  Other than that there
are no significant differences.

4 files changed, 32 insertions, 23 deletions

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index e7e943434..decabad7f 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -8,11 +8,11 @@ type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
 init_param=0
-kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
 mem_mode=atomic
-pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -264,7 +264,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -284,7 +284,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -410,7 +410,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
index 5a1d0bef0..83c71fc5c 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
@@ -2,6 +2,4 @@ warn: Sockets disabled, not accepting terminal connections
 For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: 97861500: Trying to launch CPU number 1!
-For more information see: http://www.m5sim.org/warn/8f7d2563
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 643403e5a..74b825924 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
+Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,12 +7,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2010 23:13:04
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 24 2010 23:13:12
-M5 executing on SC2B0619
+M5 compiled Jun 16 2010 10:39:13
+M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats
+M5 started Jun 16 2010 10:44:34
+M5 executing on phenom
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
+info: Launching CPU 1 @ 97861500
 Exiting @ tick 1870335522500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 591b54757..7f610a74e 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2090501                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 278608                       # Number of bytes of host memory used
-host_seconds                                    30.21                       # Real time elapsed on the host
-host_tick_rate                            61910551280                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3116744                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 276812                       # Number of bytes of host memory used
+host_seconds                                    20.26                       # Real time elapsed on the host
+host_tick_rate                            92302855126                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_seconds                                  1.870336                       # Number of seconds simulated
@@ -699,14 +699,22 @@ system.l2c.ReadReq_miss_rate::1              0.040193                       # mi
 system.l2c.ReadReq_misses::0                   958815                       # number of ReadReq misses
 system.l2c.ReadReq_misses::1                     5721                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total               964536                       # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0              117429                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                7578                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          125007                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0             26914                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1              2297                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         29211                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_miss_rate::0                1                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1                1                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_misses::0               26914                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1                2297                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total           29211                       # number of SCUpgradeReq misses
+system.l2c.UpgradeReq_accesses::0               90515                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                5281                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           95796                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_miss_rate::0                  1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                117429                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                  7578                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total            125007                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::0                 90515                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                  5281                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             95796                       # number of UpgradeReq misses
 system.l2c.Writeback_accesses::0               427641                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           427641                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_hits::0                   427641                       # number of Writeback hits