Update stats for new writeback behavior.

--HG--
extra : convert_revision : 3e932b5773f5fb9a119822d5bf497f61e9409c14

1 files changed, 49 insertions, 50 deletions

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
index 0780c3207..082e17724 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
@@ -1,21 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2454439                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 324968                       # Number of bytes of host memory used
-host_seconds                                    24.44                       # Real time elapsed on the host
-host_tick_rate                            74797977378                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1474278                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 260680                       # Number of bytes of host memory used
+host_seconds                                    40.70                       # Real time elapsed on the host
+host_tick_rate                            44928072322                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    59995479                       # Number of instructions simulated
 sim_seconds                                  1.828355                       # Number of seconds simulated
-sim_ticks                                1828355476000                       # Number of ticks simulated
+sim_ticks                                1828355496000                       # Number of ticks simulated
 system.cpu.dcache.LoadLockedReq_accesses       200279                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_hits           183119                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_miss_rate     0.085680                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_misses          17160                       # number of LoadLockedReq misses
 system.cpu.dcache.ReadReq_accesses            9523054                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits                7801377                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits                7801378                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_miss_rate          0.180790                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1721677                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses              1721676                       # number of ReadReq misses
 system.cpu.dcache.StoreCondReq_accesses        199258                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_hits            169392                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_miss_rate     0.149886                       # miss rate for StoreCondReq accesses
@@ -26,7 +26,7 @@ system.cpu.dcache.WriteReq_miss_rate         0.064944                       # mi
 system.cpu.dcache.WriteReq_misses              399417                       # number of WriteReq misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                   6.866558                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                   6.866562                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
@@ -35,10 +35,10 @@ system.cpu.dcache.cache_copies                      0                       # nu
 system.cpu.dcache.demand_accesses            15673243                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_avg_miss_latency            0                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                13552149                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits                13552150                       # number of demand (read+write) hits
 system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.135332                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2121094                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses               2121093                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate             0                       # mshr miss rate for demand accesses
@@ -50,10 +50,10 @@ system.cpu.dcache.overall_accesses           15673243                       # nu
 system.cpu.dcache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               13552149                       # number of overall hits
+system.cpu.dcache.overall_hits               13552150                       # number of overall hits
 system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.135332                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2121094                       # number of overall misses
+system.cpu.dcache.overall_misses              2121093                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
@@ -69,11 +69,11 @@ system.cpu.dcache.prefetcher.num_hwpf_issued            0
 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements                2042666                       # number of replacements
-system.cpu.dcache.sampled_refs                2043178                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                2042665                       # number of replacements
+system.cpu.dcache.sampled_refs                2043177                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.tagsinuse                511.997801                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14029601                       # Total number of references to valid blocks.
+system.cpu.dcache.total_refs                 14029602                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   428885                       # number of writebacks
 system.cpu.dtb.accesses                       1020787                       # DTB accesses
@@ -89,12 +89,12 @@ system.cpu.dtb.write_acv                          157                       # DT
 system.cpu.dtb.write_hits                     6349968                       # DTB write hits
 system.cpu.dtb.write_misses                      1142                       # DTB write misses
 system.cpu.icache.ReadReq_accesses           60007317                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits               59087260                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits               59087262                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_rate          0.015332                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses               920057                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses               920055                       # number of ReadReq misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  64.229332                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  64.229474                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
@@ -103,10 +103,10 @@ system.cpu.icache.cache_copies                      0                       # nu
 system.cpu.icache.demand_accesses            60007317                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency            0                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                59087260                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits                59087262                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.015332                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                920057                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses                920055                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate             0                       # mshr miss rate for demand accesses
@@ -118,10 +118,10 @@ system.cpu.icache.overall_accesses           60007317                       # nu
 system.cpu.icache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               59087260                       # number of overall hits
+system.cpu.icache.overall_hits               59087262                       # number of overall hits
 system.cpu.icache.overall_miss_latency              0                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.015332                       # miss rate for overall accesses
-system.cpu.icache.overall_misses               920057                       # number of overall misses
+system.cpu.icache.overall_misses               920055                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
@@ -137,11 +137,11 @@ system.cpu.icache.prefetcher.num_hwpf_issued            0
 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements                 919430                       # number of replacements
-system.cpu.icache.sampled_refs                 919942                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                 919428                       # number of replacements
+system.cpu.icache.sampled_refs                 919940                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.tagsinuse                511.214820                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 59087260                       # Total number of references to valid blocks.
+system.cpu.icache.total_refs                 59087262                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle             9686972500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                     0.983588                       # Percentage of idle cycles
@@ -179,8 +179,8 @@ system.cpu.kern.ipl_good_0                      73448     49.29%     49.29% # nu
 system.cpu.kern.ipl_good_21                       243      0.16%     49.46% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good_22                      1865      1.25%     50.71% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good_31                     73448     49.29%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks                1828355268500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0              1811087537500     99.06%     99.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks                1828355288500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0              1811087557500     99.06%     99.06% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks_21                 20110000      0.00%     99.06% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks_22                 80195000      0.00%     99.06% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks_31              17167426000      0.94%    100.00% # number of cycles we spent at this ipl
@@ -200,7 +200,7 @@ system.cpu.kern.mode_switch_good_user               1                       # fr
 system.cpu.kern.mode_switch_good_idle        0.081545                       # fraction of useful protection mode switches
 system.cpu.kern.mode_ticks_kernel         26834026500      1.47%      1.47% # number of ticks spent at the given mode
 system.cpu.kern.mode_ticks_user            1465069000      0.08%      1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle          1800056172000     98.45%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle          1800056192000     98.45%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 system.cpu.kern.syscall                           326                       # number of syscalls executed
 system.cpu.kern.syscall_2                           8      2.45%      2.45% # number of syscalls executed
@@ -234,7 +234,7 @@ system.cpu.kern.syscall_132                         4      1.23%     98.77% # nu
 system.cpu.kern.syscall_144                         2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall_147                         2      0.61%    100.00% # number of syscalls executed
 system.cpu.not_idle_fraction                 0.016412                       # Percentage of non-idle cycles
-system.cpu.numCycles                       3656710843                       # number of cpu cycles simulated
+system.cpu.numCycles                       3656710883                       # number of cpu cycles simulated
 system.cpu.num_insts                         59995479                       # Number of instructions executed
 system.cpu.num_refs                          16302129                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -310,31 +310,30 @@ system.iocache.writebacks                       41512                       # nu
 system.l2c.ReadExReq_accesses                  304342                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_misses                    304342                       # number of ReadExReq misses
-system.l2c.ReadReq_accesses                   2658877                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits                       1558398                       # number of ReadReq hits
-system.l2c.ReadReq_miss_rate                 0.413889                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses                     1100479                       # number of ReadReq misses
+system.l2c.ReadReq_accesses                   2658874                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits                       1696454                       # number of ReadReq hits
+system.l2c.ReadReq_miss_rate                 0.361965                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses                      962420                       # number of ReadReq misses
 system.l2c.UpgradeReq_accesses                 124941                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_misses                   124941                       # number of UpgradeReq misses
 system.l2c.Writeback_accesses                  428885                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_miss_rate                      1                       # miss rate for Writeback accesses
-system.l2c.Writeback_misses                    428885                       # number of Writeback misses
+system.l2c.Writeback_hits                      428885                       # number of Writeback hits
 system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          1.644070                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          1.726821                       # Average number of references to valid blocks.
 system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
 system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses                    2963219                       # number of demand (read+write) accesses
+system.l2c.demand_accesses                    2963216                       # number of demand (read+write) accesses
 system.l2c.demand_avg_miss_latency                  0                       # average overall miss latency
 system.l2c.demand_avg_mshr_miss_latency  <err: div-0>                       # average overall mshr miss latency
-system.l2c.demand_hits                        1558398                       # number of demand (read+write) hits
+system.l2c.demand_hits                        1696454                       # number of demand (read+write) hits
 system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate                  0.474086                       # miss rate for demand accesses
-system.l2c.demand_misses                      1404821                       # number of demand (read+write) misses
+system.l2c.demand_miss_rate                  0.427496                       # miss rate for demand accesses
+system.l2c.demand_misses                      1266762                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_rate                    0                       # mshr miss rate for demand accesses
@@ -342,14 +341,14 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.overall_accesses                   2963219                       # number of overall (read+write) accesses
+system.l2c.overall_accesses                   2963216                       # number of overall (read+write) accesses
 system.l2c.overall_avg_miss_latency                 0                       # average overall miss latency
 system.l2c.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.l2c.overall_hits                       1558398                       # number of overall hits
+system.l2c.overall_hits                       1696454                       # number of overall hits
 system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.overall_miss_rate                 0.474086                       # miss rate for overall accesses
-system.l2c.overall_misses                     1404821                       # number of overall misses
+system.l2c.overall_miss_rate                 0.427496                       # miss rate for overall accesses
+system.l2c.overall_misses                     1266762                       # number of overall misses
 system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
 system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_rate                   0                       # mshr miss rate for overall accesses
@@ -365,13 +364,13 @@ system.l2c.prefetcher.num_hwpf_issued               0                       # nu
 system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements                        947436                       # number of replacements
-system.l2c.sampled_refs                        965232                       # Sample count of references to valid blocks.
+system.l2c.replacements                       1050727                       # number of replacements
+system.l2c.sampled_refs                       1081066                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     15309.548937                       # Cycle average of tags in use
-system.l2c.total_refs                         1586909                       # Total number of references to valid blocks.
-system.l2c.warmup_cycle                     789998500                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                               0                       # number of writebacks
+system.l2c.tagsinuse                     30223.986648                       # Cycle average of tags in use
+system.l2c.total_refs                         1866807                       # Total number of references to valid blocks.
+system.l2c.warmup_cycle                     765422500                       # Cycle when the warmup percentage was hit.
+system.l2c.writebacks                          119145                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post