update stats for fixed nextCycle()

--HG--
extra : convert_revision : 3626c4d2d67ed190d846f6edae06c43444a14feb

1 files changed, 26 insertions, 26 deletions

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
index a2ea188c7..722437701 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
@@ -1,23 +1,23 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 109117                       # Simulator instruction rate (inst/s)
-host_seconds                                   549.94                       # Real time elapsed on the host
-host_tick_rate                             3324672454                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1403977                       # Simulator instruction rate (inst/s)
+host_seconds                                    42.74                       # Real time elapsed on the host
+host_tick_rate                            42777462102                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    60007317                       # Number of instructions simulated
 sim_seconds                                  1.828355                       # Number of seconds simulated
-sim_ticks                                1828355481500                       # Number of ticks simulated
+sim_ticks                                1828355486000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses            9723333                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits                7984499                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits                7984498                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_miss_rate          0.178831                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1738834                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses              1738835                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_accesses           6349447                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_hits               6045093                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_rate         0.047934                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses              304354                       # number of WriteReq misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                   6.866570                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                   6.866566                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
@@ -26,10 +26,10 @@ system.cpu.dcache.cache_copies                      0                       # nu
 system.cpu.dcache.demand_accesses            16072780                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_avg_miss_latency            0                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                14029592                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits                14029591                       # number of demand (read+write) hits
 system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.127121                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2043188                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses               2043189                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate             0                       # mshr miss rate for demand accesses
@@ -41,10 +41,10 @@ system.cpu.dcache.overall_accesses           16072780                       # nu
 system.cpu.dcache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               14029592                       # number of overall hits
+system.cpu.dcache.overall_hits               14029591                       # number of overall hits
 system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.127121                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2043188                       # number of overall misses
+system.cpu.dcache.overall_misses              2043189                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
@@ -61,7 +61,7 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.protocol.hwpf_invalid             0                       # hard prefetch misses to invalid blocks
-system.cpu.dcache.protocol.read_invalid       1738834                       # read misses to invalid blocks
+system.cpu.dcache.protocol.read_invalid       1738835                       # read misses to invalid blocks
 system.cpu.dcache.protocol.snoop_inv_exclusive            0                       # Invalidate snoops on exclusive blocks
 system.cpu.dcache.protocol.snoop_inv_invalid            0                       # Invalidate snoops on invalid blocks
 system.cpu.dcache.protocol.snoop_inv_modified            1                       # Invalidate snoops on modified blocks
@@ -86,11 +86,11 @@ system.cpu.dcache.protocol.swpf_invalid             0                       # so
 system.cpu.dcache.protocol.write_invalid       304342                       # write misses to invalid blocks
 system.cpu.dcache.protocol.write_owned              8                       # write misses to owned blocks
 system.cpu.dcache.protocol.write_shared             4                       # write misses to shared blocks
-system.cpu.dcache.replacements                2042663                       # number of replacements
-system.cpu.dcache.sampled_refs                2043175                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                2042664                       # number of replacements
+system.cpu.dcache.sampled_refs                2043176                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.tagsinuse                511.997801                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14029604                       # Total number of references to valid blocks.
+system.cpu.dcache.total_refs                 14029603                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
 system.cpu.dtb.accesses                       1020787                       # DTB accesses
@@ -222,8 +222,8 @@ system.cpu.kern.ipl_good_0                      73448     49.29%     49.29% # nu
 system.cpu.kern.ipl_good_21                       243      0.16%     49.46% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good_22                      1865      1.25%     50.71% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good_31                     73448     49.29%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks                1828355274000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0              1811087543000     99.06%     99.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks                1828355278500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0              1811087547500     99.06%     99.06% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks_21                 20110000      0.00%     99.06% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks_22                 80195000      0.00%     99.06% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks_31              17167426000      0.94%    100.00% # number of cycles we spent at this ipl
@@ -243,7 +243,7 @@ system.cpu.kern.mode_switch_good_user               1                       # fr
 system.cpu.kern.mode_switch_good_idle        0.081545                       # fraction of useful protection mode switches
 system.cpu.kern.mode_ticks_kernel         26834026500      1.47%      1.47% # number of ticks spent at the given mode
 system.cpu.kern.mode_ticks_user            1465069000      0.08%      1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle          1800056177500     98.45%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle          1800056182000     98.45%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 system.cpu.kern.syscall                           326                       # number of syscalls executed
 system.cpu.kern.syscall_2                           8      2.45%      2.45% # number of syscalls executed
@@ -296,24 +296,24 @@ system.l2c.ReadExReq_accesses                  304342                       # nu
 system.l2c.ReadExReq_hits                      187346                       # number of ReadExReq hits
 system.l2c.ReadExReq_miss_rate               0.384423                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_misses                    116996                       # number of ReadExReq misses
-system.l2c.ReadReq_accesses                   2658871                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits                       1717827                       # number of ReadReq hits
+system.l2c.ReadReq_accesses                   2658872                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits                       1717828                       # number of ReadReq hits
 system.l2c.ReadReq_miss_rate                 0.353926                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_misses                      941044                       # number of ReadReq misses
 system.l2c.Writeback_accesses                  428885                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_hits                      428885                       # number of Writeback hits
 system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          2.205900                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          2.205901                       # Average number of references to valid blocks.
 system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
 system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses                    2658871                       # number of demand (read+write) accesses
+system.l2c.demand_accesses                    2658872                       # number of demand (read+write) accesses
 system.l2c.demand_avg_miss_latency                  0                       # average overall miss latency
 system.l2c.demand_avg_mshr_miss_latency  <err: div-0>                       # average overall mshr miss latency
-system.l2c.demand_hits                        1717827                       # number of demand (read+write) hits
+system.l2c.demand_hits                        1717828                       # number of demand (read+write) hits
 system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_rate                  0.353926                       # miss rate for demand accesses
 system.l2c.demand_misses                       941044                       # number of demand (read+write) misses
@@ -324,11 +324,11 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.overall_accesses                   3087756                       # number of overall (read+write) accesses
+system.l2c.overall_accesses                   3087757                       # number of overall (read+write) accesses
 system.l2c.overall_avg_miss_latency                 0                       # average overall miss latency
 system.l2c.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.l2c.overall_hits                       2146712                       # number of overall hits
+system.l2c.overall_hits                       2146713                       # number of overall hits
 system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
 system.l2c.overall_miss_rate                 0.304766                       # miss rate for overall accesses
 system.l2c.overall_misses                      941044                       # number of overall misses
@@ -351,7 +351,7 @@ system.l2c.replacements                        992432                       # nu
 system.l2c.sampled_refs                       1057820                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
 system.l2c.tagsinuse                     65517.661064                       # Cycle average of tags in use
-system.l2c.total_refs                         2333445                       # Total number of references to valid blocks.
+system.l2c.total_refs                         2333446                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                     614754000                       # Cycle when the warmup percentage was hit.
 system.l2c.writebacks                               0                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post