Update stats for new single bad-address responder.

Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.

3 files changed, 17 insertions, 39 deletions

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 511baadf2..d098a0440 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -69,11 +69,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=1000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=4
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -105,11 +104,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=1000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=4
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -199,14 +197,13 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst
 
 [system.iocache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_range=0:8589934591
 assoc=8
 block_size=64
-cpu_side_filter_ranges=549755813888:18446744073709551615
+forward_snoops=false
 hash_delay=1
 latency=50000
 max_miss_count=0
-mem_side_filter_ranges=0:18446744073709551615
 mshrs=20
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -234,11 +231,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=8
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=10000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=92
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -263,20 +259,20 @@ mem_side=system.membus.port[3]
 
 [system.membus]
 type=Bus
-children=responder
+children=badaddr_responder
 block_size=64
 bus_id=1
 clock=1000
 header_cycles=1
 responder_set=false
 width=64
-default=system.membus.responder.pio
+default=system.membus.badaddr_responder.pio
 port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
 
-[system.membus.responder]
+[system.membus.badaddr_responder]
 type=IsaFake
 pio_addr=0
-pio_latency=1
+pio_latency=1000
 pio_size=8
 platform=system.tsunami
 ret_bad_addr=true
@@ -319,32 +315,14 @@ port=3456
 
 [system.toL2Bus]
 type=Bus
-children=responder
 block_size=64
 bus_id=0
 clock=1000
 header_cycles=1
 responder_set=false
 width=64
-default=system.toL2Bus.responder.pio
 port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
-[system.toL2Bus.responder]
-type=IsaFake
-pio_addr=0
-pio_latency=1
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.toL2Bus.default
-
 [system.tsunami]
 type=Tsunami
 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index b5820599c..6085e3c17 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr  8 2009 12:30:02
-M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
-M5 started Apr  8 2009 12:30:05
-M5 executing on maize
+M5 compiled Apr 21 2009 17:45:48
+M5 revision e6dd09514462 6117 default qtip tip stats-update
+M5 started Apr 21 2009 17:54:37
+M5 executing on zizzer
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 9c2b9013b..2f7905f66 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                4520875                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 293196                       # Number of bytes of host memory used
-host_seconds                                    13.28                       # Real time elapsed on the host
-host_tick_rate                           137745560508                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2944628                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 292076                       # Number of bytes of host memory used
+host_seconds                                    20.39                       # Real time elapsed on the host
+host_tick_rate                            89719993414                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_seconds                                  1.829332                       # Number of seconds simulated