diff options
| author | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
| commit | 9e45ada1718b6df9310757fdc7cd78db4695516f (patch) | |
| tree | c5cc9f2173f36e38addd8ca08e32ac010e56ef73 /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic | |
| parent | 12497284949cb5418e6bc403723c034aee655666 (diff) | |
| download | gem5-9e45ada1718b6df9310757fdc7cd78db4695516f.tar.xz | |
stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic')
3 files changed, 83 insertions, 79 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index c4ecb27ec..95ba28054 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -8,11 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=atomic -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -157,7 +158,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -177,7 +178,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -303,7 +304,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index af78d2d19..88c4f9cc3 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr +Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 16 2010 10:39:13 -M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats -M5 started Jun 16 2010 10:39:16 -M5 executing on phenom -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +M5 compiled Aug 26 2010 12:51:14 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:51:50 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 7a54ae203..da0ed6f79 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3274924 # Simulator instruction rate (inst/s) -host_mem_usage 275440 # Number of bytes of host memory used -host_seconds 18.33 # Real time elapsed on the host -host_tick_rate 99783911231 # Simulator tick rate (ticks/s) +host_inst_rate 2897706 # Simulator instruction rate (inst/s) +host_mem_usage 291728 # Number of bytes of host memory used +host_seconds 20.72 # Real time elapsed on the host +host_tick_rate 88290469218 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated @@ -24,18 +24,18 @@ system.cpu.dcache.ReadReq_misses::0 1721705 # nu system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 169415 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 169415 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_rate::0 0.149873 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 29867 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 29867 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_hits::0 177079 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 177079 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate::0 0.111415 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 22203 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 22203 # number of StoreCondReq misses system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits::0 5753150 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5753150 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate::0 0.064920 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 399424 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 399424 # number of WriteReq misses +system.cpu.dcache.WriteReq_hits::0 5781102 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5781102 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.060377 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 371472 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 371472 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. @@ -51,16 +51,16 @@ system.cpu.dcache.demand_avg_miss_latency::0 0 system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13560932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 13588884 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13560932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13588884 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.135258 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.133476 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 2121129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 2093177 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2121129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2093177 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -80,16 +80,16 @@ system.cpu.dcache.overall_avg_miss_latency::1 no_value system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13560932 # number of overall hits +system.cpu.dcache.overall_hits::0 13588884 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13560932 # number of overall hits +system.cpu.dcache.overall_hits::total 13588884 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.135258 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.133476 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 2121129 # number of overall misses +system.cpu.dcache.overall_misses::0 2093177 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2121129 # number of overall misses +system.cpu.dcache.overall_misses::total 2093177 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -104,7 +104,7 @@ system.cpu.dcache.soft_prefetch_mshr_full 0 # n system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 428893 # number of writebacks +system.cpu.dcache.writebacks 450979 # number of writebacks system.cpu.dtb.data_accesses 1020787 # DTB accesses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_hits 16062925 # DTB hits @@ -395,33 +395,35 @@ system.iocache.warmup_cycle 1685780659017 # C system.iocache.writebacks 41512 # number of writebacks system.l2c.ReadExReq_accesses::0 304346 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 304346 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 304346 # number of ReadExReq misses +system.l2c.ReadExReq_hits::0 1965 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1965 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.993544 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 302381 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 302381 # number of ReadExReq misses system.l2c.ReadReq_accesses::0 2659071 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2659071 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 1696652 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1696652 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.361938 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 962419 # number of ReadReq misses -system.l2c.ReadReq_misses::total 962419 # number of ReadReq misses -system.l2c.SCUpgradeReq_accesses::0 29867 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29867 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 1697753 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1697753 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.361524 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 961318 # number of ReadReq misses +system.l2c.ReadReq_misses::total 961318 # number of ReadReq misses +system.l2c.SCUpgradeReq_accesses::0 22203 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 22203 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 29867 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 29867 # number of SCUpgradeReq misses -system.l2c.UpgradeReq_accesses::0 95078 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 95078 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_misses::0 22203 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 22203 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_accesses::0 67126 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 67126 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 95078 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 95078 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 428893 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 428893 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 428893 # number of Writeback hits -system.l2c.Writeback_hits::total 428893 # number of Writeback hits +system.l2c.UpgradeReq_misses::0 67126 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 67126 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 450979 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 450979 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 450979 # number of Writeback hits +system.l2c.Writeback_hits::total 450979 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 1.727246 # Average number of references to valid blocks. +system.l2c.avg_refs 1.759381 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -434,16 +436,16 @@ system.l2c.demand_avg_miss_latency::0 0 # av system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 1696652 # number of demand (read+write) hits +system.l2c.demand_hits::0 1699718 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1696652 # number of demand (read+write) hits +system.l2c.demand_hits::total 1699718 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.427468 # miss rate for demand accesses +system.l2c.demand_miss_rate::0 0.426433 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 1266765 # number of demand (read+write) misses +system.l2c.demand_misses::0 1263699 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 1266765 # number of demand (read+write) misses +system.l2c.demand_misses::total 1263699 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -453,10 +455,10 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.077203 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.384049 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5059.576308 # Average occupied blocks per context -system.l2c.occ_blocks::1 25169.009297 # Average occupied blocks per context +system.l2c.occ_%::0 0.141683 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.342776 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 9285.312813 # Average occupied blocks per context +system.l2c.occ_blocks::1 22464.151503 # Average occupied blocks per context system.l2c.overall_accesses::0 2963417 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2963417 # number of overall (read+write) accesses @@ -465,16 +467,16 @@ system.l2c.overall_avg_miss_latency::1 no_value # av system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1696652 # number of overall hits +system.l2c.overall_hits::0 1699718 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1696652 # number of overall hits +system.l2c.overall_hits::total 1699718 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.427468 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.426433 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 1266765 # number of overall misses +system.l2c.overall_misses::0 1263699 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 1266765 # number of overall misses +system.l2c.overall_misses::total 1263699 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -483,13 +485,13 @@ system.l2c.overall_mshr_miss_rate::total no_value # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 1050724 # number of replacements -system.l2c.sampled_refs 1081067 # Sample count of references to valid blocks. +system.l2c.replacements 1048986 # number of replacements +system.l2c.sampled_refs 1079842 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30228.585605 # Cycle average of tags in use -system.l2c.total_refs 1867269 # Total number of references to valid blocks. +system.l2c.tagsinuse 31749.464316 # Cycle average of tags in use +system.l2c.total_refs 1899854 # Total number of references to valid blocks. system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119147 # number of writebacks +system.l2c.writebacks 118452 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post |