diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-15 19:25:35 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-15 19:25:35 -0400 |
| commit | b85690e239616b703881b7734b0559f61f9eb75e (patch) | |
| tree | f144325bc982177a8ff0d87ba87cc9e840bfb301 /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic | |
| parent | c30e615689148c6e5ecd06e86069cba716dec5e0 (diff) | |
| download | gem5-b85690e239616b703881b7734b0559f61f9eb75e.tar.xz | |
update all the regresstion tests for release
--HG--
extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic')
5 files changed, 681 insertions, 136 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 26242f3b3..791200f9a 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -5,8 +5,8 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -21,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -51,13 +56,101 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu.dtb] type=AlphaDTB size=64 +[system.cpu.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu.itb] type=AlphaITB size=48 @@ -65,7 +158,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -84,7 +177,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -106,27 +199,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -166,6 +299,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -175,7 +335,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -186,7 +346,7 @@ type=AlphaConsole cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -201,7 +361,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -211,19 +371,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -268,7 +430,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -284,7 +446,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -300,7 +462,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -316,7 +478,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -332,7 +494,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -348,7 +510,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -364,7 +526,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -380,7 +542,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -396,7 +558,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -412,7 +574,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -428,7 +590,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -444,7 +606,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -460,7 +622,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -476,7 +638,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -492,7 +654,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -508,7 +670,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -524,7 +686,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -540,7 +702,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -556,7 +718,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -573,7 +735,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -581,13 +743,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -631,9 +795,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -644,7 +808,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -662,7 +826,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index 7a0f99013..94cc53f32 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -11,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=atomic kernel=/dist/m5/system/binaries/vmlinux @@ -27,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -43,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -55,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -78,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -96,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.simple_disk.disk] type=RawDiskImage @@ -111,7 +154,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -126,7 +169,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -141,7 +184,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -156,7 +199,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -171,7 +214,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -186,7 +229,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -194,8 +237,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -241,7 +284,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -257,12 +300,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -277,7 +320,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -292,7 +335,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -300,7 +343,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -315,7 +358,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -330,7 +373,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -345,7 +388,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -360,7 +403,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -375,7 +418,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -390,7 +433,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -405,7 +448,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -420,7 +463,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -438,7 +481,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -479,12 +522,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -493,9 +538,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -512,7 +557,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -527,7 +572,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -535,7 +580,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -550,7 +595,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -601,18 +646,128 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.cpu.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index de848de68..aaa6c0c86 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,31 +1,199 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1069072 # Simulator instruction rate (inst/s) -host_mem_usage 251484 # Number of bytes of host memory used -host_seconds 56.13 # Real time elapsed on the host -host_tick_rate 65146530 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 60007301 # Number of instructions simulated -sim_seconds 1.828354 # Number of seconds simulated -sim_ticks 3656708271 # Number of ticks simulated +host_inst_rate 577751 # Simulator instruction rate (inst/s) +host_mem_usage 244724 # Number of bytes of host memory used +host_seconds 103.86 # Real time elapsed on the host +host_tick_rate 17603359253 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 60007317 # Number of instructions simulated +sim_seconds 1.828355 # Number of seconds simulated +sim_ticks 1828355481500 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 9723333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7984499 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.178831 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1738834 # number of ReadReq misses +system.cpu.dcache.WriteReq_accesses 6349447 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 6045093 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.047934 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 304354 # number of WriteReq misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 6.866570 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 16072780 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.demand_hits 14029592 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127121 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2043188 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 16072780 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 14029592 # number of overall hits +system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127121 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2043188 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.dcache.protocol.read_invalid 1738834 # read misses to invalid blocks +system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_inv_modified 1 # Invalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.dcache.protocol.snoop_read_exclusive 10 # read snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks +system.cpu.dcache.protocol.snoop_read_owned 2 # read snoops on owned blocks +system.cpu.dcache.protocol.snoop_read_shared 124 # read snoops on shared blocks +system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks +system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.dcache.protocol.write_invalid 304342 # write misses to invalid blocks +system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks +system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks +system.cpu.dcache.replacements 2042663 # number of replacements +system.cpu.dcache.sampled_refs 2043175 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use +system.cpu.dcache.total_refs 14029604 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16053817 # DTB hits +system.cpu.dtb.hits 16053818 # DTB hits system.cpu.dtb.misses 11471 # DTB misses system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9703849 # DTB read hits +system.cpu.dtb.read_hits 9703850 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_hits 6349968 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits 59087263 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 920054 # number of ReadReq misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 64.229545 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.demand_hits 59087263 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses +system.cpu.icache.demand_misses 920054 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 60007317 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 59087263 # number of overall hits +system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses +system.cpu.icache.overall_misses 920054 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.icache.protocol.read_invalid 920054 # read misses to invalid blocks +system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.icache.protocol.snoop_read_exclusive 643 # read snoops on exclusive blocks +system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu.icache.protocol.snoop_read_shared 1039 # read snoops on shared blocks +system.cpu.icache.protocol.snoop_readex_exclusive 105 # readEx snoops on exclusive blocks +system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks +system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.icache.protocol.snoop_upgrade_shared 9 # upgradee snoops on shared blocks +system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu.icache.replacements 919427 # number of replacements +system.cpu.icache.sampled_refs 919939 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use +system.cpu.icache.total_refs 59087263 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0.983588 # Percentage of idle cycles -system.cpu.itb.accesses 4979206 # ITB accesses +system.cpu.itb.accesses 4979217 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974200 # ITB hits +system.cpu.itb.hits 4974211 # ITB hits system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192138 # number of callpals executed +system.cpu.kern.callpal 192139 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -33,7 +201,7 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal_swpipl 175209 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_swpipl 175210 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed @@ -43,41 +211,40 @@ system.cpu.kern.callpal_rti 5202 2.71% 99.64% # nu system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211276 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211277 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed -system.cpu.kern.ipl_count 182520 # number of times we switched to this ipl +system.cpu.kern.ipl_count 182521 # number of times we switched to this ipl system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105597 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105598 57.86% 100.00% # number of times we switched to this ipl system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3656707856 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3622172407 99.06% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 40220 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 160390 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 34334839 0.94% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.816371 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks 1828355274000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087543000 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.695550 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1907 -system.cpu.kern.mode_good_user 1736 +system.cpu.kern.ipl_used_31 0.695543 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1908 +system.cpu.kern.mode_good_user 1737 system.cpu.kern.mode_good_idle 171 system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches -system.cpu.kern.mode_switch_user 1736 # number of protection mode switches +system.cpu.kern.mode_switch_user 1737 # number of protection mode switches system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.389940 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.320612 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.402325 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320780 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 53668047 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 2930128 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3600109679 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056177500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -111,9 +278,9 @@ system.cpu.kern.syscall_132 4 1.23% 98.77% # nu system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles -system.cpu.numCycles 60012491 # number of cpu cycles simulated -system.cpu.num_insts 60007301 # Number of instructions executed -system.cpu.num_refs 16302128 # Number of memory references +system.cpu.numCycles 60012507 # number of cpu cycles simulated +system.cpu.num_insts 60007317 # Number of instructions executed +system.cpu.num_refs 16302129 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -126,6 +293,68 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits 187346 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate 0.384423 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 116996 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2658871 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1717827 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.353926 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941044 # number of ReadReq misses +system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 428885 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.205900 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2658871 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_hits 1717827 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.353926 # miss rate for demand accesses +system.l2c.demand_misses 941044 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3087756 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 2146712 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.304766 # miss rate for overall accesses +system.l2c.overall_misses 941044 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 992432 # number of replacements +system.l2c.sampled_refs 1057820 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65517.661064 # Cycle average of tags in use +system.l2c.total_refs 2333445 # Total number of references to valid blocks. +system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 969291745..072cb6c8c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,5 +1,3 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index c3a1cb464..e47b6f226 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:52:08 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Global frequency set at 2000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3656708271 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:06:07 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1828355481500 because m5_exit instruction encountered |