diff options
| author | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-02-25 10:08:41 -0800 |
|---|---|---|
| committer | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-02-25 10:08:41 -0800 |
| commit | ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c (patch) | |
| tree | 93b9bd8be890468c550b85eae4b467285b4d6811 /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic | |
| parent | 7f3cd9a9fd636c1e48dcec20de3f6c14214d0ce4 (diff) | |
| download | gem5-ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c.tar.xz | |
stats: update stats for the changes I pushed re: shared cache occupancy
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic')
3 files changed, 239 insertions, 105 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index d098a0440..5eca545be 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux mem_mode=atomic -pal=/dist/m5/system/binaries/ts_osfpal +pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -74,7 +74,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -157,7 +157,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -177,7 +177,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -205,7 +205,7 @@ hash_delay=1 latency=50000 max_miss_count=0 mshrs=20 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 @@ -236,7 +236,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -303,7 +303,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index ee81c2844..a264b4253 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:02:48 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:10:46 -M5 executing on maize +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 24 2010 23:13:11 +M5 executing on SC2B0619 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 0982d41b4..8a27a93dd 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,29 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4370209 # Simulator instruction rate (inst/s) -host_mem_usage 276044 # Number of bytes of host memory used -host_seconds 13.74 # Real time elapsed on the host -host_tick_rate 133154437863 # Simulator tick rate (ticks/s) +host_inst_rate 2156504 # Simulator instruction rate (inst/s) +host_mem_usage 277176 # Number of bytes of host memory used +host_seconds 27.84 # Real time elapsed on the host +host_tick_rate 65706739181 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated sim_ticks 1829332258000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17162 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7807782 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate 0.180671 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1721705 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 169415 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_rate 0.149873 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses -system.cpu.dcache.WriteReq_accesses 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits 5753150 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate 0.064920 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 399424 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_accesses::0 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::0 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses::0 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::0 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate::0 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1721705 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 169415 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 169415 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate::0 0.149873 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 29867 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 29867 # number of StoreCondReq misses +system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::0 5753150 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5753150 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.064920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 399424 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 399424 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. @@ -32,31 +44,57 @@ system.cpu.dcache.blocked::no_targets 0 # nu system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15682061 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.demand_accesses::0 15682061 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits 13560932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 13560932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13560932 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135258 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2121129 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate::0 0.135258 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 2121129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2121129 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15682061 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.occ_%::0 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.997802 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15682061 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13560932 # number of overall hits +system.cpu.dcache.overall_hits::0 13560932 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 13560932 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135258 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2121129 # number of overall misses +system.cpu.dcache.overall_miss_rate::0 0.135258 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 2121129 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 2121129 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -83,10 +121,13 @@ system.cpu.dtb.write_accesses 291931 # DT system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_hits 6352498 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits 59129922 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate 0.015324 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 920221 # number of ReadReq misses +system.cpu.icache.ReadReq_accesses::0 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits::0 59129922 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate::0 0.015324 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 920221 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. @@ -95,31 +136,57 @@ system.cpu.icache.blocked::no_targets 0 # nu system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60050143 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.demand_accesses::0 60050143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.demand_hits 59129922 # number of demand (read+write) hits +system.cpu.icache.demand_hits::0 59129922 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.015324 # miss rate for demand accesses -system.cpu.icache.demand_misses 920221 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate::0 0.015324 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 920221 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60050143 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.occ_%::0 0.998467 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 511.215243 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 60050143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59129922 # number of overall hits +system.cpu.icache.overall_hits::0 59129922 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 59129922 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.015324 # miss rate for overall accesses -system.cpu.icache.overall_misses 920221 # number of overall misses +system.cpu.icache.overall_miss_rate::0 0.015324 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 920221 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 920221 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -247,12 +314,16 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 174 # number of ReadReq misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::1 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. @@ -261,31 +332,57 @@ system.iocache.blocked::no_targets 0 # nu system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41726 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 0 # average overall miss latency +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41726 # number of demand (read+write) misses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41726 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 0 # average overall miss latency +system.iocache.occ_%::1 0.076598 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.225570 # Average occupied blocks per context +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41726 # number of overall misses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 0 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -296,18 +393,27 @@ system.iocache.tagsinuse 1.225570 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304346 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304346 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2659071 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1696652 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.361938 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 962419 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 124945 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 124945 # number of UpgradeReq misses -system.l2c.Writeback_accesses 428893 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 428893 # number of Writeback hits +system.l2c.ReadExReq_accesses::0 304346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 304346 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 304346 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 2659071 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2659071 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 1696652 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1696652 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.361938 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 962419 # number of ReadReq misses +system.l2c.ReadReq_misses::total 962419 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 124945 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 124945 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 124945 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 124945 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 428893 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 428893 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 428893 # number of Writeback hits +system.l2c.Writeback_hits::total 428893 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 1.727246 # Average number of references to valid blocks. @@ -316,31 +422,59 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2963417 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_accesses::0 2963417 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2963417 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency +system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits 1696652 # number of demand (read+write) hits +system.l2c.demand_hits::0 1696652 # number of demand (read+write) hits +system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1696652 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.427468 # miss rate for demand accesses -system.l2c.demand_misses 1266765 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.427468 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.demand_misses::0 1266765 # number of demand (read+write) misses +system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 1266765 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2963417 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.occ_%::0 0.077203 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.384049 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5059.576308 # Average occupied blocks per context +system.l2c.occ_blocks::1 25169.009297 # Average occupied blocks per context +system.l2c.overall_accesses::0 2963417 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2963417 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 no_value # average overall miss latency +system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits 1696652 # number of overall hits +system.l2c.overall_hits::0 1696652 # number of overall hits +system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::total 1696652 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.427468 # miss rate for overall accesses -system.l2c.overall_misses 1266765 # number of overall misses +system.l2c.overall_miss_rate::0 0.427468 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.overall_misses::0 1266765 # number of overall misses +system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::total 1266765 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |