diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-10 16:14:02 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-10 16:14:02 -0400 |
commit | 9493501fdb087c82111d8692995474f2e8f3f390 (patch) | |
tree | e9c87ab5f27c44399bc91628d60f7c4fa7565627 /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini | |
parent | 06a9f58c68b621f082d39299bdb01f59ef68ef0e (diff) | |
download | gem5-9493501fdb087c82111d8692995474f2e8f3f390.tar.xz |
Regression: Add an I/O Cache to the full system regressions that have a cache.
--HG--
extra : convert_revision : 8ba96e21be2f602eed8258d410038dbe998ef176
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini')
-rw-r--r-- | tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini | 66 |
1 files changed, 56 insertions, 10 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index bbfd059cd..f2dae72bb 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -22,8 +22,8 @@ system_type=34 [system.bridge] type=Bridge delay=50000 -fix_partial_write_a=false -fix_partial_write_b=true +filter_ranges_a=0:18446744073709551615 +filter_ranges_b=0:8589934591 nack_delay=4000 req_size_a=16 req_size_b=16 @@ -63,10 +63,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=4 prefetch_access=false prefetch_cache_check_push=true @@ -101,10 +103,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=4 prefetch_access=false prefetch_cache_check_push=true @@ -167,10 +171,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=4 prefetch_access=false prefetch_cache_check_push=true @@ -205,10 +211,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=4 prefetch_access=false prefetch_cache_check_push=true @@ -291,17 +299,55 @@ clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio -port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma + +[system.iocache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges=549755813888:18446744073709551615 +hash_delay=1 +latency=50000 +lifo=false +max_miss_count=0 +mem_side_filter_ranges=0:18446744073709551615 +mshrs=20 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=500000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.port[28] +mem_side=system.membus.port[2] [system.l2c] type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=10000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=92 prefetch_access=false prefetch_cache_check_push=true @@ -325,7 +371,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.port[0] -mem_side=system.membus.port[2] +mem_side=system.membus.port[3] [system.membus] type=Bus @@ -336,7 +382,7 @@ clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side +port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side [system.membus.responder] type=IsaFake @@ -470,8 +516,8 @@ system=system tx_delay=1000000 tx_fifo_size=524288 tx_thread=false -config=system.iobus.port[28] -dma=system.iobus.port[29] +config=system.iobus.port[29] +dma=system.iobus.port[30] pio=system.iobus.port[27] [system.tsunami.ethernet.configdata] @@ -836,8 +882,8 @@ pci_func=0 pio_latency=1000 platform=system.tsunami system=system -config=system.iobus.port[30] -dma=system.iobus.port[31] +config=system.iobus.port[31] +dma=system.iobus.port[32] pio=system.iobus.port[26] [system.tsunami.ide.configdata] |