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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-09-28 13:22:34 -0400 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-09-28 13:22:34 -0400 |
commit | 272d867402e50dba49f1f78976711388a8056427 (patch) | |
tree | 4542f12377fae4e2f31a592b161997487856cd74 /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual | |
parent | d2a4f595d6e70f5f9f5c7cae4f496c2db1e39ca5 (diff) | |
download | gem5-272d867402e50dba49f1f78976711388a8056427.tar.xz |
Update statistics for the last three revisions
--HG--
extra : convert_revision : 117e2a40bd6e0867d013a3a6076fb758ac526d24
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual')
-rw-r--r-- | tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini | 103 | ||||
-rw-r--r-- | tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt | 12 |
2 files changed, 50 insertions, 65 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index f2dae72bb..4dde5bc10 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -456,7 +456,7 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system @@ -480,48 +480,8 @@ sim_console=system.sim_console system=system pio=system.iobus.port[25] -[system.tsunami.etherint] -type=NSGigEInt -device=system.tsunami.ethernet -peer=Null - [system.tsunami.ethernet] type=NSGigE -children=configdata -clock=0 -config_latency=20000 -configdata=system.tsunami.ethernet.configdata -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -hardware_address=00:90:00:00:00:01 -intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=1000 -platform=system.tsunami -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -config=system.iobus.port[29] -dma=system.iobus.port[30] -pio=system.iobus.port[27] - -[system.tsunami.ethernet.configdata] -type=PciConfigData BAR0=1 BAR0Size=256 BAR1=0 @@ -554,6 +514,36 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 +clock=0 +config_latency=20000 +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:01 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=system +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=system.iobus.port[29] +dma=system.iobus.port[30] +pio=system.iobus.port[27] [system.tsunami.fake_OROM] type=IsaFake @@ -870,24 +860,6 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController -children=configdata -config_latency=20000 -configdata=system.tsunami.ide.configdata -disks=system.disk0 system.disk2 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=1000 -platform=system.tsunami -system=system -config=system.iobus.port[31] -dma=system.iobus.port[32] -pio=system.iobus.port[26] - -[system.tsunami.ide.configdata] -type=PciConfigData BAR0=1 BAR0Size=8 BAR1=1 @@ -920,6 +892,19 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +config_latency=20000 +disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +system=system +config=system.iobus.port[31] +dma=system.iobus.port[32] +pio=system.iobus.port[26] [system.tsunami.io] type=TsunamiIO diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 8b29b06d6..e6200df10 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 979093 # Simulator instruction rate (inst/s) -host_mem_usage 278732 # Number of bytes of host memory used -host_seconds 66.19 # Real time elapsed on the host -host_tick_rate 29741162851 # Simulator tick rate (ticks/s) +host_inst_rate 1027363 # Simulator instruction rate (inst/s) +host_mem_usage 295468 # Number of bytes of host memory used +host_seconds 63.08 # Real time elapsed on the host +host_tick_rate 31207407187 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 64810685 # Number of instructions simulated sim_seconds 1.968714 # Number of seconds simulated @@ -273,7 +273,7 @@ system.cpu0.kern.syscall_132 2 0.94% 98.58% # nu system.cpu0.kern.syscall_144 1 0.47% 99.06% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.94% 100.00% # number of syscalls executed system.cpu0.not_idle_fraction 0.057929 # Percentage of non-idle cycles -system.cpu0.numCycles 1967810461000 # number of cpu cycles simulated +system.cpu0.numCycles 3935620922 # number of cpu cycles simulated system.cpu0.num_insts 50990937 # Number of instructions executed system.cpu0.num_refs 13220047 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 60083 # number of LoadLockedReq accesses(hits+misses) @@ -528,7 +528,7 @@ system.cpu1.kern.syscall_92 2 1.75% 97.37% # nu system.cpu1.kern.syscall_132 2 1.75% 99.12% # number of syscalls executed system.cpu1.kern.syscall_144 1 0.88% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.013720 # Percentage of non-idle cycles -system.cpu1.numCycles 1968713509000 # number of cpu cycles simulated +system.cpu1.numCycles 3937427018 # number of cpu cycles simulated system.cpu1.num_insts 13819748 # Number of instructions executed system.cpu1.num_refs 4429865 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). |