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authorNathan Binkert <nate@binkert.org>2011-04-19 18:45:23 -0700
committerNathan Binkert <nate@binkert.org>2011-04-19 18:45:23 -0700
commit8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch)
tree8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual
parent63371c86648ed65a453a95aec80f326f15a9666d (diff)
downloadgem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz
tests: update stats for name changes
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual')
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini6
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout7
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt26
3 files changed, 22 insertions, 17 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 41a7379e1..8d055ed5f 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -78,6 +78,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -113,6 +114,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -182,6 +184,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -217,6 +220,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -313,6 +317,7 @@ assoc=8
block_size=64
forward_snoops=false
hash_delay=1
+is_top_level=true
latency=50000
max_miss_count=0
mshrs=20
@@ -344,6 +349,7 @@ assoc=8
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 8f8e92a25..a027f13fc 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:17:36
+M5 started Apr 19 2011 12:17:43
+M5 executing on maize
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 6e0648c43..58de64347 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 901052 # Simulator instruction rate (inst/s)
-host_mem_usage 309020 # Number of bytes of host memory used
-host_seconds 65.87 # Real time elapsed on the host
-host_tick_rate 29733229075 # Simulator tick rate (ticks/s)
+host_inst_rate 2296983 # Simulator instruction rate (inst/s)
+host_mem_usage 289272 # Number of bytes of host memory used
+host_seconds 25.84 # Real time elapsed on the host
+host_tick_rate 75796433096 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 59355643 # Number of instructions simulated
sim_seconds 1.958647 # Number of seconds simulated
@@ -114,10 +114,10 @@ system.cpu0.dcache.demand_mshr_misses 1327637 # nu
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0 0.983447 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0 503.524900 # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0 0.983447 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy
system.cpu0.dcache.overall_accesses::0 14308776 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses
@@ -218,8 +218,8 @@ system.cpu0.icache.demand_mshr_misses 915781 # nu
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0 0.993751 # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0 508.800486 # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0 0.993751 # Average percentage of cache occupancy
system.cpu0.icache.overall_accesses::0 54081252 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses
@@ -484,8 +484,8 @@ system.cpu1.dcache.demand_mshr_misses 57534 # nu
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0 0.760784 # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0 389.521271 # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0 0.760784 # Average percentage of cache occupancy
system.cpu1.dcache.overall_accesses::0 1677594 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses
@@ -586,8 +586,8 @@ system.cpu1.icache.demand_mshr_misses 87005 # nu
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0 0.819937 # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0 419.807616 # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0 0.819937 # Average percentage of cache occupancy
system.cpu1.icache.overall_accesses::0 5286354 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses
@@ -801,8 +801,8 @@ system.iocache.demand_mshr_misses 41726 # nu
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.occ_%::1 0.035233 # Average percentage of cache occupancy
system.iocache.occ_blocks::1 0.563721 # Average occupied blocks per context
+system.iocache.occ_percent::1 0.035233 # Average percentage of cache occupancy
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
@@ -977,12 +977,12 @@ system.l2c.demand_mshr_misses 428511 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.165831 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.003052 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.357359 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 10867.929163 # Average occupied blocks per context
system.l2c.occ_blocks::1 199.983935 # Average occupied blocks per context
system.l2c.occ_blocks::2 23419.887612 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.165831 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.003052 # Average percentage of cache occupancy
+system.l2c.occ_percent::2 0.357359 # Average percentage of cache occupancy
system.l2c.overall_accesses::0 2250056 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 139909 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses