Update stats for new prefetching fixes.

Prefetching is not enabled in any of our regressions, so no significant
stat values have changed, but zero-valued prefetch stats no longer
show up when prefetching is disabled so there are noticable changes
in the reference stat files anyway.

4 files changed, 35 insertions, 77 deletions

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index de9bfc9e4..f8e47e1b8 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -36,6 +36,7 @@ side_b=system.membus.port[0]
 [system.cpu0]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts itb tracer
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
@@ -71,12 +72,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -108,12 +108,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -143,6 +142,7 @@ type=ExeTracer
 [system.cpu1]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts itb tracer
+checker=Null
 clock=500
 cpu_id=1
 defer_registration=false
@@ -178,12 +178,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -215,12 +214,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -258,6 +256,7 @@ image=system.disk0.image
 type=CowDiskImage
 children=child
 child=system.disk0.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -277,6 +276,7 @@ image=system.disk2.image
 type=CowDiskImage
 children=child
 child=system.disk2.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -311,12 +311,11 @@ latency=50000
 max_miss_count=0
 mem_side_filter_ranges=0:18446744073709551615
 mshrs=20
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=500000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -344,12 +343,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=92
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -479,16 +477,22 @@ pio=system.iobus.port[1]
 [system.tsunami.ethernet]
 type=NSGigE
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=256
 BAR1=0
+BAR1LegacyIO=false
 BAR1Size=4096
 BAR2=0
+BAR2LegacyIO=false
 BAR2Size=0
 BAR3=0
+BAR3LegacyIO=false
 BAR3Size=0
 BAR4=0
+BAR4LegacyIO=false
 BAR4Size=0
 BAR5=0
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
@@ -857,16 +861,22 @@ pio=system.iobus.port[22]
 [system.tsunami.ide]
 type=IdeController
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=8
 BAR1=1
+BAR1LegacyIO=false
 BAR1Size=4
 BAR2=1
+BAR2LegacyIO=false
 BAR2Size=8
 BAR3=1
+BAR3LegacyIO=false
 BAR3Size=4
 BAR4=1
+BAR4LegacyIO=false
 BAR4Size=16
 BAR5=1
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
index dad1cad88..e077a7fd9 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
@@ -1,5 +1,7 @@
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
 warn: Sockets disabled, not accepting terminal connections
+For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
 warn: 591544000: Trying to launch CPU number 1!
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/8f7d2563
+hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 9f8bf8070..6b56db972 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec 14 2008 21:47:07
-M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
-M5 commit date Sun Dec 14 21:45:15 2008 -0800
-M5 started Dec 14 2008 21:47:52
-M5 executing on tater
+M5 compiled Feb 16 2009 00:15:24
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:15:51
+M5 executing on zizzer
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1972135461000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 2f2449fdc..4a6754053 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 741695                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 289172                       # Number of bytes of host memory used
-host_seconds                                    80.11                       # Real time elapsed on the host
-host_tick_rate                            24616375840                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1382701                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 289788                       # Number of bytes of host memory used
+host_seconds                                    42.97                       # Real time elapsed on the host
+host_tick_rate                            45890646030                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    59420593                       # Number of instructions simulated
 sim_seconds                                  1.972135                       # Number of seconds simulated
@@ -88,15 +88,6 @@ system.cpu0.dcache.overall_mshr_miss_rate     0.098910                       # m
 system.cpu0.dcache.overall_mshr_misses        1417958                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_uncacheable_latency   2124474000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu0.dcache.replacements               1338610                       # number of replacements
 system.cpu0.dcache.sampled_refs               1339122                       # Sample count of references to valid blocks.
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -162,15 +153,6 @@ system.cpu0.icache.overall_mshr_miss_rate     0.016917                       # m
 system.cpu0.icache.overall_mshr_misses         916324                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu0.icache.replacements                915684                       # number of replacements
 system.cpu0.icache.sampled_refs                916195                       # Sample count of references to valid blocks.
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -356,15 +338,6 @@ system.cpu1.dcache.overall_mshr_miss_rate     0.037169                       # m
 system.cpu1.dcache.overall_mshr_misses          62092                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_uncacheable_latency    315545000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu1.dcache.replacements                 53724                       # number of replacements
 system.cpu1.dcache.sampled_refs                 54120                       # Sample count of references to valid blocks.
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -430,15 +403,6 @@ system.cpu1.icache.overall_mshr_miss_rate     0.016597                       # m
 system.cpu1.icache.overall_mshr_misses          87436                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu1.icache.replacements                 86896                       # number of replacements
 system.cpu1.icache.sampled_refs                 87408                       # Sample count of references to valid blocks.
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -597,15 +561,6 @@ system.iocache.overall_mshr_miss_rate               1                       # ms
 system.iocache.overall_mshr_misses              41730                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.iocache.replacements                     41698                       # number of replacements
 system.iocache.sampled_refs                     41714                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
@@ -684,15 +639,6 @@ system.l2c.overall_mshr_miss_rate            0.256233                       # ms
 system.l2c.overall_mshr_misses                 614222                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency   2197317000                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.l2c.replacements                        399005                       # number of replacements
 system.l2c.sampled_refs                        430732                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions