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| author | Nathan Binkert <binkertn@umich.edu> | 2007-06-12 07:56:53 -0700 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2007-06-12 07:56:53 -0700 |
| commit | 1a3e668446e4b2d2c61651c9ae58e643c2aa3ad2 (patch) | |
| tree | c1a0811248e7d8addf4e84d3532e5d506e8aaec8 /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini | |
| parent | 125237d357be7f2c5adf03da8dcf352ccad32954 (diff) | |
| download | gem5-1a3e668446e4b2d2c61651c9ae58e643c2aa3ad2.tar.xz | |
update for small parameter and statistics name changes
--HG--
extra : convert_revision : d538b79986c11a462ab285c167cef45dd793da32
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini')
| -rw-r--r-- | tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index ded525737..c726f11fe 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -74,7 +74,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -122,7 +122,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -221,7 +221,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -252,7 +252,7 @@ clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.l2c.mem_side +port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side [system.membus.responder] type=IsaFake |