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authorNathan Binkert <nate@binkert.org>2008-12-08 07:16:40 -0800
committerNathan Binkert <nate@binkert.org>2008-12-08 07:16:40 -0800
commit19273164da50011d59b7f362026f8e80260807d4 (patch)
treebf5053cec37827ff14037776b019990ffaed32cc /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
parent9192b7f1effaa9aabdd61840903e4f0c12079758 (diff)
downloadgem5-19273164da50011d59b7f362026f8e80260807d4.tar.xz
output: Change default output directory and files and update tests.
--HG-- rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr => tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout => tests/long/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr => tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout => tests/long/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr => tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout => tests/long/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stderr => tests/long/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stdout => tests/long/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr => tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout => tests/long/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr => tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout => tests/long/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stderr => tests/long/10.mcf/ref/x86/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stdout => tests/long/10.mcf/ref/x86/linux/simple-timing/simout rename : tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stderr => tests/long/20.parser/ref/x86/linux/simple-atomic/simerr rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stdout => tests/long/20.parser/ref/x86/linux/simple-atomic/simout rename : tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-timing/stderr => tests/long/20.parser/ref/x86/linux/simple-timing/simerr rename : tests/long/20.parser/ref/x86/linux/simple-timing/stdout => tests/long/20.parser/ref/x86/linux/simple-timing/simout rename : tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr => tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout => tests/long/30.eon/ref/alpha/tru64/o3-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr => tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout => tests/long/30.eon/ref/alpha/tru64/simple-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr => tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout => tests/long/50.vortex/ref/sparc/linux/simple-timing/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr => tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout => tests/long/60.bzip2/ref/x86/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr => tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout => tests/long/70.twolf/ref/sparc/linux/simple-timing/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr => tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout => tests/long/70.twolf/ref/x86/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stderr => tests/long/70.twolf/ref/x86/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stdout => tests/long/70.twolf/ref/x86/linux/simple-timing/simout rename : tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr => tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout => tests/quick/00.hello/ref/alpha/linux/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr => tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout => tests/quick/00.hello/ref/alpha/linux/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr => tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout => tests/quick/00.hello/ref/mips/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stderr => tests/quick/00.hello/ref/mips/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stdout => tests/quick/00.hello/ref/mips/linux/simple-timing/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr => tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout => tests/quick/00.hello/ref/sparc/linux/simple-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr => tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout => tests/quick/00.hello/ref/x86/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stderr => tests/quick/00.hello/ref/x86/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stdout => tests/quick/00.hello/ref/x86/linux/simple-timing/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/simout rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stderr => tests/quick/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stdout => tests/quick/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt => tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt')
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt474
1 files changed, 474 insertions, 0 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
new file mode 100644
index 000000000..bcad4cd62
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -0,0 +1,474 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1283720 # Simulator instruction rate (inst/s)
+host_mem_usage 286560 # Number of bytes of host memory used
+host_seconds 43.75 # Real time elapsed on the host
+host_tick_rate 44115985890 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 56165112 # Number of instructions simulated
+sim_seconds 1.930166 # Number of seconds simulated
+sim_ticks 1930165791000 # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses 200388 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.212121 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.212121 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits 183063 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 248808000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate 0.086457 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses 17325 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196833000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086457 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_misses 17325 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 8882666 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 25452.857499 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.814515 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_hits 7812517 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 27238350000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.120476 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1070149 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 24027857000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.120476 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1070149 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 847845000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses 199368 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.365794 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.365794 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_hits 169362 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_latency 1680467000 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_rate 0.150506 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses 30006 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590449000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150506 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_misses 30006 # number of StoreCondReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6158164 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56004.032630 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.032630 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_hits 5757309 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 22449496500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.065093 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 21246931500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.065093 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1186275000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 10.091593 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 15040830 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 33778.185851 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 13569826 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 49687846500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.097801 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1471004 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 45274788500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.097801 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1471004 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 15040830 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 33778.185851 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 13569826 # number of overall hits
+system.cpu.dcache.overall_miss_latency 49687846500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.097801 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1471004 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 45274788500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.097801 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1471004 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 2034120000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 1391586 # number of replacements
+system.cpu.dcache.sampled_refs 1392098 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 511.984141 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14048487 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 430461 # number of writebacks
+system.cpu.dtb.accesses 1020784 # DTB accesses
+system.cpu.dtb.acv 367 # DTB access violations
+system.cpu.dtb.hits 15421361 # DTB hits
+system.cpu.dtb.misses 11466 # DTB misses
+system.cpu.dtb.read_accesses 728853 # DTB read accesses
+system.cpu.dtb.read_acv 210 # DTB read access violations
+system.cpu.dtb.read_hits 9063577 # DTB read hits
+system.cpu.dtb.read_misses 10324 # DTB read misses
+system.cpu.dtb.write_accesses 291931 # DTB write accesses
+system.cpu.dtb.write_acv 157 # DTB write access violations
+system.cpu.dtb.write_hits 6357784 # DTB write hits
+system.cpu.dtb.write_misses 1142 # DTB write misses
+system.cpu.icache.ReadReq_accesses 56176946 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 14711.628674 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.898216 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 55246023 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 13695393500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.016571 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 930923 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 10901944500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.016571 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 930923 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 59.355692 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 56176946 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 14711.628674 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency
+system.cpu.icache.demand_hits 55246023 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 13695393500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.016571 # miss rate for demand accesses
+system.cpu.icache.demand_misses 930923 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 10901944500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.016571 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 930923 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 56176946 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 14711.628674 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 55246023 # number of overall hits
+system.cpu.icache.overall_miss_latency 13695393500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.016571 # miss rate for overall accesses
+system.cpu.icache.overall_misses 930923 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 10901944500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.016571 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 930923 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 930251 # number of replacements
+system.cpu.icache.sampled_refs 930762 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 508.559731 # Cycle average of tags in use
+system.cpu.icache.total_refs 55246023 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0.929251 # Percentage of idle cycles
+system.cpu.itb.accesses 4982832 # ITB accesses
+system.cpu.itb.acv 184 # ITB acv
+system.cpu.itb.hits 4977822 # ITB hits
+system.cpu.itb.misses 5010 # ITB misses
+system.cpu.kern.callpal 193204 # number of callpals executed
+system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed
+system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed
+system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed
+system.cpu.kern.callpal_swpipl 176240 91.22% 93.41% # number of callpals executed
+system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed
+system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal_rti 5169 2.68% 99.64% # number of callpals executed
+system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
+system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.hwrei 212308 # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce 6258 # number of quiesce instructions executed
+system.cpu.kern.ipl_count 183485 # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0 74993 40.87% 40.87% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31 106417 58.00% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good 149327 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0 73626 49.31% 49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31 73626 49.31% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks 1930165033000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0 1867007591000 96.73% 96.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21 96059500 0.00% 96.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22 565327500 0.03% 96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31 62496055000 3.24% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used_0 0.981772 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_31 0.691863 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel 1910
+system.cpu.kern.mode_good_user 1743
+system.cpu.kern.mode_good_idle 167
+system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches
+system.cpu.kern.mode_switch_user 1743 # number of protection mode switches
+system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches
+system.cpu.kern.mode_switch_good 1.402741 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel 0.322799 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel 48448667000 2.51% 2.51% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user 5540662000 0.29% 2.80% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle 1876175702000 97.20% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4172 # number of times the context was actually changed
+system.cpu.kern.syscall 326 # number of syscalls executed
+system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
+system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
+system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed
+system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed
+system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed
+system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed
+system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed
+system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed
+system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed
+system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed
+system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed
+system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed
+system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed
+system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed
+system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed
+system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed
+system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed
+system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed
+system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed
+system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed
+system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed
+system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed
+system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed
+system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed
+system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed
+system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed
+system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed
+system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
+system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
+system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
+system.cpu.not_idle_fraction 0.070749 # Percentage of non-idle cycles
+system.cpu.numCycles 3860331582 # number of cpu cycles simulated
+system.cpu.num_insts 56165112 # Number of instructions executed
+system.cpu.num_refs 15669461 # Number of memory references
+system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
+system.disk0.dma_write_txs 395 # Number of DMA write transactions.
+system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses 173 # number of ReadReq misses
+system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
+system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_avg_miss_latency 137880.578697 # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85877.091981 # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency 5729213806 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses 41552 # number of WriteReq misses
+system.iocache.WriteReq_mshr_miss_latency 3568364926 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
+system.iocache.avg_blocked_cycles_no_mshrs 6163.865928 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.iocache.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked
+system.iocache.blocked_no_targets 0 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs 64548004 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency 137786.765824 # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency
+system.iocache.demand_hits 0 # number of demand (read+write) hits
+system.iocache.demand_miss_latency 5749152804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate 1 # miss rate for demand accesses
+system.iocache.demand_misses 41725 # number of demand (read+write) misses
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency 3579307924 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency 137786.765824 # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.iocache.overall_hits 0 # number of overall hits
+system.iocache.overall_miss_latency 5749152804 # number of overall miss cycles
+system.iocache.overall_miss_rate 1 # miss rate for overall accesses
+system.iocache.overall_misses 41725 # number of overall misses
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency 3579307924 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements 41685 # number of replacements
+system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse 1.353410 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.warmup_cycle 1762299198000 # Cycle when the warmup percentage was hit.
+system.iocache.writebacks 41512 # number of writebacks
+system.l2c.ReadExReq_accesses 304625 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 52003.272876 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40003.272876 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 15841497000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 304625 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 12185997000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 304625 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 2018377 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 52016.376522 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.358642 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits 1710772 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 16000497500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.152402 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 307605 # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency 12309232000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.152402 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 307605 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 759315000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses 126236 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 52001.881397 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.980861 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 6564509500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 126236 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 5050195000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 126236 # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency 1071771000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses 430461 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 430461 # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_refs 4.436452 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.demand_accesses 2323002 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 52009.856590 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency
+system.l2c.demand_hits 1710772 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 31841994500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.263551 # miss rate for demand accesses
+system.l2c.demand_misses 612230 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 24495229000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.263551 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 612230 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.overall_accesses 2323002 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 52009.856590 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.overall_hits 1710772 # number of overall hits
+system.l2c.overall_miss_latency 31841994500 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.263551 # miss rate for overall accesses
+system.l2c.overall_misses 612230 # number of overall misses
+system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 24495229000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.263551 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 612230 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 1831086000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements 394925 # number of replacements
+system.l2c.sampled_refs 425907 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 30594.024615 # Cycle average of tags in use
+system.l2c.total_refs 1889516 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 119047 # number of writebacks
+system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+
+---------- End Simulation Statistics ----------
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-18 08:48:39 +0000