diff options
author | Steve Reinhardt <stever@gmail.com> | 2008-08-03 18:13:29 -0400 |
---|---|---|
committer | Steve Reinhardt <stever@gmail.com> | 2008-08-03 18:13:29 -0400 |
commit | 62c08a75ad18fda5d06d919db6d8d31a79be9630 (patch) | |
tree | 739253709735d1a8b5da963d2230a5418779d297 /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal | |
parent | b179c3f4cd1e89872de34d70105f703e72377029 (diff) | |
download | gem5-62c08a75ad18fda5d06d919db6d8d31a79be9630.tar.xz |
Make default PhysicalMemory latency slightly more realistic.
Also update stats to reflect change.
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal')
-rw-r--r-- | tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal index 7930e9e46..3efa225a8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal @@ -24,6 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 +
4096K Bcache detected; load hit latency 40 cycles, load miss latency 124 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 |