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authorNathan Binkert <nate@binkert.org>2011-04-19 18:45:23 -0700
committerNathan Binkert <nate@binkert.org>2011-04-19 18:45:23 -0700
commit8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch)
tree8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing
parent63371c86648ed65a453a95aec80f326f15a9666d (diff)
downloadgem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz
tests: update stats for name changes
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing')
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini4
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout7
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt18
3 files changed, 16 insertions, 13 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index f28d4e037..80db30395 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -78,6 +78,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -113,6 +114,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -209,6 +211,7 @@ assoc=8
block_size=64
forward_snoops=false
hash_delay=1
+is_top_level=true
latency=50000
max_miss_count=0
mshrs=20
@@ -240,6 +243,7 @@ assoc=8
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index be2bcef8d..aee40b816 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:17:36
+M5 started Apr 19 2011 12:17:43
+M5 executing on maize
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 5f1750494..397168bed 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1077887 # Simulator instruction rate (inst/s)
-host_mem_usage 307624 # Number of bytes of host memory used
-host_seconds 52.08 # Real time elapsed on the host
-host_tick_rate 36780244064 # Simulator tick rate (ticks/s)
+host_inst_rate 2410973 # Simulator instruction rate (inst/s)
+host_mem_usage 287860 # Number of bytes of host memory used
+host_seconds 23.28 # Real time elapsed on the host
+host_tick_rate 82268225536 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 56137087 # Number of instructions simulated
sim_seconds 1.915549 # Number of seconds simulated
@@ -101,8 +101,8 @@ system.cpu.dcache.demand_mshr_misses 1373445 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999969 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 511.984023 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.999969 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses::0 15029535 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses
@@ -203,8 +203,8 @@ system.cpu.icache.demand_mshr_misses 928354 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.993597 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 508.721464 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.993597 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses::0 56148907 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses
@@ -435,8 +435,8 @@ system.iocache.demand_mshr_misses 41725 # nu
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.occ_%::1 0.083770 # Average percentage of cache occupancy
system.iocache.occ_blocks::1 1.340325 # Average occupied blocks per context
+system.iocache.occ_percent::1 0.083770 # Average percentage of cache occupancy
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
@@ -563,10 +563,10 @@ system.l2c.demand_mshr_misses 422432 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.171530 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.352641 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 11241.373247 # Average occupied blocks per context
system.l2c.occ_blocks::1 23110.665097 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.171530 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.352641 # Average percentage of cache occupancy
system.l2c.overall_accesses::0 2318771 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses