diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-05-18 13:36:47 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-05-18 13:36:47 -0700 |
| commit | a13d5af274a1847eaad649af226e643e86a3322d (patch) | |
| tree | 6b3bdd0b269802b324b4744e6ed8362d1917e1a0 /tests/quick/10.linux-boot/ref/alpha | |
| parent | 6a6e62014ec72f9dd29a42c3e92fbc91d6b1f648 (diff) | |
| parent | a8278c3bde2ba9abc2820afafa9d0e766e36b2c8 (diff) | |
| download | gem5-a13d5af274a1847eaad649af226e643e86a3322d.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into doughnut.mwconnections.com:/home/gblack/m5/newmem-x86
--HG--
extra : convert_revision : 3f17fc418ee5a30da2b08a515fb394cc8fcdd237
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha')
20 files changed, 3970 insertions, 1019 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index ce952d718..6e38281a1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -1,16 +1,12 @@ [root] type=Root children=system -checkpoint= -clock=2000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -25,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu0] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -55,21 +56,109 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu0.dtb] type=AlphaDTB size=64 +[system.cpu0.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu0.itb] type=AlphaITB size=48 [system.cpu1] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true @@ -89,13 +178,101 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[5] -icache_port=system.membus.port[4] +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu1.dtb] type=AlphaDTB size=64 +[system.cpu1.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu1.itb] type=AlphaITB size=48 @@ -103,7 +280,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -122,7 +299,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -144,27 +321,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -204,6 +421,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -213,7 +457,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -224,7 +468,7 @@ type=AlphaConsole cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -239,7 +483,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -249,19 +493,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -306,7 +552,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -322,7 +568,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -338,7 +584,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -354,7 +600,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -370,7 +616,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -386,7 +632,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -402,7 +648,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -418,7 +664,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -434,7 +680,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -450,7 +696,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -466,7 +712,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -482,7 +728,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -498,7 +744,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -514,7 +760,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -530,7 +776,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -546,7 +792,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -562,7 +808,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -578,7 +824,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -594,7 +840,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -611,7 +857,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -619,13 +865,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -669,9 +917,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -682,7 +930,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -700,7 +948,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out index 313620c59..324ede6b4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=2000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -14,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=atomic kernel=/dist/m5/system/binaries/vmlinux @@ -30,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -46,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -58,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -81,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -99,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.cpu0.itb] type=AlphaITB @@ -124,7 +164,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -132,6 +172,90 @@ function_trace=false function_trace_start=0 simulate_stalls=false +[system.cpu0.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.cpu1.itb] type=AlphaITB size=48 @@ -155,7 +279,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -163,6 +287,90 @@ function_trace=false function_trace_start=0 simulate_stalls=false +[system.cpu1.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.simple_disk.disk] type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img @@ -176,7 +384,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -191,7 +399,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -206,7 +414,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -221,7 +429,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -236,7 +444,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -251,7 +459,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -259,8 +467,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -291,12 +499,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu0 platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -311,7 +519,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -326,7 +534,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -334,7 +542,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -349,7 +557,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -364,7 +572,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -379,7 +587,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -394,7 +602,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -409,7 +617,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -424,7 +632,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -439,7 +647,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -454,7 +662,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -472,7 +680,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -513,12 +721,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -527,9 +737,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -546,7 +756,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -561,7 +771,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -569,7 +779,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -584,7 +794,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -635,18 +845,44 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 4dbe8c13c..7765c2852 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,232 +1,632 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1026206 # Simulator instruction rate (inst/s) -host_mem_usage 240860 # Number of bytes of host memory used -host_seconds 63.27 # Real time elapsed on the host -host_tick_rate 58764450 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 64932819 # Number of instructions simulated -sim_seconds 1.859157 # Number of seconds simulated -sim_ticks 3718314928 # Number of ticks simulated -system.cpu0.dtb.accesses 544556 # DTB accesses -system.cpu0.dtb.acv 335 # DTB access violations -system.cpu0.dtb.hits 14841931 # DTB hits -system.cpu0.dtb.misses 7356 # DTB misses -system.cpu0.dtb.read_accesses 377530 # DTB read accesses -system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_hits 8970576 # DTB read hits -system.cpu0.dtb.read_misses 6581 # DTB read misses -system.cpu0.dtb.write_accesses 167026 # DTB write accesses -system.cpu0.dtb.write_acv 125 # DTB write access violations -system.cpu0.dtb.write_hits 5871355 # DTB write hits -system.cpu0.dtb.write_misses 775 # DTB write misses -system.cpu0.idle_fraction 0.984944 # Percentage of idle cycles -system.cpu0.itb.accesses 3586919 # ITB accesses -system.cpu0.itb.acv 184 # ITB acv -system.cpu0.itb.hits 3583450 # ITB hits -system.cpu0.itb.misses 3469 # ITB misses -system.cpu0.kern.callpal 182754 # number of callpals executed +host_inst_rate 607412 # Simulator instruction rate (inst/s) +host_mem_usage 245896 # Number of bytes of host memory used +host_seconds 103.93 # Real time elapsed on the host +host_tick_rate 17996726251 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 63125943 # Number of instructions simulated +sim_seconds 1.870335 # Number of seconds simulated +sim_ticks 1870335097000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 9163941 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7464208 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.185481 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1699733 # number of ReadReq misses +system.cpu0.dcache.WriteReq_accesses 5933396 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5646723 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.048315 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 286673 # number of WriteReq misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 6.625609 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 15097337 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.demand_hits 13110931 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.131573 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1986406 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 15097337 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 13110931 # number of overall hits +system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.131573 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1986406 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.dcache.protocol.read_invalid 1699733 # read misses to invalid blocks +system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_inv_modified 2 # Invalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.dcache.protocol.snoop_read_exclusive 689 # read snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_read_modified 4128 # read snoops on modified blocks +system.cpu0.dcache.protocol.snoop_read_owned 122 # read snoops on owned blocks +system.cpu0.dcache.protocol.snoop_read_shared 2691 # read snoops on shared blocks +system.cpu0.dcache.protocol.snoop_readex_exclusive 241 # readEx snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_readex_modified 227 # readEx snoops on modified blocks +system.cpu0.dcache.protocol.snoop_readex_owned 21 # readEx snoops on owned blocks +system.cpu0.dcache.protocol.snoop_readex_shared 14 # readEx snoops on shared blocks +system.cpu0.dcache.protocol.snoop_upgrade_owned 1359 # upgrade snoops on owned blocks +system.cpu0.dcache.protocol.snoop_upgrade_shared 725 # upgradee snoops on shared blocks +system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.dcache.protocol.write_invalid 282337 # write misses to invalid blocks +system.cpu0.dcache.protocol.write_owned 2517 # write misses to owned blocks +system.cpu0.dcache.protocol.write_shared 1819 # write misses to shared blocks +system.cpu0.dcache.replacements 1978969 # number of replacements +system.cpu0.dcache.sampled_refs 1979481 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 504.827576 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13115267 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 0 # number of writebacks +system.cpu0.dtb.accesses 698037 # DTB accesses +system.cpu0.dtb.acv 251 # DTB access violations +system.cpu0.dtb.hits 15082969 # DTB hits +system.cpu0.dtb.misses 7805 # DTB misses +system.cpu0.dtb.read_accesses 508987 # DTB read accesses +system.cpu0.dtb.read_acv 152 # DTB read access violations +system.cpu0.dtb.read_hits 9148390 # DTB read hits +system.cpu0.dtb.read_misses 7079 # DTB read misses +system.cpu0.dtb.write_accesses 189050 # DTB write accesses +system.cpu0.dtb.write_acv 99 # DTB write access violations +system.cpu0.dtb.write_hits 5934579 # DTB write hits +system.cpu0.dtb.write_misses 726 # DTB write misses +system.cpu0.icache.ReadReq_accesses 57190172 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 56305300 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.015472 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 884872 # number of ReadReq misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 63.637052 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 57190172 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.demand_hits 56305300 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.015472 # miss rate for demand accesses +system.cpu0.icache.demand_misses 884872 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 57190172 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 56305300 # number of overall hits +system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.015472 # miss rate for overall accesses +system.cpu0.icache.overall_misses 884872 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.icache.protocol.read_invalid 884872 # read misses to invalid blocks +system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.icache.protocol.snoop_read_exclusive 25821 # read snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu0.icache.protocol.snoop_read_shared 13268 # read snoops on shared blocks +system.cpu0.icache.protocol.snoop_readex_exclusive 78 # readEx snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu0.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu0.icache.protocol.snoop_upgrade_shared 6 # upgradee snoops on shared blocks +system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu0.icache.replacements 884276 # number of replacements +system.cpu0.icache.sampled_refs 884788 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 511.244752 # Cycle average of tags in use +system.cpu0.icache.total_refs 56305300 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles +system.cpu0.itb.accesses 3858835 # ITB accesses +system.cpu0.itb.acv 127 # ITB acv +system.cpu0.itb.hits 3855350 # ITB hits +system.cpu0.itb.misses 3485 # ITB misses +system.cpu0.kern.callpal 183272 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 115 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3791 2.07% 2.14% # number of callpals executed -system.cpu0.kern.callpal_tbi 49 0.03% 2.17% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal_swpipl 167832 91.83% 94.01% # number of callpals executed -system.cpu0.kern.callpal_rdps 5780 3.16% 97.17% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed +system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed +system.cpu0.kern.callpal_swpipl 168017 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_wrusp 2 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_rdusp 9 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal_rti 4696 2.57% 99.75% # number of callpals executed -system.cpu0.kern.callpal_callsys 344 0.19% 99.93% # number of callpals executed -system.cpu0.kern.callpal_imb 122 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed +system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 196249 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6184 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174678 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 70736 40.50% 40.50% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 245 0.14% 40.64% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1896 1.09% 41.72% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 8 0.00% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101793 58.27% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 140889 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 69374 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 245 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1896 1.35% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.hwrei 197101 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 174850 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 101695 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 69366 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3718314513 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3683820285 99.07% 99.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 40474 0.00% 99.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 163056 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 2026 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 34288672 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.806564 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1870334889500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1853125118000 99.08% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 17106668000 0.91% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.681442 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1192 -system.cpu0.kern.mode_good_user 1193 +system.cpu0.kern.ipl_used_31 0.684606 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1155 +system.cpu0.kern.mode_good_user 1156 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7143 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1193 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1156 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.286108 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.166877 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.162906 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3716671550 99.96% 99.96% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 1642961 0.04% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1869377889500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 956999000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3792 # number of times the context was actually changed -system.cpu0.kern.syscall 199 # number of syscalls executed -system.cpu0.kern.syscall_2 8 4.02% 4.02% # number of syscalls executed -system.cpu0.kern.syscall_3 17 8.54% 12.56% # number of syscalls executed -system.cpu0.kern.syscall_4 4 2.01% 14.57% # number of syscalls executed -system.cpu0.kern.syscall_6 29 14.57% 29.15% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.50% 29.65% # number of syscalls executed -system.cpu0.kern.syscall_17 4 2.01% 31.66% # number of syscalls executed -system.cpu0.kern.syscall_19 10 5.03% 36.68% # number of syscalls executed -system.cpu0.kern.syscall_20 6 3.02% 39.70% # number of syscalls executed -system.cpu0.kern.syscall_23 1 0.50% 40.20% # number of syscalls executed -system.cpu0.kern.syscall_24 3 1.51% 41.71% # number of syscalls executed -system.cpu0.kern.syscall_33 6 3.02% 44.72% # number of syscalls executed -system.cpu0.kern.syscall_41 2 1.01% 45.73% # number of syscalls executed -system.cpu0.kern.syscall_45 31 15.58% 61.31% # number of syscalls executed -system.cpu0.kern.syscall_47 3 1.51% 62.81% # number of syscalls executed -system.cpu0.kern.syscall_48 10 5.03% 67.84% # number of syscalls executed -system.cpu0.kern.syscall_54 9 4.52% 72.36% # number of syscalls executed -system.cpu0.kern.syscall_59 6 3.02% 75.38% # number of syscalls executed -system.cpu0.kern.syscall_71 20 10.05% 85.43% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.51% 86.93% # number of syscalls executed -system.cpu0.kern.syscall_74 5 2.51% 89.45% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.50% 89.95% # number of syscalls executed -system.cpu0.kern.syscall_90 3 1.51% 91.46% # number of syscalls executed -system.cpu0.kern.syscall_92 8 4.02% 95.48% # number of syscalls executed -system.cpu0.kern.syscall_97 2 1.01% 96.48% # number of syscalls executed -system.cpu0.kern.syscall_98 2 1.01% 97.49% # number of syscalls executed -system.cpu0.kern.syscall_132 1 0.50% 97.99% # number of syscalls executed -system.cpu0.kern.syscall_144 2 1.01% 98.99% # number of syscalls executed -system.cpu0.kern.syscall_147 2 1.01% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015056 # Percentage of non-idle cycles -system.cpu0.numCycles 55984201 # number of cpu cycles simulated -system.cpu0.num_insts 55980548 # Number of instructions executed -system.cpu0.num_refs 15081320 # Number of memory references -system.cpu1.dtb.accesses 761000 # DTB accesses -system.cpu1.dtb.acv 32 # DTB access violations -system.cpu1.dtb.hits 2658022 # DTB hits -system.cpu1.dtb.misses 4173 # DTB misses -system.cpu1.dtb.read_accesses 523552 # DTB read accesses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_hits 1679180 # DTB read hits -system.cpu1.dtb.read_misses 3798 # DTB read misses -system.cpu1.dtb.write_accesses 237448 # DTB write accesses -system.cpu1.dtb.write_acv 32 # DTB write access violations -system.cpu1.dtb.write_hits 978842 # DTB write hits -system.cpu1.dtb.write_misses 375 # DTB write misses -system.cpu1.idle_fraction 0.997592 # Percentage of idle cycles -system.cpu1.itb.accesses 2420426 # ITB accesses -system.cpu1.itb.acv 0 # ITB acv -system.cpu1.itb.hits 2418839 # ITB hits -system.cpu1.itb.misses 1587 # ITB misses -system.cpu1.kern.callpal 34411 # number of callpals executed +system.cpu0.kern.swap_context 3762 # number of times the context was actually changed +system.cpu0.kern.syscall 226 # number of syscalls executed +system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed +system.cpu0.kern.syscall_4 2 0.88% 11.95% # number of syscalls executed +system.cpu0.kern.syscall_6 32 14.16% 26.11% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.44% 26.55% # number of syscalls executed +system.cpu0.kern.syscall_15 1 0.44% 26.99% # number of syscalls executed +system.cpu0.kern.syscall_17 9 3.98% 30.97% # number of syscalls executed +system.cpu0.kern.syscall_19 8 3.54% 34.51% # number of syscalls executed +system.cpu0.kern.syscall_20 6 2.65% 37.17% # number of syscalls executed +system.cpu0.kern.syscall_23 2 0.88% 38.05% # number of syscalls executed +system.cpu0.kern.syscall_24 4 1.77% 39.82% # number of syscalls executed +system.cpu0.kern.syscall_33 7 3.10% 42.92% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.88% 43.81% # number of syscalls executed +system.cpu0.kern.syscall_45 37 16.37% 60.18% # number of syscalls executed +system.cpu0.kern.syscall_47 4 1.77% 61.95% # number of syscalls executed +system.cpu0.kern.syscall_48 8 3.54% 65.49% # number of syscalls executed +system.cpu0.kern.syscall_54 10 4.42% 69.91% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.44% 70.35% # number of syscalls executed +system.cpu0.kern.syscall_59 4 1.77% 72.12% # number of syscalls executed +system.cpu0.kern.syscall_71 30 13.27% 85.40% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.33% 86.73% # number of syscalls executed +system.cpu0.kern.syscall_74 8 3.54% 90.27% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.44% 90.71% # number of syscalls executed +system.cpu0.kern.syscall_90 2 0.88% 91.59% # number of syscalls executed +system.cpu0.kern.syscall_92 9 3.98% 95.58% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.88% 96.46% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.88% 97.35% # number of syscalls executed +system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed +system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles +system.cpu0.numCycles 57193784 # number of cpu cycles simulated +system.cpu0.num_insts 57190172 # Number of instructions executed +system.cpu0.num_refs 15322419 # Number of memory references +system.cpu1.dcache.ReadReq_accesses 1167383 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 1124444 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.036782 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 42939 # number of ReadReq misses +system.cpu1.dcache.WriteReq_accesses 749650 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 723062 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.035467 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 26588 # number of WriteReq misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 1917033 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1847506 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.036268 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 69527 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 1917033 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 1847506 # number of overall hits +system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.036268 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 69527 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.dcache.protocol.read_invalid 42939 # read misses to invalid blocks +system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.dcache.protocol.snoop_read_exclusive 939 # read snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_read_modified 2438 # read snoops on modified blocks +system.cpu1.dcache.protocol.snoop_read_owned 337 # read snoops on owned blocks +system.cpu1.dcache.protocol.snoop_read_shared 61769 # read snoops on shared blocks +system.cpu1.dcache.protocol.snoop_readex_exclusive 103 # readEx snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_readex_modified 275 # readEx snoops on modified blocks +system.cpu1.dcache.protocol.snoop_readex_owned 44 # readEx snoops on owned blocks +system.cpu1.dcache.protocol.snoop_readex_shared 39 # readEx snoops on shared blocks +system.cpu1.dcache.protocol.snoop_upgrade_owned 1538 # upgrade snoops on owned blocks +system.cpu1.dcache.protocol.snoop_upgrade_shared 2755 # upgradee snoops on shared blocks +system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.dcache.protocol.write_invalid 24475 # write misses to invalid blocks +system.cpu1.dcache.protocol.write_owned 641 # write misses to owned blocks +system.cpu1.dcache.protocol.write_shared 1472 # write misses to shared blocks +system.cpu1.dcache.replacements 62341 # number of replacements +system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851266669500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 0 # number of writebacks +system.cpu1.dtb.accesses 323622 # DTB accesses +system.cpu1.dtb.acv 116 # DTB access violations +system.cpu1.dtb.hits 1914885 # DTB hits +system.cpu1.dtb.misses 3692 # DTB misses +system.cpu1.dtb.read_accesses 220342 # DTB read accesses +system.cpu1.dtb.read_acv 58 # DTB read access violations +system.cpu1.dtb.read_hits 1163439 # DTB read hits +system.cpu1.dtb.read_misses 3277 # DTB read misses +system.cpu1.dtb.write_accesses 103280 # DTB write accesses +system.cpu1.dtb.write_acv 58 # DTB write access violations +system.cpu1.dtb.write_hits 751446 # DTB write hits +system.cpu1.dtb.write_misses 415 # DTB write misses +system.cpu1.icache.ReadReq_accesses 5935771 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 5832135 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.017460 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 103636 # number of ReadReq misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 56.289849 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 5935771 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.demand_hits 5832135 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.017460 # miss rate for demand accesses +system.cpu1.icache.demand_misses 103636 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 5935771 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 5832135 # number of overall hits +system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.017460 # miss rate for overall accesses +system.cpu1.icache.overall_misses 103636 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.icache.protocol.read_invalid 103636 # read misses to invalid blocks +system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.icache.protocol.snoop_read_exclusive 17328 # read snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu1.icache.protocol.snoop_read_shared 199395 # read snoops on shared blocks +system.cpu1.icache.protocol.snoop_readex_exclusive 25 # readEx snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks +system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu1.icache.replacements 103097 # number of replacements +system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 427.126314 # Cycle average of tags in use +system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868932665500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles +system.cpu1.itb.accesses 1469938 # ITB accesses +system.cpu1.itb.acv 57 # ITB acv +system.cpu1.itb.hits 1468399 # ITB hits +system.cpu1.itb.misses 1539 # ITB misses +system.cpu1.kern.callpal 32131 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 468 1.36% 1.39% # number of callpals executed -system.cpu1.kern.callpal_tbi 5 0.01% 1.41% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.02% 1.43% # number of callpals executed -system.cpu1.kern.callpal_swpipl 28036 81.47% 82.90% # number of callpals executed -system.cpu1.kern.callpal_rdps 3042 8.84% 91.74% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 91.74% # number of callpals executed -system.cpu1.kern.callpal_wrusp 5 0.01% 91.76% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 91.77% # number of callpals executed -system.cpu1.kern.callpal_rti 2586 7.52% 99.28% # number of callpals executed -system.cpu1.kern.callpal_callsys 187 0.54% 99.83% # number of callpals executed -system.cpu1.kern.callpal_imb 59 0.17% 100.00% # number of callpals executed +system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed +system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed +system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed +system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed +system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed +system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 42215 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2214 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 32633 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 11168 34.22% 34.22% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1895 5.81% 40.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 115 0.35% 40.38% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 19455 59.62% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 24201 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 11153 46.08% 46.08% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1895 7.83% 53.92% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 115 0.48% 54.39% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 11038 45.61% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3717892668 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3695802544 99.41% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 162970 0.00% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 29122 0.00% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 21898032 0.59% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.741611 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.998657 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1870124001500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1859122583000 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.567361 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 602 -system.cpu1.kern.mode_good_user 563 -system.cpu1.kern.mode_good_idle 39 -system.cpu1.kern.mode_switch_kernel 1011 # number of protection mode switches -system.cpu1.kern.mode_switch_user 563 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2045 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.332689 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.595450 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 612 +system.cpu1.kern.mode_good_user 580 +system.cpu1.kern.mode_good_idle 32 +system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches +system.cpu1.kern.mode_switch_user 580 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.019071 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 4872726 0.13% 0.13% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1950903 0.05% 0.18% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3710606044 99.82% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 469 # number of times the context was actually changed -system.cpu1.kern.syscall 130 # number of syscalls executed -system.cpu1.kern.syscall_3 13 10.00% 10.00% # number of syscalls executed -system.cpu1.kern.syscall_6 14 10.77% 20.77% # number of syscalls executed -system.cpu1.kern.syscall_15 1 0.77% 21.54% # number of syscalls executed -system.cpu1.kern.syscall_17 11 8.46% 30.00% # number of syscalls executed -system.cpu1.kern.syscall_23 3 2.31% 32.31% # number of syscalls executed -system.cpu1.kern.syscall_24 3 2.31% 34.62% # number of syscalls executed -system.cpu1.kern.syscall_33 5 3.85% 38.46% # number of syscalls executed -system.cpu1.kern.syscall_45 24 18.46% 56.92% # number of syscalls executed -system.cpu1.kern.syscall_47 3 2.31% 59.23% # number of syscalls executed -system.cpu1.kern.syscall_54 1 0.77% 60.00% # number of syscalls executed -system.cpu1.kern.syscall_58 1 0.77% 60.77% # number of syscalls executed -system.cpu1.kern.syscall_59 1 0.77% 61.54% # number of syscalls executed -system.cpu1.kern.syscall_71 34 26.15% 87.69% # number of syscalls executed -system.cpu1.kern.syscall_74 11 8.46% 96.15% # number of syscalls executed -system.cpu1.kern.syscall_92 2 1.54% 97.69% # number of syscalls executed -system.cpu1.kern.syscall_132 3 2.31% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.002408 # Percentage of non-idle cycles -system.cpu1.numCycles 8953858 # number of cpu cycles simulated -system.cpu1.num_insts 8952271 # Number of instructions executed -system.cpu1.num_refs 2670182 # Number of memory references +system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 1373909500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1868002152500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 471 # number of times the context was actually changed +system.cpu1.kern.syscall 100 # number of syscalls executed +system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed +system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed +system.cpu1.kern.syscall_4 2 2.00% 15.00% # number of syscalls executed +system.cpu1.kern.syscall_6 10 10.00% 25.00% # number of syscalls executed +system.cpu1.kern.syscall_17 6 6.00% 31.00% # number of syscalls executed +system.cpu1.kern.syscall_19 2 2.00% 33.00% # number of syscalls executed +system.cpu1.kern.syscall_23 2 2.00% 35.00% # number of syscalls executed +system.cpu1.kern.syscall_24 2 2.00% 37.00% # number of syscalls executed +system.cpu1.kern.syscall_33 4 4.00% 41.00% # number of syscalls executed +system.cpu1.kern.syscall_45 17 17.00% 58.00% # number of syscalls executed +system.cpu1.kern.syscall_47 2 2.00% 60.00% # number of syscalls executed +system.cpu1.kern.syscall_48 2 2.00% 62.00% # number of syscalls executed +system.cpu1.kern.syscall_59 3 3.00% 65.00% # number of syscalls executed +system.cpu1.kern.syscall_71 24 24.00% 89.00% # number of syscalls executed +system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed +system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed +system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles +system.cpu1.numCycles 5937367 # number of cpu cycles simulated +system.cpu1.num_insts 5935771 # Number of instructions executed +system.cpu1.num_refs 1926645 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. -system.disk0.dma_write_txs 408 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 306245 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits 181107 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate 0.408621 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 125138 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2724155 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1782852 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.345539 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941303 # number of ReadReq misses +system.l2c.Writeback_accesses 427632 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 427632 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.242866 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2724155 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_hits 1782852 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.345539 # miss rate for demand accesses +system.l2c.demand_misses 941303 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3151787 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 2210484 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.298657 # miss rate for overall accesses +system.l2c.overall_misses 941303 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 1000779 # number of replacements +system.l2c.sampled_refs 1066159 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65517.575355 # Cycle average of tags in use +system.l2c.total_refs 2391252 # Total number of references to valid blocks. +system.l2c.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 9a6301977..563ca3160 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,8 +1,5 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... -warn: 195723: Trying to launch CPU number 1! +warn: 97861500: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 1cecd3a25..6afe2cfa0 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:06:16 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -Exiting @ tick 3718314928 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:06:07 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1870335097000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 8cb8b6cbd..791200f9a 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -1,16 +1,12 @@ [root] type=Root children=system -checkpoint= -clock=2000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -25,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -55,13 +56,101 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu.dtb] type=AlphaDTB size=64 +[system.cpu.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu.itb] type=AlphaITB size=48 @@ -69,7 +158,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -88,7 +177,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -110,27 +199,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -170,6 +299,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -179,7 +335,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -190,7 +346,7 @@ type=AlphaConsole cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -205,7 +361,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -215,19 +371,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -272,7 +430,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -288,7 +446,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -304,7 +462,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -320,7 +478,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -336,7 +494,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -352,7 +510,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -368,7 +526,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -384,7 +542,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -400,7 +558,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -416,7 +574,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -432,7 +590,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -448,7 +606,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -464,7 +622,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -480,7 +638,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -496,7 +654,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -512,7 +670,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -528,7 +686,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -544,7 +702,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -560,7 +718,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -577,7 +735,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -585,13 +743,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -635,9 +795,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -648,7 +808,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -666,7 +826,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index ab56c5d90..94cc53f32 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=2000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -14,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=atomic kernel=/dist/m5/system/binaries/vmlinux @@ -30,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -46,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -58,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -81,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -99,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.simple_disk.disk] type=RawDiskImage @@ -114,7 +154,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -129,7 +169,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -144,7 +184,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -159,7 +199,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -174,7 +214,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -189,7 +229,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -197,8 +237,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -244,7 +284,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -260,12 +300,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -280,7 +320,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -295,7 +335,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -303,7 +343,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -318,7 +358,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -333,7 +373,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -348,7 +388,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -363,7 +403,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -378,7 +418,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -393,7 +433,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -408,7 +448,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -423,7 +463,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -441,7 +481,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -482,12 +522,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -496,9 +538,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -515,7 +557,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -530,7 +572,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -538,7 +580,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -553,7 +595,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -604,18 +646,128 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.cpu.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index a10779a99..aaa6c0c86 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,137 +1,366 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1452138 # Simulator instruction rate (inst/s) -host_mem_usage 239532 # Number of bytes of host memory used -host_seconds 42.57 # Real time elapsed on the host -host_tick_rate 85380734 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 61811715 # Number of instructions simulated -sim_seconds 1.817169 # Number of seconds simulated -sim_ticks 3634338452 # Number of ticks simulated -system.cpu.dtb.accesses 1304494 # DTB accesses +host_inst_rate 577751 # Simulator instruction rate (inst/s) +host_mem_usage 244724 # Number of bytes of host memory used +host_seconds 103.86 # Real time elapsed on the host +host_tick_rate 17603359253 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 60007317 # Number of instructions simulated +sim_seconds 1.828355 # Number of seconds simulated +sim_ticks 1828355481500 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 9723333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7984499 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.178831 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1738834 # number of ReadReq misses +system.cpu.dcache.WriteReq_accesses 6349447 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 6045093 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.047934 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 304354 # number of WriteReq misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 6.866570 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 16072780 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.demand_hits 14029592 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127121 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2043188 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 16072780 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 14029592 # number of overall hits +system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127121 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2043188 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.dcache.protocol.read_invalid 1738834 # read misses to invalid blocks +system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_inv_modified 1 # Invalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.dcache.protocol.snoop_read_exclusive 10 # read snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks +system.cpu.dcache.protocol.snoop_read_owned 2 # read snoops on owned blocks +system.cpu.dcache.protocol.snoop_read_shared 124 # read snoops on shared blocks +system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks +system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.dcache.protocol.write_invalid 304342 # write misses to invalid blocks +system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks +system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks +system.cpu.dcache.replacements 2042663 # number of replacements +system.cpu.dcache.sampled_refs 2043175 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use +system.cpu.dcache.total_refs 14029604 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16556949 # DTB hits -system.cpu.dtb.misses 11425 # DTB misses -system.cpu.dtb.read_accesses 900425 # DTB read accesses +system.cpu.dtb.hits 16053818 # DTB hits +system.cpu.dtb.misses 11471 # DTB misses +system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 10041919 # DTB read hits -system.cpu.dtb.read_misses 10280 # DTB read misses -system.cpu.dtb.write_accesses 404069 # DTB write accesses +system.cpu.dtb.read_hits 9703850 # DTB read hits +system.cpu.dtb.read_misses 10329 # DTB read misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6515030 # DTB write hits -system.cpu.dtb.write_misses 1145 # DTB write misses -system.cpu.idle_fraction 0.982991 # Percentage of idle cycles -system.cpu.itb.accesses 5655354 # ITB accesses +system.cpu.dtb.write_hits 6349968 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits 59087263 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 920054 # number of ReadReq misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 64.229545 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.demand_hits 59087263 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses +system.cpu.icache.demand_misses 920054 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 60007317 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 59087263 # number of overall hits +system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses +system.cpu.icache.overall_misses 920054 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.icache.protocol.read_invalid 920054 # read misses to invalid blocks +system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.icache.protocol.snoop_read_exclusive 643 # read snoops on exclusive blocks +system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu.icache.protocol.snoop_read_shared 1039 # read snoops on shared blocks +system.cpu.icache.protocol.snoop_readex_exclusive 105 # readEx snoops on exclusive blocks +system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks +system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.icache.protocol.snoop_upgrade_shared 9 # upgradee snoops on shared blocks +system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu.icache.replacements 919427 # number of replacements +system.cpu.icache.sampled_refs 919939 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use +system.cpu.icache.total_refs 59087263 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0.983588 # Percentage of idle cycles +system.cpu.itb.accesses 4979217 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 5650364 # ITB hits -system.cpu.itb.misses 4990 # ITB misses -system.cpu.kern.callpal 193847 # number of callpals executed +system.cpu.itb.hits 4974211 # ITB hits +system.cpu.itb.misses 5006 # ITB misses +system.cpu.kern.callpal 192139 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4203 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 176756 91.18% 93.38% # number of callpals executed -system.cpu.kern.callpal_rdps 6881 3.55% 96.93% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_rti 5211 2.69% 99.63% # number of callpals executed -system.cpu.kern.callpal_callsys 531 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed +system.cpu.kern.callpal_swpipl 175210 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_rti 5202 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212913 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6275 # number of quiesce instructions executed -system.cpu.kern.ipl_count 184066 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75351 40.94% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 245 0.13% 41.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1853 1.01% 42.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106617 57.92% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 150066 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73984 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 245 0.16% 49.46% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1853 1.23% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73984 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3634338037 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3599646965 99.05% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 40474 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 159358 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 34491240 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.815284 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.981858 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211277 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed +system.cpu.kern.ipl_count 182521 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105598 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1828355274000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087543000 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.693923 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1937 -system.cpu.kern.mode_good_user 1757 -system.cpu.kern.mode_good_idle 180 -system.cpu.kern.mode_switch_kernel 5978 # number of protection mode switches -system.cpu.kern.mode_switch_user 1757 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2102 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.393819 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.324021 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.695543 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1908 +system.cpu.kern.mode_good_user 1737 +system.cpu.kern.mode_good_idle 171 +system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches +system.cpu.kern.mode_switch_user 1737 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.402325 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320780 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.085633 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 54841721 1.51% 1.51% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 3591234 0.10% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3575905080 98.39% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4204 # number of times the context was actually changed -system.cpu.kern.syscall 329 # number of syscalls executed -system.cpu.kern.syscall_2 8 2.43% 2.43% # number of syscalls executed -system.cpu.kern.syscall_3 30 9.12% 11.55% # number of syscalls executed -system.cpu.kern.syscall_4 4 1.22% 12.77% # number of syscalls executed -system.cpu.kern.syscall_6 43 13.07% 25.84% # number of syscalls executed -system.cpu.kern.syscall_12 1 0.30% 26.14% # number of syscalls executed -system.cpu.kern.syscall_15 1 0.30% 26.44% # number of syscalls executed -system.cpu.kern.syscall_17 15 4.56% 31.00% # number of syscalls executed -system.cpu.kern.syscall_19 10 3.04% 34.04% # number of syscalls executed -system.cpu.kern.syscall_20 6 1.82% 35.87% # number of syscalls executed -system.cpu.kern.syscall_23 4 1.22% 37.08% # number of syscalls executed -system.cpu.kern.syscall_24 6 1.82% 38.91% # number of syscalls executed -system.cpu.kern.syscall_33 11 3.34% 42.25% # number of syscalls executed -system.cpu.kern.syscall_41 2 0.61% 42.86% # number of syscalls executed -system.cpu.kern.syscall_45 55 16.72% 59.57% # number of syscalls executed -system.cpu.kern.syscall_47 6 1.82% 61.40% # number of syscalls executed -system.cpu.kern.syscall_48 10 3.04% 64.44% # number of syscalls executed -system.cpu.kern.syscall_54 10 3.04% 67.48% # number of syscalls executed -system.cpu.kern.syscall_58 1 0.30% 67.78% # number of syscalls executed -system.cpu.kern.syscall_59 7 2.13% 69.91% # number of syscalls executed -system.cpu.kern.syscall_71 54 16.41% 86.32% # number of syscalls executed -system.cpu.kern.syscall_73 3 0.91% 87.23% # number of syscalls executed -system.cpu.kern.syscall_74 16 4.86% 92.10% # number of syscalls executed -system.cpu.kern.syscall_87 1 0.30% 92.40% # number of syscalls executed -system.cpu.kern.syscall_90 3 0.91% 93.31% # number of syscalls executed -system.cpu.kern.syscall_92 10 3.04% 96.35% # number of syscalls executed -system.cpu.kern.syscall_97 2 0.61% 96.96% # number of syscalls executed -system.cpu.kern.syscall_98 2 0.61% 97.57% # number of syscalls executed -system.cpu.kern.syscall_132 4 1.22% 98.78% # number of syscalls executed +system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056177500 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.syscall 326 # number of syscalls executed +system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed +system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed +system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed +system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed +system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed +system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed +system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed +system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed +system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed +system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed +system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed +system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed +system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed +system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed +system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed +system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed +system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed +system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed +system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed +system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed +system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed +system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed +system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed +system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed +system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed +system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed +system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed +system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.017009 # Percentage of non-idle cycles -system.cpu.numCycles 61816889 # number of cpu cycles simulated -system.cpu.num_insts 61811715 # Number of instructions executed -system.cpu.num_refs 16805478 # Number of memory references +system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles +system.cpu.numCycles 60012507 # number of cpu cycles simulated +system.cpu.num_insts 60007317 # Number of instructions executed +system.cpu.num_refs 16302129 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. -system.disk0.dma_write_txs 408 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits 187346 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate 0.384423 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 116996 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2658871 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1717827 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.353926 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941044 # number of ReadReq misses +system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 428885 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.205900 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2658871 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_hits 1717827 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.353926 # miss rate for demand accesses +system.l2c.demand_misses 941044 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3087756 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 2146712 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.304766 # miss rate for overall accesses +system.l2c.overall_misses 941044 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 992432 # number of replacements +system.l2c.sampled_refs 1057820 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65517.661064 # Cycle average of tags in use +system.l2c.total_refs 2333445 # Total number of references to valid blocks. +system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 69304a604..072cb6c8c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,6 +1,3 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +Listening for system connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index 631453025..e47b6f226 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:05:33 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Exiting @ tick 3634338452 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:06:07 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1828355481500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 856856ae8..7bcdbdb71 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -1,16 +1,12 @@ [root] type=Root children=system -checkpoint= -clock=2000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -25,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu0] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -53,21 +54,109 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu0.dtb] type=AlphaDTB size=64 +[system.cpu0.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu0.itb] type=AlphaITB size=48 [system.cpu1] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true @@ -85,13 +174,101 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[5] -icache_port=system.membus.port[4] +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu1.dtb] type=AlphaDTB size=64 +[system.cpu1.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu1.itb] type=AlphaITB size=48 @@ -99,7 +276,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -118,7 +295,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -140,27 +317,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -200,6 +417,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -209,7 +453,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -220,7 +464,7 @@ type=AlphaConsole cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -235,7 +479,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -245,19 +489,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -302,7 +548,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -318,7 +564,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -334,7 +580,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -350,7 +596,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -366,7 +612,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -382,7 +628,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -398,7 +644,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -414,7 +660,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -430,7 +676,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -446,7 +692,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -462,7 +708,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -478,7 +724,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -494,7 +740,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -510,7 +756,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -526,7 +772,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -542,7 +788,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -558,7 +804,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -574,7 +820,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -590,7 +836,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -607,7 +853,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -615,13 +861,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -665,9 +913,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -678,7 +926,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -696,7 +944,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index a4dd003e4..68698cf83 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=2000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -14,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=timing kernel=/dist/m5/system/binaries/vmlinux @@ -30,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -46,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -58,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -81,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -99,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.cpu0.itb] type=AlphaITB @@ -124,7 +164,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -132,6 +172,90 @@ function_trace=false function_trace_start=0 // simulate_stalls not specified +[system.cpu0.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.cpu1.itb] type=AlphaITB size=48 @@ -155,7 +279,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -163,6 +287,90 @@ function_trace=false function_trace_start=0 // simulate_stalls not specified +[system.cpu1.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.simple_disk.disk] type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img @@ -176,7 +384,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -191,7 +399,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -206,7 +414,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -221,7 +429,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -236,7 +444,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -251,7 +459,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -259,8 +467,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -291,12 +499,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu0 platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -311,7 +519,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -326,7 +534,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -334,7 +542,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -349,7 +557,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -364,7 +572,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -379,7 +587,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -394,7 +602,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -409,7 +617,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -424,7 +632,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -439,7 +647,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -454,7 +662,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -472,7 +680,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -513,12 +721,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -527,9 +737,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -546,7 +756,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -561,7 +771,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -569,7 +779,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -584,7 +794,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -635,18 +845,44 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index d6bc028f1..83bb77f93 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,196 +1,578 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 359240 # Simulator instruction rate (inst/s) -host_mem_usage 240844 # Number of bytes of host memory used -host_seconds 186.42 # Real time elapsed on the host -host_tick_rate 21297758 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 66968427 # Number of instructions simulated -sim_seconds 1.985132 # Number of seconds simulated -sim_ticks 3970264174 # Number of ticks simulated -system.cpu0.dtb.accesses 1003481 # DTB accesses +host_inst_rate 213082 # Simulator instruction rate (inst/s) +host_mem_usage 203724 # Number of bytes of host memory used +host_seconds 296.83 # Real time elapsed on the host +host_tick_rate 6573231278 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 63248814 # Number of instructions simulated +sim_seconds 1.951129 # Number of seconds simulated +sim_ticks 1951129131000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 9299202 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 13073.177688 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12073.152824 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 7589849 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 22346675500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.183817 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1709353 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 20637280000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.183817 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1709353 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable 6873 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu0.dcache.ReadResp_mshr_uncacheable_latency 841915000 # number of ReadResp MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_accesses 6016348 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 12644.438594 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 11630.972878 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 5727689 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 3649931000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.047979 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 288659 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 3357385000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.047979 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 288659 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable 9698 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu0.dcache.WriteResp_mshr_uncacheable_latency 1186164500 # number of WriteResp MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 6.687909 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 15315550 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 13011.236419 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 13317538 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 25996606500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.130456 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1998012 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 23994665000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.130456 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1998012 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 15315550 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 13011.236419 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 13317538 # number of overall hits +system.cpu0.dcache.overall_miss_latency 25996606500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.130456 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1998012 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 23994665000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.130456 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1998012 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 16571 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.dcache.protocol.read_invalid 1709421 # read misses to invalid blocks +system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.dcache.protocol.snoop_read_exclusive 908 # read snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_read_modified 3762 # read snoops on modified blocks +system.cpu0.dcache.protocol.snoop_read_owned 72 # read snoops on owned blocks +system.cpu0.dcache.protocol.snoop_read_shared 2297 # read snoops on shared blocks +system.cpu0.dcache.protocol.snoop_readex_exclusive 235 # readEx snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_readex_modified 207 # readEx snoops on modified blocks +system.cpu0.dcache.protocol.snoop_readex_owned 15 # readEx snoops on owned blocks +system.cpu0.dcache.protocol.snoop_readex_shared 7 # readEx snoops on shared blocks +system.cpu0.dcache.protocol.snoop_upgrade_owned 1074 # upgrade snoops on owned blocks +system.cpu0.dcache.protocol.snoop_upgrade_shared 726 # upgradee snoops on shared blocks +system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.dcache.protocol.write_invalid 284810 # write misses to invalid blocks +system.cpu0.dcache.protocol.write_owned 2533 # write misses to owned blocks +system.cpu0.dcache.protocol.write_shared 1354 # write misses to shared blocks +system.cpu0.dcache.replacements 1991354 # number of replacements +system.cpu0.dcache.sampled_refs 1991866 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 503.775443 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13321418 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 57953000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 401606 # number of writebacks +system.cpu0.dtb.accesses 719860 # DTB accesses system.cpu0.dtb.acv 289 # DTB access violations -system.cpu0.dtb.hits 13332650 # DTB hits -system.cpu0.dtb.misses 8437 # DTB misses -system.cpu0.dtb.read_accesses 695694 # DTB read accesses +system.cpu0.dtb.hits 15299767 # DTB hits +system.cpu0.dtb.misses 8485 # DTB misses +system.cpu0.dtb.read_accesses 524201 # DTB read accesses system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 8285777 # DTB read hits -system.cpu0.dtb.read_misses 7640 # DTB read misses -system.cpu0.dtb.write_accesses 307787 # DTB write accesses +system.cpu0.dtb.read_hits 9282693 # DTB read hits +system.cpu0.dtb.read_misses 7687 # DTB read misses +system.cpu0.dtb.write_accesses 195659 # DTB write accesses system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 5046873 # DTB write hits -system.cpu0.dtb.write_misses 797 # DTB write misses -system.cpu0.idle_fraction 0.928155 # Percentage of idle cycles -system.cpu0.itb.accesses 4220935 # ITB accesses +system.cpu0.dtb.write_hits 6017074 # DTB write hits +system.cpu0.dtb.write_misses 798 # DTB write misses +system.cpu0.icache.ReadReq_accesses 57872551 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 12029.752588 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11029.000057 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 56957639 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 11006165000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.015809 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 914912 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 10090564500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.015809 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 914912 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 62.632934 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 57872551 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 12029.752588 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency +system.cpu0.icache.demand_hits 56957639 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 11006165000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.015809 # miss rate for demand accesses +system.cpu0.icache.demand_misses 914912 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 10090564500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.015809 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 914912 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 57872551 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 12029.752588 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 56957639 # number of overall hits +system.cpu0.icache.overall_miss_latency 11006165000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.015809 # miss rate for overall accesses +system.cpu0.icache.overall_misses 914912 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 10090564500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.015809 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 914912 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.icache.protocol.read_invalid 915158 # read misses to invalid blocks +system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.icache.protocol.snoop_read_exclusive 4652 # read snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu0.icache.protocol.snoop_read_shared 8768 # read snoops on shared blocks +system.cpu0.icache.protocol.snoop_readex_exclusive 121 # readEx snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu0.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks +system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu0.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks +system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu0.icache.replacements 908876 # number of replacements +system.cpu0.icache.sampled_refs 909388 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 508.806183 # Cycle average of tags in use +system.cpu0.icache.total_refs 56957639 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 34906249000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0.943968 # Percentage of idle cycles +system.cpu0.itb.accesses 3944641 # ITB accesses system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 4217111 # ITB hits -system.cpu0.itb.misses 3824 # ITB misses -system.cpu0.kern.callpal 144637 # number of callpals executed +system.cpu0.itb.hits 3940800 # ITB hits +system.cpu0.itb.misses 3841 # ITB misses +system.cpu0.kern.callpal 187118 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 571 0.39% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_swpctx 2907 2.01% 2.41% # number of callpals executed -system.cpu0.kern.callpal_tbi 44 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.44% # number of callpals executed -system.cpu0.kern.callpal_swpipl 129633 89.63% 92.07% # number of callpals executed -system.cpu0.kern.callpal_rdps 6650 4.60% 96.67% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 96.67% # number of callpals executed -system.cpu0.kern.callpal_wrusp 4 0.00% 96.67% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_rti 4286 2.96% 99.64% # number of callpals executed -system.cpu0.kern.callpal_callsys 372 0.26% 99.90% # number of callpals executed -system.cpu0.kern.callpal_imb 149 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 96 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3865 2.07% 2.12% # number of callpals executed +system.cpu0.kern.callpal_tbi 44 0.02% 2.14% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.15% # number of callpals executed +system.cpu0.kern.callpal_swpipl 171254 91.52% 93.67% # number of callpals executed +system.cpu0.kern.callpal_rdps 6635 3.55% 97.21% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 97.21% # number of callpals executed +system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_rti 4694 2.51% 99.73% # number of callpals executed +system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 159963 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6648 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 136551 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 54497 39.91% 39.91% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 143 0.10% 40.01% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 2005 1.47% 41.48% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 483 0.35% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 79423 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 110306 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 54079 49.03% 49.03% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 143 0.13% 49.16% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 2005 1.82% 50.97% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 483 0.44% 51.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 53596 48.59% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3970262390 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3836377682 96.63% 96.63% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 133000 0.00% 96.63% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1870128 0.05% 96.68% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1206048 0.03% 96.71% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 130675532 3.29% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.807801 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.992330 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 201983 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6162 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 178054 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72322 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1968 1.11% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 6 0.00% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 103627 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 144005 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 70953 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1968 1.37% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 70947 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1951128432000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1894864204500 97.12% 97.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 72482500 0.00% 97.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 564462000 0.03% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 4114000 0.00% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 55623169000 2.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.981071 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.674817 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1253 -system.cpu0.kern.mode_good_user 1254 +system.cpu0.kern.ipl_used_31 0.684638 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1230 +system.cpu0.kern.mode_good_user 1231 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 6799 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1254 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7215 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1231 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.311313 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.184292 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.170478 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3956507378 99.65% 99.65% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 13755004 0.35% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1947973402000 99.84% 99.84% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3155028000 0.16% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2908 # number of times the context was actually changed -system.cpu0.kern.syscall 227 # number of syscalls executed -system.cpu0.kern.syscall_2 6 2.64% 2.64% # number of syscalls executed -system.cpu0.kern.syscall_3 19 8.37% 11.01% # number of syscalls executed -system.cpu0.kern.syscall_4 3 1.32% 12.33% # number of syscalls executed -system.cpu0.kern.syscall_6 31 13.66% 25.99% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.44% 26.43% # number of syscalls executed -system.cpu0.kern.syscall_15 1 0.44% 26.87% # number of syscalls executed -system.cpu0.kern.syscall_17 10 4.41% 31.28% # number of syscalls executed -system.cpu0.kern.syscall_19 6 2.64% 33.92% # number of syscalls executed -system.cpu0.kern.syscall_20 4 1.76% 35.68% # number of syscalls executed -system.cpu0.kern.syscall_23 2 0.88% 36.56% # number of syscalls executed -system.cpu0.kern.syscall_24 4 1.76% 38.33% # number of syscalls executed -system.cpu0.kern.syscall_33 8 3.52% 41.85% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.88% 42.73% # number of syscalls executed -system.cpu0.kern.syscall_45 40 17.62% 60.35% # number of syscalls executed -system.cpu0.kern.syscall_47 4 1.76% 62.11% # number of syscalls executed -system.cpu0.kern.syscall_48 7 3.08% 65.20% # number of syscalls executed -system.cpu0.kern.syscall_54 9 3.96% 69.16% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.44% 69.60% # number of syscalls executed -system.cpu0.kern.syscall_59 5 2.20% 71.81% # number of syscalls executed -system.cpu0.kern.syscall_71 32 14.10% 85.90% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.32% 87.22% # number of syscalls executed -system.cpu0.kern.syscall_74 9 3.96% 91.19% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.44% 91.63% # number of syscalls executed -system.cpu0.kern.syscall_90 2 0.88% 92.51% # number of syscalls executed -system.cpu0.kern.syscall_92 8 3.52% 96.04% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.88% 96.92% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.88% 97.80% # number of syscalls executed -system.cpu0.kern.syscall_132 2 0.88% 98.68% # number of syscalls executed -system.cpu0.kern.syscall_144 1 0.44% 99.12% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.071845 # Percentage of non-idle cycles -system.cpu0.numCycles 3970264174 # number of cpu cycles simulated -system.cpu0.num_insts 52311968 # Number of instructions executed -system.cpu0.num_refs 13564877 # Number of memory references -system.cpu1.dtb.accesses 302962 # DTB accesses +system.cpu0.kern.swap_context 3866 # number of times the context was actually changed +system.cpu0.kern.syscall 224 # number of syscalls executed +system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed +system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed +system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed +system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed +system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed +system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed +system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed +system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed +system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed +system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed +system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed +system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed +system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed +system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed +system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed +system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed +system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed +system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed +system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed +system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed +system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.056032 # Percentage of non-idle cycles +system.cpu0.numCycles 1951129131000 # number of cpu cycles simulated +system.cpu0.num_insts 57872550 # Number of instructions executed +system.cpu0.num_refs 15541096 # Number of memory references +system.cpu1.dcache.ReadReq_accesses 1052558 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 11119.734481 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10119.576119 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 1014670 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 421304500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.035996 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 37888 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 383410500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035996 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 37888 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable 120 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu1.dcache.ReadResp_mshr_uncacheable_latency 14641500 # number of ReadResp MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_accesses 677186 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 11920.138166 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 10843.231096 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 653157 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 286429000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.035484 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 24029 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 260552000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.035484 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 24029 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable 2496 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu1.dcache.WriteResp_mshr_uncacheable_latency 304596500 # number of WriteResp MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 29.876823 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 1729744 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 11430.358383 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1667827 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 707733500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.035795 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 61917 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 643962500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.035795 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 61917 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 1729744 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 11430.358383 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 1667827 # number of overall hits +system.cpu1.dcache.overall_miss_latency 707733500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.035795 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 61917 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 643962500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.035795 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 61917 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 2616 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.dcache.protocol.read_invalid 37951 # read misses to invalid blocks +system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.dcache.protocol.snoop_read_exclusive 906 # read snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_read_modified 1965 # read snoops on modified blocks +system.cpu1.dcache.protocol.snoop_read_owned 254 # read snoops on owned blocks +system.cpu1.dcache.protocol.snoop_read_shared 65869 # read snoops on shared blocks +system.cpu1.dcache.protocol.snoop_readex_exclusive 191 # readEx snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_readex_modified 198 # readEx snoops on modified blocks +system.cpu1.dcache.protocol.snoop_readex_owned 48 # readEx snoops on owned blocks +system.cpu1.dcache.protocol.snoop_readex_shared 42 # readEx snoops on shared blocks +system.cpu1.dcache.protocol.snoop_upgrade_owned 1132 # upgrade snoops on owned blocks +system.cpu1.dcache.protocol.snoop_upgrade_shared 2716 # upgradee snoops on shared blocks +system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.dcache.protocol.write_invalid 22206 # write misses to invalid blocks +system.cpu1.dcache.protocol.write_owned 601 # write misses to owned blocks +system.cpu1.dcache.protocol.write_shared 1247 # write misses to shared blocks +system.cpu1.dcache.replacements 55360 # number of replacements +system.cpu1.dcache.sampled_refs 55749 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 388.749341 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1665603 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1935095598000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 27663 # number of writebacks +system.cpu1.dtb.accesses 302878 # DTB accesses system.cpu1.dtb.acv 84 # DTB access violations -system.cpu1.dtb.hits 4640482 # DTB hits -system.cpu1.dtb.misses 3107 # DTB misses -system.cpu1.dtb.read_accesses 205912 # DTB read accesses +system.cpu1.dtb.hits 1728432 # DTB hits +system.cpu1.dtb.misses 3106 # DTB misses +system.cpu1.dtb.read_accesses 205838 # DTB read accesses system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 2668410 # DTB read hits -system.cpu1.dtb.read_misses 2747 # DTB read misses -system.cpu1.dtb.write_accesses 97050 # DTB write accesses +system.cpu1.dtb.read_hits 1049360 # DTB read hits +system.cpu1.dtb.read_misses 2750 # DTB read misses +system.cpu1.dtb.write_accesses 97040 # DTB write accesses system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_hits 1972072 # DTB write hits -system.cpu1.dtb.write_misses 360 # DTB write misses -system.cpu1.idle_fraction 0.974914 # Percentage of idle cycles -system.cpu1.itb.accesses 1965758 # ITB accesses +system.cpu1.dtb.write_hits 679072 # DTB write hits +system.cpu1.dtb.write_misses 356 # DTB write misses +system.cpu1.icache.ReadReq_accesses 5376264 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 12045.939531 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11045.466957 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 5281041 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 1147050500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.017712 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 95223 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 1051782500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.017712 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 95223 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 57.662729 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 5376264 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 12045.939531 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency +system.cpu1.icache.demand_hits 5281041 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 1147050500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.017712 # miss rate for demand accesses +system.cpu1.icache.demand_misses 95223 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 1051782500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.017712 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 95223 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 5376264 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 12045.939531 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 5281041 # number of overall hits +system.cpu1.icache.overall_miss_latency 1147050500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.017712 # miss rate for overall accesses +system.cpu1.icache.overall_misses 95223 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 1051782500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.017712 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 95223 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.icache.protocol.read_invalid 97341 # read misses to invalid blocks +system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.icache.protocol.snoop_read_exclusive 39627 # read snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu1.icache.protocol.snoop_read_shared 214588 # read snoops on shared blocks +system.cpu1.icache.protocol.snoop_readex_exclusive 26 # readEx snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks +system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu1.icache.replacements 91073 # number of replacements +system.cpu1.icache.sampled_refs 91585 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 420.500398 # Cycle average of tags in use +system.cpu1.icache.total_refs 5281041 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1947911714000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0.995322 # Percentage of idle cycles +system.cpu1.itb.accesses 1399877 # ITB accesses system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 1964511 # ITB hits -system.cpu1.itb.misses 1247 # ITB misses -system.cpu1.kern.callpal 80671 # number of callpals executed +system.cpu1.itb.hits 1398631 # ITB hits +system.cpu1.itb.misses 1246 # ITB misses +system.cpu1.kern.callpal 29847 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 483 0.60% 0.60% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_swpctx 2277 2.82% 3.43% # number of callpals executed -system.cpu1.kern.callpal_tbi 10 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 3.45% # number of callpals executed -system.cpu1.kern.callpal_swpipl 71267 88.34% 91.79% # number of callpals executed -system.cpu1.kern.callpal_rdps 2378 2.95% 94.74% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 94.74% # number of callpals executed -system.cpu1.kern.callpal_wrusp 3 0.00% 94.74% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.00% 94.74% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.00% 94.75% # number of callpals executed -system.cpu1.kern.callpal_rti 4044 5.01% 99.76% # number of callpals executed -system.cpu1.kern.callpal_callsys 161 0.20% 99.96% # number of callpals executed -system.cpu1.kern.callpal_imb 31 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_swpctx 375 1.26% 1.29% # number of callpals executed +system.cpu1.kern.callpal_tbi 10 0.03% 1.32% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.34% # number of callpals executed +system.cpu1.kern.callpal_swpipl 24461 81.95% 83.30% # number of callpals executed +system.cpu1.kern.callpal_rdps 2201 7.37% 90.67% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 90.68% # number of callpals executed +system.cpu1.kern.callpal_wrusp 3 0.01% 90.69% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 90.69% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 90.70% # number of callpals executed +system.cpu1.kern.callpal_rti 2582 8.65% 99.35% # number of callpals executed +system.cpu1.kern.callpal_callsys 161 0.54% 99.89% # number of callpals executed +system.cpu1.kern.callpal_imb 31 0.10% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 87720 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2808 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 77880 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 30262 38.86% 38.86% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1997 2.56% 41.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 571 0.73% 42.15% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 45050 57.85% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 60603 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 29303 48.35% 48.35% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1997 3.30% 51.65% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 571 0.94% 52.59% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 28732 47.41% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3968772136 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3846937158 96.93% 96.93% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1867822 0.05% 96.98% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 1457952 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 118509204 2.99% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.778159 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.968310 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 36385 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2332 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 29103 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 9344 32.11% 32.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1963 6.75% 38.85% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 96 0.33% 39.18% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 17700 60.82% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 20635 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 9336 45.24% 45.24% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1963 9.51% 54.76% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 96 0.47% 55.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 9240 44.78% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1950372731000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1911409272000 98.00% 98.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 494740000 0.03% 98.03% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 52316000 0.00% 98.03% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 38416403000 1.97% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999144 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.637780 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 1014 -system.cpu1.kern.mode_good_user 519 -system.cpu1.kern.mode_good_idle 495 -system.cpu1.kern.mode_switch_kernel 2345 # number of protection mode switches -system.cpu1.kern.mode_switch_user 519 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 3028 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.344196 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.432409 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.522034 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 538 +system.cpu1.kern.mode_good_user 517 +system.cpu1.kern.mode_good_idle 21 +system.cpu1.kern.mode_switch_kernel 884 # number of protection mode switches +system.cpu1.kern.mode_switch_user 517 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2075 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.618718 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.608597 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.163474 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 63257834 1.59% 1.59% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 5106070 0.13% 1.72% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3899443084 98.28% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2278 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good_idle 0.010120 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 3563216000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1513259000 0.08% 0.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1945257297000 99.74% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 376 # number of times the context was actually changed system.cpu1.kern.syscall 102 # number of syscalls executed system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed @@ -213,28 +595,113 @@ system.cpu1.kern.syscall_90 1 0.98% 95.10% # nu system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.025086 # Percentage of non-idle cycles -system.cpu1.numCycles 3968772376 # number of cpu cycles simulated -system.cpu1.num_insts 14656459 # Number of instructions executed -system.cpu1.num_refs 4670067 # Number of memory references +system.cpu1.not_idle_fraction 0.004678 # Percentage of non-idle cycles +system.cpu1.numCycles 1950372761000 # number of cpu cycles simulated +system.cpu1.num_insts 5376264 # Number of instructions executed +system.cpu1.num_refs 1738417 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. -system.disk0.dma_write_txs 408 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 306499 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 12998.029396 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 10997.988681 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 183694 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 1596223000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.400670 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 122805 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 1350608000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.400670 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 122805 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2751323 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 12999.901707 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 10999.990968 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 1810263 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 12233687500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.342039 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941060 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 10351530500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.342035 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 941049 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 6993 # number of ReadReq MSHR uncacheable +system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.l2c.ReadResp_mshr_uncacheable_latency 779629500 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 12194 # number of WriteReq MSHR uncacheable +system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.l2c.WriteResp_mshr_uncacheable_latency 1356619000 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 429269 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 429256 # number of Writeback hits +system.l2c.Writeback_miss_rate 0.000030 # miss rate for Writeback accesses +system.l2c.Writeback_misses 13 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 0.000030 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 13 # number of Writeback MSHR misses +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.277768 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2751323 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 12999.901707 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency +system.l2c.demand_hits 1810263 # number of demand (read+write) hits +system.l2c.demand_miss_latency 12233687500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.342039 # miss rate for demand accesses +system.l2c.demand_misses 941060 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 10351530500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.342035 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 941049 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3180592 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 12999.722126 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.l2c.overall_hits 2239519 # number of overall hits +system.l2c.overall_miss_latency 12233687500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.295880 # miss rate for overall accesses +system.l2c.overall_misses 941073 # number of overall misses +system.l2c.overall_mshr_hits 11 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 10351530500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.295872 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 941049 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 19187 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 998318 # number of replacements +system.l2c.sampled_refs 1063854 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65469.787238 # Cycle average of tags in use +system.l2c.total_refs 2423213 # Total number of references to valid blocks. +system.l2c.warmup_cycle 3064127000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 79556 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index 5b02d9b91..dc84ff88b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,8 +1,5 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... -warn: 1082476: Trying to launch CPU number 1! +warn: 423901000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 9c25032e4..a3bd937f6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:09:33 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -Exiting @ tick 3970264174 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:07:53 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1951129131000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 6f48977b0..ded525737 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -1,16 +1,12 @@ [root] type=Root children=system -checkpoint= -clock=2000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -25,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -53,13 +54,101 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu.dtb] type=AlphaDTB size=64 +[system.cpu.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu.itb] type=AlphaITB size=48 @@ -67,7 +156,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -86,7 +175,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -108,27 +197,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -168,6 +297,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -177,7 +333,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -188,7 +344,7 @@ type=AlphaConsole cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -203,7 +359,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -213,19 +369,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -270,7 +428,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -286,7 +444,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -302,7 +460,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -318,7 +476,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -334,7 +492,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -350,7 +508,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -366,7 +524,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -382,7 +540,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -398,7 +556,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -414,7 +572,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -430,7 +588,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -446,7 +604,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -462,7 +620,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -478,7 +636,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -494,7 +652,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -510,7 +668,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -526,7 +684,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -542,7 +700,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -558,7 +716,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -575,7 +733,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -583,13 +741,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -633,9 +793,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -646,7 +806,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -664,7 +824,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index a99b59ae7..b51eb234e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=2000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -14,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=timing kernel=/dist/m5/system/binaries/vmlinux @@ -30,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -46,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -58,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -81,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -99,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.simple_disk.disk] type=RawDiskImage @@ -114,7 +154,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -129,7 +169,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -144,7 +184,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -159,7 +199,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -174,7 +214,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -189,7 +229,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -197,8 +237,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -244,7 +284,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -260,12 +300,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -280,7 +320,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -295,7 +335,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -303,7 +343,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -318,7 +358,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -333,7 +373,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -348,7 +388,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -363,7 +403,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -378,7 +418,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -393,7 +433,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -408,7 +448,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -423,7 +463,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -441,7 +481,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -482,12 +522,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -496,9 +538,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -515,7 +557,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -530,7 +572,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -538,7 +580,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -553,7 +595,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -604,18 +646,128 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.cpu.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 75746eadf..d9f42b16b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,137 +1,408 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 469266 # Simulator instruction rate (inst/s) -host_mem_usage 238376 # Number of bytes of host memory used -host_seconds 131.89 # Real time elapsed on the host -host_tick_rate 29380471 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 61893104 # Number of instructions simulated -sim_seconds 1.937550 # Number of seconds simulated -sim_ticks 3875100962 # Number of ticks simulated -system.cpu.dtb.accesses 1304554 # DTB accesses +host_inst_rate 212380 # Simulator instruction rate (inst/s) +host_mem_usage 201984 # Number of bytes of host memory used +host_seconds 282.69 # Real time elapsed on the host +host_tick_rate 6746442466 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 60037406 # Number of instructions simulated +sim_seconds 1.907146 # Number of seconds simulated +sim_ticks 1907146437000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 9726331 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13065.219101 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12065.192690 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7984648 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 22755470000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.179069 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1741683 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 21013741000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.179069 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1741683 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu.dcache.ReadResp_mshr_uncacheable_latency 824099000 # number of ReadResp MSHR uncacheable cycles +system.cpu.dcache.WriteReq_accesses 6350552 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 12768.106941 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11768.067509 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6046235 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3885552000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.047920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 304317 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3581223000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.047920 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 304317 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu.dcache.WriteResp_mshr_uncacheable_latency 1154484000 # number of WriteResp MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 6.857760 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 16076883 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13021.027370 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency +system.cpu.dcache.demand_hits 14030883 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26641022000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127263 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2046000 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 24594964000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.127263 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2046000 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 16076883 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13021.027370 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 14030883 # number of overall hits +system.cpu.dcache.overall_miss_latency 26641022000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127263 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2046000 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 24594964000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.127263 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2046000 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.dcache.protocol.read_invalid 1741683 # read misses to invalid blocks +system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.dcache.protocol.snoop_read_exclusive 9 # read snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks +system.cpu.dcache.protocol.snoop_read_owned 4 # read snoops on owned blocks +system.cpu.dcache.protocol.snoop_read_shared 92 # read snoops on shared blocks +system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks +system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.dcache.protocol.write_invalid 304305 # write misses to invalid blocks +system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks +system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks +system.cpu.dcache.replacements 2045476 # number of replacements +system.cpu.dcache.sampled_refs 2045988 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.987904 # Cycle average of tags in use +system.cpu.dcache.total_refs 14030895 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 57945000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 429989 # number of writebacks +system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16571487 # DTB hits -system.cpu.dtb.misses 11447 # DTB misses -system.cpu.dtb.read_accesses 900486 # DTB read accesses +system.cpu.dtb.hits 16057425 # DTB hits +system.cpu.dtb.misses 11471 # DTB misses +system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 10051940 # DTB read hits -system.cpu.dtb.read_misses 10303 # DTB read misses -system.cpu.dtb.write_accesses 404068 # DTB write accesses +system.cpu.dtb.read_hits 9706740 # DTB read hits +system.cpu.dtb.read_misses 10329 # DTB read misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6519547 # DTB write hits -system.cpu.dtb.write_misses 1144 # DTB write misses -system.cpu.idle_fraction 0.918919 # Percentage of idle cycles -system.cpu.itb.accesses 5664253 # ITB accesses +system.cpu.dtb.write_hits 6350685 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.icache.ReadReq_accesses 60037407 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 12029.456206 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11028.713640 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 59110217 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 11153591500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.015444 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 927190 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10225713000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.015444 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 927190 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 63.763003 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 60037407 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 12029.456206 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency +system.cpu.icache.demand_hits 59110217 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 11153591500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015444 # miss rate for demand accesses +system.cpu.icache.demand_misses 927190 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10225713000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.015444 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 927190 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 60037407 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 12029.456206 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 59110217 # number of overall hits +system.cpu.icache.overall_miss_latency 11153591500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015444 # miss rate for overall accesses +system.cpu.icache.overall_misses 927190 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10225713000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.015444 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 927190 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.icache.protocol.read_invalid 927190 # read misses to invalid blocks +system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.icache.protocol.snoop_read_exclusive 644 # read snoops on exclusive blocks +system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu.icache.protocol.snoop_read_shared 1040 # read snoops on shared blocks +system.cpu.icache.protocol.snoop_readex_exclusive 146 # readEx snoops on exclusive blocks +system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.icache.protocol.snoop_readex_shared 2 # readEx snoops on shared blocks +system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks +system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu.icache.replacements 926519 # number of replacements +system.cpu.icache.sampled_refs 927030 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 508.761542 # Cycle average of tags in use +system.cpu.icache.total_refs 59110217 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 34634685000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0.940784 # Percentage of idle cycles +system.cpu.itb.accesses 4977586 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 5659250 # ITB hits -system.cpu.itb.misses 5003 # ITB misses -system.cpu.kern.callpal 195265 # number of callpals executed +system.cpu.itb.hits 4972580 # ITB hits +system.cpu.itb.misses 5006 # ITB misses +system.cpu.kern.callpal 192752 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4161 2.13% 2.13% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.16% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.16% # number of callpals executed -system.cpu.kern.callpal_swpipl 178117 91.22% 93.38% # number of callpals executed -system.cpu.kern.callpal_rdps 6978 3.57% 96.96% # number of callpals executed +system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal_swpipl 175824 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal_rdps 6824 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal_rti 5213 2.67% 99.64% # number of callpals executed -system.cpu.kern.callpal_callsys 531 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_rti 5148 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 214368 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6180 # number of quiesce instructions executed -system.cpu.kern.ipl_count 185431 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75630 40.79% 40.79% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 143 0.08% 40.86% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1957 1.06% 41.92% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 107701 58.08% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 150626 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 74263 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 143 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1957 1.30% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 74263 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3875099178 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3747191842 96.70% 96.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 122728 0.00% 96.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 915876 0.02% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 126868732 3.27% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.812302 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.981925 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211836 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6181 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183027 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74862 40.90% 40.90% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 131 0.07% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1923 1.05% 42.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106111 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149044 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73495 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1923 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73495 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1907145727000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1851261210000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 73754500 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 531976500 0.03% 97.10% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 55278786000 2.90% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981740 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.689529 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1926 -system.cpu.kern.mode_good_user 1765 -system.cpu.kern.mode_good_idle 161 -system.cpu.kern.mode_switch_kernel 5968 # number of protection mode switches -system.cpu.kern.mode_switch_user 1765 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2072 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.392861 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.322721 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.692624 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1910 +system.cpu.kern.mode_good_user 1740 +system.cpu.kern.mode_good_idle 170 +system.cpu.kern.mode_switch_kernel 5894 # number of protection mode switches +system.cpu.kern.mode_switch_user 1740 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.405165 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.324058 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.077703 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 118484404 3.06% 3.06% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 18744972 0.48% 3.54% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3737869794 96.46% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4162 # number of times the context was actually changed -system.cpu.kern.syscall 329 # number of syscalls executed -system.cpu.kern.syscall_2 8 2.43% 2.43% # number of syscalls executed -system.cpu.kern.syscall_3 30 9.12% 11.55% # number of syscalls executed -system.cpu.kern.syscall_4 4 1.22% 12.77% # number of syscalls executed -system.cpu.kern.syscall_6 43 13.07% 25.84% # number of syscalls executed -system.cpu.kern.syscall_12 1 0.30% 26.14% # number of syscalls executed -system.cpu.kern.syscall_15 1 0.30% 26.44% # number of syscalls executed -system.cpu.kern.syscall_17 15 4.56% 31.00% # number of syscalls executed -system.cpu.kern.syscall_19 10 3.04% 34.04% # number of syscalls executed -system.cpu.kern.syscall_20 6 1.82% 35.87% # number of syscalls executed -system.cpu.kern.syscall_23 4 1.22% 37.08% # number of syscalls executed -system.cpu.kern.syscall_24 6 1.82% 38.91% # number of syscalls executed -system.cpu.kern.syscall_33 11 3.34% 42.25% # number of syscalls executed -system.cpu.kern.syscall_41 2 0.61% 42.86% # number of syscalls executed -system.cpu.kern.syscall_45 55 16.72% 59.57% # number of syscalls executed -system.cpu.kern.syscall_47 6 1.82% 61.40% # number of syscalls executed -system.cpu.kern.syscall_48 10 3.04% 64.44% # number of syscalls executed -system.cpu.kern.syscall_54 10 3.04% 67.48% # number of syscalls executed -system.cpu.kern.syscall_58 1 0.30% 67.78% # number of syscalls executed -system.cpu.kern.syscall_59 7 2.13% 69.91% # number of syscalls executed -system.cpu.kern.syscall_71 54 16.41% 86.32% # number of syscalls executed -system.cpu.kern.syscall_73 3 0.91% 87.23% # number of syscalls executed -system.cpu.kern.syscall_74 16 4.86% 92.10% # number of syscalls executed -system.cpu.kern.syscall_87 1 0.30% 92.40% # number of syscalls executed -system.cpu.kern.syscall_90 3 0.91% 93.31% # number of syscalls executed -system.cpu.kern.syscall_92 10 3.04% 96.35% # number of syscalls executed -system.cpu.kern.syscall_97 2 0.61% 96.96% # number of syscalls executed -system.cpu.kern.syscall_98 2 0.61% 97.57% # number of syscalls executed -system.cpu.kern.syscall_132 4 1.22% 98.78% # number of syscalls executed +system.cpu.kern.mode_switch_good_idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 42657550000 2.24% 2.24% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 4648649000 0.24% 2.48% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1859839526000 97.52% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.kern.syscall 326 # number of syscalls executed +system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed +system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed +system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed +system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed +system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed +system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed +system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed +system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed +system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed +system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed +system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed +system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed +system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed +system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed +system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed +system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed +system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed +system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed +system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed +system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed +system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed +system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed +system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed +system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed +system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed +system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed +system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed +system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.081081 # Percentage of non-idle cycles -system.cpu.numCycles 3875100962 # number of cpu cycles simulated -system.cpu.num_insts 61893104 # Number of instructions executed -system.cpu.num_refs 16819569 # Number of memory references +system.cpu.not_idle_fraction 0.059216 # Percentage of non-idle cycles +system.cpu.numCycles 1907146437000 # number of cpu cycles simulated +system.cpu.num_insts 60037406 # Number of instructions executed +system.cpu.num_refs 16305563 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. -system.disk0.dma_write_txs 408 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 304305 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 13000.153945 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 11000.153945 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 187380 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 1520043000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.384236 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 116925 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 1286193000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.384236 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 116925 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2668854 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 13000.065889 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 11000.065889 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 1727874 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 12232802000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.352578 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 940980 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 10350842000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.352578 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 940980 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable +system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.l2c.ReadResp_mshr_uncacheable_latency 750102000 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable +system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.l2c.WriteResp_mshr_uncacheable_latency 1050666000 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 429989 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 429989 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.216875 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2668854 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 13000.065889 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency +system.l2c.demand_hits 1727874 # number of demand (read+write) hits +system.l2c.demand_miss_latency 12232802000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.352578 # miss rate for demand accesses +system.l2c.demand_misses 940980 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 10350842000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.352578 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 940980 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3098843 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 13000.065889 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.l2c.overall_hits 2157863 # number of overall hits +system.l2c.overall_miss_latency 12232802000 # number of overall miss cycles +system.l2c.overall_miss_rate 0.303655 # miss rate for overall accesses +system.l2c.overall_misses 940980 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 10350842000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.303655 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 940980 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 992369 # number of replacements +system.l2c.sampled_refs 1057905 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65468.856552 # Cycle average of tags in use +system.l2c.total_refs 2345243 # Total number of references to valid blocks. +system.l2c.warmup_cycle 3045832000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 74072 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 69304a604..072cb6c8c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,6 +1,3 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +Listening for system connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 206c366c1..b8196fe27 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:07:20 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing -Exiting @ tick 3875100962 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:07:53 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1907146437000 because m5_exit instruction encountered |