diff options
| author | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
| commit | 8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch) | |
| tree | 8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/quick/10.linux-boot/ref/alpha | |
| parent | 63371c86648ed65a453a95aec80f326f15a9666d (diff) | |
| download | gem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz | |
tests: update stats for name changes
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha')
12 files changed, 75 insertions, 59 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 1712ae4de..b9ee6d3dc 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -81,6 +81,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -116,6 +117,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -188,6 +190,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -223,6 +226,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -319,6 +323,7 @@ assoc=8 block_size=64 forward_snoops=false hash_delay=1 +is_top_level=true latency=50000 max_miss_count=0 mshrs=20 @@ -350,6 +355,7 @@ assoc=8 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=92 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index dcb0b4c2e..9887f002f 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:46:17 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:46:32 -M5 executing on burrito +M5 compiled Apr 19 2011 12:17:36 +M5 started Apr 19 2011 12:18:19 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 55bb5b9bd..b94a40430 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1669061 # Simulator instruction rate (inst/s) -host_mem_usage 312244 # Number of bytes of host memory used -host_seconds 37.84 # Real time elapsed on the host -host_tick_rate 49429698361 # Simulator tick rate (ticks/s) +host_inst_rate 4662508 # Simulator instruction rate (inst/s) +host_mem_usage 292496 # Number of bytes of host memory used +host_seconds 13.55 # Real time elapsed on the host +host_tick_rate 138080405600 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated @@ -70,8 +70,8 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.985990 # Average percentage of cache occupancy system.cpu0.dcache.occ_blocks::0 504.827058 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.985990 # Average percentage of cache occupancy system.cpu0.dcache.overall_accesses::0 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses @@ -162,8 +162,8 @@ system.cpu0.icache.demand_mshr_misses 0 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.998525 # Average percentage of cache occupancy system.cpu0.icache.occ_blocks::0 511.244754 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.998525 # Average percentage of cache occupancy system.cpu0.icache.overall_accesses::0 57230132 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses @@ -385,8 +385,8 @@ system.cpu1.dcache.demand_mshr_misses 0 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.765530 # Average percentage of cache occupancy system.cpu1.dcache.occ_blocks::0 391.951263 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.765530 # Average percentage of cache occupancy system.cpu1.dcache.overall_accesses::0 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses @@ -477,8 +477,8 @@ system.cpu1.icache.demand_mshr_misses 0 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.834231 # Average percentage of cache occupancy system.cpu1.icache.occ_blocks::0 427.126317 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.834231 # Average percentage of cache occupancy system.cpu1.icache.overall_accesses::0 5935766 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses @@ -677,8 +677,8 @@ system.iocache.demand_mshr_misses 0 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.027215 # Average percentage of cache occupancy system.iocache.occ_blocks::1 0.435437 # Average occupied blocks per context +system.iocache.occ_percent::1 0.027215 # Average percentage of cache occupancy system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses @@ -800,12 +800,12 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.152888 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.004061 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.363646 # Average percentage of cache occupancy system.l2c.occ_blocks::0 10019.673951 # Average occupied blocks per context system.l2c.occ_blocks::1 266.115685 # Average occupied blocks per context system.l2c.occ_blocks::2 23831.931773 # Average occupied blocks per context +system.l2c.occ_percent::0 0.152888 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.004061 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.363646 # Average percentage of cache occupancy system.l2c.overall_accesses::0 2859320 # number of overall (read+write) accesses system.l2c.overall_accesses::1 165593 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 6d9c221c4..ffa9d4df6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -81,6 +81,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -116,6 +117,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -212,6 +214,7 @@ assoc=8 block_size=64 forward_snoops=false hash_delay=1 +is_top_level=true latency=50000 max_miss_count=0 mshrs=20 @@ -243,6 +246,7 @@ assoc=8 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=92 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 644d4ca07..01b553cc1 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:46:17 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:46:32 -M5 executing on burrito +M5 compiled Apr 19 2011 12:17:36 +M5 started Apr 19 2011 12:18:17 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 3b6776214..85848a462 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1616180 # Simulator instruction rate (inst/s) -host_mem_usage 311108 # Number of bytes of host memory used -host_seconds 37.15 # Real time elapsed on the host -host_tick_rate 49243802130 # Simulator tick rate (ticks/s) +host_inst_rate 4724073 # Simulator instruction rate (inst/s) +host_mem_usage 291084 # Number of bytes of host memory used +host_seconds 12.71 # Real time elapsed on the host +host_tick_rate 143937379014 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated @@ -67,8 +67,8 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 511.997802 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999996 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses::0 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses @@ -159,8 +159,8 @@ system.cpu.icache.demand_mshr_misses 0 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.998467 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 511.215243 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.998467 # Average percentage of cache occupancy system.cpu.icache.overall_accesses::0 60050143 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses @@ -371,8 +371,8 @@ system.iocache.demand_mshr_misses 0 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.076598 # Average percentage of cache occupancy system.iocache.occ_blocks::1 1.225570 # Average occupied blocks per context +system.iocache.occ_percent::1 0.076598 # Average percentage of cache occupancy system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses @@ -465,10 +465,10 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.155542 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.360312 # Average percentage of cache occupancy system.l2c.occ_blocks::0 10193.605493 # Average occupied blocks per context system.l2c.occ_blocks::1 23613.410409 # Average occupied blocks per context +system.l2c.occ_percent::0 0.155542 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.360312 # Average percentage of cache occupancy system.l2c.overall_accesses::0 2963266 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 41a7379e1..8d055ed5f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -78,6 +78,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -113,6 +114,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -182,6 +184,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -217,6 +220,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -313,6 +317,7 @@ assoc=8 block_size=64 forward_snoops=false hash_delay=1 +is_top_level=true latency=50000 max_miss_count=0 mshrs=20 @@ -344,6 +349,7 @@ assoc=8 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=92 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 8f8e92a25..a027f13fc 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:46:17 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:46:32 -M5 executing on burrito +M5 compiled Apr 19 2011 12:17:36 +M5 started Apr 19 2011 12:17:43 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 6e0648c43..58de64347 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 901052 # Simulator instruction rate (inst/s) -host_mem_usage 309020 # Number of bytes of host memory used -host_seconds 65.87 # Real time elapsed on the host -host_tick_rate 29733229075 # Simulator tick rate (ticks/s) +host_inst_rate 2296983 # Simulator instruction rate (inst/s) +host_mem_usage 289272 # Number of bytes of host memory used +host_seconds 25.84 # Real time elapsed on the host +host_tick_rate 75796433096 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59355643 # Number of instructions simulated sim_seconds 1.958647 # Number of seconds simulated @@ -114,10 +114,10 @@ system.cpu0.dcache.demand_mshr_misses 1327637 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.983447 # Average percentage of cache occupancy -system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy system.cpu0.dcache.occ_blocks::0 503.524900 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.983447 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy system.cpu0.dcache.overall_accesses::0 14308776 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses @@ -218,8 +218,8 @@ system.cpu0.icache.demand_mshr_misses 915781 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.993751 # Average percentage of cache occupancy system.cpu0.icache.occ_blocks::0 508.800486 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.993751 # Average percentage of cache occupancy system.cpu0.icache.overall_accesses::0 54081252 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses @@ -484,8 +484,8 @@ system.cpu1.dcache.demand_mshr_misses 57534 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.760784 # Average percentage of cache occupancy system.cpu1.dcache.occ_blocks::0 389.521271 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.760784 # Average percentage of cache occupancy system.cpu1.dcache.overall_accesses::0 1677594 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses @@ -586,8 +586,8 @@ system.cpu1.icache.demand_mshr_misses 87005 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.819937 # Average percentage of cache occupancy system.cpu1.icache.occ_blocks::0 419.807616 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.819937 # Average percentage of cache occupancy system.cpu1.icache.overall_accesses::0 5286354 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses @@ -801,8 +801,8 @@ system.iocache.demand_mshr_misses 41726 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.035233 # Average percentage of cache occupancy system.iocache.occ_blocks::1 0.563721 # Average occupied blocks per context +system.iocache.occ_percent::1 0.035233 # Average percentage of cache occupancy system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses @@ -977,12 +977,12 @@ system.l2c.demand_mshr_misses 428511 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.165831 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.003052 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.357359 # Average percentage of cache occupancy system.l2c.occ_blocks::0 10867.929163 # Average occupied blocks per context system.l2c.occ_blocks::1 199.983935 # Average occupied blocks per context system.l2c.occ_blocks::2 23419.887612 # Average occupied blocks per context +system.l2c.occ_percent::0 0.165831 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.003052 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.357359 # Average percentage of cache occupancy system.l2c.overall_accesses::0 2250056 # number of overall (read+write) accesses system.l2c.overall_accesses::1 139909 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index f28d4e037..80db30395 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -78,6 +78,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -113,6 +114,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -209,6 +211,7 @@ assoc=8 block_size=64 forward_snoops=false hash_delay=1 +is_top_level=true latency=50000 max_miss_count=0 mshrs=20 @@ -240,6 +243,7 @@ assoc=8 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=92 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index be2bcef8d..aee40b816 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:46:17 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:46:32 -M5 executing on burrito +M5 compiled Apr 19 2011 12:17:36 +M5 started Apr 19 2011 12:17:43 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 5f1750494..397168bed 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1077887 # Simulator instruction rate (inst/s) -host_mem_usage 307624 # Number of bytes of host memory used -host_seconds 52.08 # Real time elapsed on the host -host_tick_rate 36780244064 # Simulator tick rate (ticks/s) +host_inst_rate 2410973 # Simulator instruction rate (inst/s) +host_mem_usage 287860 # Number of bytes of host memory used +host_seconds 23.28 # Real time elapsed on the host +host_tick_rate 82268225536 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56137087 # Number of instructions simulated sim_seconds 1.915549 # Number of seconds simulated @@ -101,8 +101,8 @@ system.cpu.dcache.demand_mshr_misses 1373445 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999969 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 511.984023 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999969 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses::0 15029535 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses @@ -203,8 +203,8 @@ system.cpu.icache.demand_mshr_misses 928354 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.993597 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 508.721464 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.993597 # Average percentage of cache occupancy system.cpu.icache.overall_accesses::0 56148907 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses @@ -435,8 +435,8 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.083770 # Average percentage of cache occupancy system.iocache.occ_blocks::1 1.340325 # Average occupied blocks per context +system.iocache.occ_percent::1 0.083770 # Average percentage of cache occupancy system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses @@ -563,10 +563,10 @@ system.l2c.demand_mshr_misses 422432 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.171530 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.352641 # Average percentage of cache occupancy system.l2c.occ_blocks::0 11241.373247 # Average occupied blocks per context system.l2c.occ_blocks::1 23110.665097 # Average occupied blocks per context +system.l2c.occ_percent::0 0.171530 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.352641 # Average percentage of cache occupancy system.l2c.overall_accesses::0 2318771 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses |