diff options
| author | Steve Reinhardt <stever@gmail.com> | 2008-08-03 18:13:29 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2008-08-03 18:13:29 -0400 |
| commit | 62c08a75ad18fda5d06d919db6d8d31a79be9630 (patch) | |
| tree | 739253709735d1a8b5da963d2230a5418779d297 /tests/quick/10.linux-boot/ref/alpha | |
| parent | b179c3f4cd1e89872de34d70105f703e72377029 (diff) | |
| download | gem5-62c08a75ad18fda5d06d919db6d8d31a79be9630.tar.xz | |
Make default PhysicalMemory latency slightly more realistic.
Also update stats to reflect change.
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha')
18 files changed, 913 insertions, 911 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index ecab1a9a6..e57480396 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -411,7 +411,7 @@ pio=system.membus.default [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index df1b8566f..af3c5730d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1110947 # Simulator instruction rate (inst/s) -host_mem_usage 261416 # Number of bytes of host memory used -host_seconds 56.81 # Real time elapsed on the host -host_tick_rate 32921847339 # Simulator tick rate (ticks/s) +host_inst_rate 4441196 # Simulator instruction rate (inst/s) +host_mem_usage 289900 # Number of bytes of host memory used +host_seconds 14.21 # Real time elapsed on the host +host_tick_rate 131610473505 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 63114046 # Number of instructions simulated -sim_seconds 1.870335 # Number of seconds simulated -sim_ticks 1870335151500 # Number of ticks simulated +sim_insts 63113507 # Number of instructions simulated +sim_seconds 1.870336 # Number of seconds simulated +sim_ticks 1870335522500 # Number of ticks simulated system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses -system.cpu0.dcache.ReadReq_accesses 8975647 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 7292074 # number of ReadReq hits +system.cpu0.dcache.ReadReq_accesses 8975619 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7292050 # number of ReadReq hits system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1683573 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses 1683569 # number of ReadReq misses system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses -system.cpu0.dcache.WriteReq_accesses 5746071 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 5372265 # number of WriteReq hits +system.cpu0.dcache.WriteReq_accesses 5746054 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5372248 # number of WriteReq hits system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.625595 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 6.625587 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14721718 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses 14721673 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12664339 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits 12664298 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2057379 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses 2057375 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -46,14 +46,14 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14721718 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses 14721673 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12664339 # number of overall hits +system.cpu0.dcache.overall_hits 12664298 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2057379 # number of overall misses +system.cpu0.dcache.overall_misses 2057375 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -69,44 +69,44 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1978971 # number of replacements -system.cpu0.dcache.sampled_refs 1979483 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1978967 # number of replacements +system.cpu0.dcache.sampled_refs 1979479 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 504.827578 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13115252 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 504.827685 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13115211 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 396793 # number of writebacks system.cpu0.dtb.accesses 698037 # DTB accesses system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15082956 # DTB hits +system.cpu0.dtb.hits 15082911 # DTB hits system.cpu0.dtb.misses 7805 # DTB misses system.cpu0.dtb.read_accesses 508987 # DTB read accesses system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_hits 9148379 # DTB read hits +system.cpu0.dtb.read_hits 9148351 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.write_accesses 189050 # DTB write accesses system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_hits 5934577 # DTB write hits +system.cpu0.dtb.write_hits 5934560 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57190139 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_hits 56305276 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_rate 0.015472 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 884863 # number of ReadReq misses +system.cpu0.icache.ReadReq_accesses 57189605 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 56304737 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.015473 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 884868 # number of ReadReq misses system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 63.637672 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 63.636703 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57190139 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses 57189605 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.icache.demand_hits 56305276 # number of demand (read+write) hits +system.cpu0.icache.demand_hits 56304737 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.015472 # miss rate for demand accesses -system.cpu0.icache.demand_misses 884863 # number of demand (read+write) misses +system.cpu0.icache.demand_miss_rate 0.015473 # miss rate for demand accesses +system.cpu0.icache.demand_misses 884868 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -114,14 +114,14 @@ system.cpu0.icache.demand_mshr_misses 0 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57190139 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses 57189605 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 56305276 # number of overall hits +system.cpu0.icache.overall_hits 56304737 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.015472 # miss rate for overall accesses -system.cpu0.icache.overall_misses 884863 # number of overall misses +system.cpu0.icache.overall_miss_rate 0.015473 # miss rate for overall accesses +system.cpu0.icache.overall_misses 884868 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -137,19 +137,19 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 884267 # number of replacements -system.cpu0.icache.sampled_refs 884779 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 884272 # number of replacements +system.cpu0.icache.sampled_refs 884784 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 511.244752 # Cycle average of tags in use -system.cpu0.icache.total_refs 56305276 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use +system.cpu0.icache.total_refs 56304737 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles -system.cpu0.itb.accesses 3858846 # ITB accesses +system.cpu0.itb.accesses 3858857 # ITB accesses system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3855361 # ITB hits +system.cpu0.itb.hits 3855372 # ITB hits system.cpu0.itb.misses 3485 # ITB misses -system.cpu0.kern.callpal 183273 # number of callpals executed +system.cpu0.kern.callpal 183274 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed @@ -158,7 +158,7 @@ system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # nu system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 168018 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_swpipl 168019 91.68% 93.82% # number of callpals executed system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed @@ -168,43 +168,43 @@ system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # nu system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 197102 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 197103 # number of hwrei instructions executed system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174851 # number of times we switched to this ipl +system.cpu0.kern.ipl_count 174852 # number of times we switched to this ipl system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101696 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 101697 58.16% 100.00% # number of times we switched to this ipl system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1870334944000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1853125190500 99.08% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1853125830000 99.08% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 17106650000 0.91% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 17106381500 0.91% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684599 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1156 -system.cpu0.kern.mode_good_user 1157 +system.cpu0.kern.ipl_used_31 0.684592 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1157 +system.cpu0.kern.mode_good_user 1158 system.cpu0.kern.mode_good_idle 0 system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1157 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1158 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.163047 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.163188 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1869377939000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 957004000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3762 # number of times the context was actually changed system.cpu0.kern.syscall 226 # number of syscalls executed @@ -239,9 +239,9 @@ system.cpu0.kern.syscall_132 2 0.88% 98.23% # nu system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles -system.cpu0.numCycles 3740670191 # number of cpu cycles simulated -system.cpu0.num_insts 57182083 # Number of instructions executed -system.cpu0.num_refs 15322406 # Number of memory references +system.cpu0.numCycles 3740670933 # number of cpu cycles simulated +system.cpu0.num_insts 57181549 # Number of instructions executed +system.cpu0.num_refs 15322361 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses @@ -255,12 +255,12 @@ system.cpu1.dcache.StoreCondReq_hits 13438 # nu system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits 702800 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate 0.041599 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 30505 # number of WriteReq misses +system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -269,10 +269,10 @@ system.cpu1.dcache.cache_copies 0 # nu system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1812115 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.038293 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 72155 # number of demand (read+write) misses +system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -284,10 +284,10 @@ system.cpu1.dcache.overall_accesses 1884270 # nu system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1812115 # number of overall hits +system.cpu1.dcache.overall_hits 1812118 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.038293 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 72155 # number of overall misses +system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 72152 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -303,13 +303,13 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 62341 # number of replacements -system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 62338 # number of replacements +system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851266680500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 30850 # number of writebacks +system.cpu1.dcache.tagsinuse 391.950049 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 30848 # number of writebacks system.cpu1.dtb.accesses 323622 # DTB accesses system.cpu1.dtb.acv 116 # DTB access violations system.cpu1.dtb.hits 1914885 # DTB hits @@ -322,25 +322,25 @@ system.cpu1.dtb.write_accesses 103280 # DT system.cpu1.dtb.write_acv 58 # DTB write access violations system.cpu1.dtb.write_hits 751446 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5935771 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_hits 5832135 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_rate 0.017460 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 103636 # number of ReadReq misses +system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 56.289849 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5935771 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.icache.demand_hits 5832135 # number of demand (read+write) hits +system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.017460 # miss rate for demand accesses -system.cpu1.icache.demand_misses 103636 # number of demand (read+write) misses +system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses +system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -348,14 +348,14 @@ system.cpu1.icache.demand_mshr_misses 0 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5935771 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5832135 # number of overall hits +system.cpu1.icache.overall_hits 5832136 # number of overall hits system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.017460 # miss rate for overall accesses -system.cpu1.icache.overall_misses 103636 # number of overall misses +system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses +system.cpu1.icache.overall_misses 103630 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -371,12 +371,12 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 103097 # number of replacements -system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 103091 # number of replacements +system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 427.126316 # Cycle average of tags in use -system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use +system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles system.cpu1.itb.accesses 1469938 # ITB accesses @@ -403,7 +403,7 @@ system.cpu1.kern.callpal_imb 38 0.12% 100.00% # nu system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl @@ -414,8 +414,8 @@ system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # nu system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1870124056000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1859122637500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks 1870124427000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl @@ -433,9 +433,9 @@ system.cpu1.kern.mode_switch_good 1.608089 # fr system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 471 # number of times the context was actually changed system.cpu1.kern.syscall 100 # number of syscalls executed system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed @@ -456,8 +456,8 @@ system.cpu1.kern.syscall_74 8 8.00% 97.00% # nu system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles -system.cpu1.numCycles 3740248139 # number of cpu cycles simulated -system.cpu1.num_insts 5931963 # Number of instructions executed +system.cpu1.numCycles 3740248881 # number of cpu cycles simulated +system.cpu1.num_insts 5931958 # Number of instructions executed system.cpu1.num_refs 1926645 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). @@ -525,37 +525,37 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41695 # number of replacements system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.435434 # Cycle average of tags in use +system.iocache.tagsinuse 0.435437 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses 306244 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306246 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2724148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1759614 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.354068 # miss rate for ReadReq accesses +system.l2c.ReadExReq_misses 306244 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2724143 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1759609 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.354069 # miss rate for ReadReq accesses system.l2c.ReadReq_misses 964534 # number of ReadReq misses system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses -system.l2c.Writeback_accesses 427643 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 427643 # number of Writeback hits +system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 427641 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.789371 # Average number of references to valid blocks. +system.l2c.avg_refs 1.789118 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3030394 # number of demand (read+write) accesses +system.l2c.demand_accesses 3030387 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1759614 # number of demand (read+write) hits +system.l2c.demand_hits 1759609 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses -system.l2c.demand_misses 1270780 # number of demand (read+write) misses +system.l2c.demand_misses 1270778 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -563,14 +563,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3030394 # number of overall (read+write) accesses +system.l2c.overall_accesses 3030387 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 1759614 # number of overall hits +system.l2c.overall_hits 1759609 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses -system.l2c.overall_misses 1270780 # number of overall misses +system.l2c.overall_misses 1270778 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -586,13 +586,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1056801 # number of replacements -system.l2c.sampled_refs 1091450 # Sample count of references to valid blocks. +system.l2c.replacements 1056800 # number of replacements +system.l2c.sampled_refs 1091449 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30522.435313 # Cycle average of tags in use -system.l2c.total_refs 1953009 # Total number of references to valid blocks. +system.l2c.tagsinuse 30522.432687 # Cycle average of tags in use +system.l2c.total_refs 1952731 # Total number of references to valid blocks. system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123879 # number of writebacks +system.l2c.writebacks 123878 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 4e60f8a9d..7d514c2b6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,6 +1,6 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +Listening for system connection on port 3459 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 +0: system.remote_gdb.listener: listening for remote gdb on port 7008 warn: Entering event queue @ 0. Starting simulation... warn: 97861500: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index a5a0972a1..601a2c3c3 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:27:21 -M5 started Mon Jul 21 20:28:09 2008 +M5 compiled Aug 2 2008 17:07:34 +M5 started Sat Aug 2 17:08:14 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1870335151500 because m5_exit instruction encountered +Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 4ce652819..e739f3815 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -300,7 +300,7 @@ pio=system.membus.default [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index 082e17724..5018c7d30 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1474278 # Simulator instruction rate (inst/s) -host_mem_usage 260680 # Number of bytes of host memory used -host_seconds 40.70 # Real time elapsed on the host -host_tick_rate 44928072322 # Simulator tick rate (ticks/s) +host_inst_rate 3096300 # Simulator instruction rate (inst/s) +host_mem_usage 288712 # Number of bytes of host memory used +host_seconds 19.38 # Real time elapsed on the host +host_tick_rate 94358252114 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 59995479 # Number of instructions simulated -sim_seconds 1.828355 # Number of seconds simulated -sim_ticks 1828355496000 # Number of ticks simulated +sim_insts 59995351 # Number of instructions simulated +sim_seconds 1.828356 # Number of seconds simulated +sim_ticks 1828355695500 # Number of ticks simulated system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 183119 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17160 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses 9523054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7801378 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate 0.180790 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1721676 # number of ReadReq misses +system.cpu.dcache.LoadLockedReq_hits 183118 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate 0.085685 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17161 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses 9523053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7801372 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.180791 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1721681 # number of ReadReq misses system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 169392 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_rate 0.149886 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29866 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_hits 169391 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate 0.149891 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits 5750772 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate 0.064944 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 399417 # number of WriteReq misses +system.cpu.dcache.WriteReq_hits 5750766 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.064945 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 399423 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.866562 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.866519 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15673243 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 15673242 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 13552150 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 13552138 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135332 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2121093 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.135333 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2121104 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -46,14 +46,14 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15673243 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 15673242 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13552150 # number of overall hits +system.cpu.dcache.overall_hits 13552138 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135332 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2121093 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.135333 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2121104 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -69,44 +69,44 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2042665 # number of replacements -system.cpu.dcache.sampled_refs 2043177 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2042676 # number of replacements +system.cpu.dcache.sampled_refs 2043188 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use -system.cpu.dcache.total_refs 14029602 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.997800 # Cycle average of tags in use +system.cpu.dcache.total_refs 14029590 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 428885 # number of writebacks +system.cpu.dcache.writebacks 428892 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16053818 # DTB hits +system.cpu.dtb.hits 16053817 # DTB hits system.cpu.dtb.misses 11471 # DTB misses system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9703850 # DTB read hits +system.cpu.dtb.read_hits 9703849 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_hits 6349968 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits 59087262 # number of ReadReq hits +system.cpu.icache.ReadReq_accesses 60007189 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits 59087131 # number of ReadReq hits system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 920055 # number of ReadReq misses +system.cpu.icache.ReadReq_misses 920058 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 64.229474 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 64.229122 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 60007189 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 59087262 # number of demand (read+write) hits +system.cpu.icache.demand_hits 59087131 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses -system.cpu.icache.demand_misses 920055 # number of demand (read+write) misses +system.cpu.icache.demand_misses 920058 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -114,14 +114,14 @@ system.cpu.icache.demand_mshr_misses 0 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60007317 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 60007189 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59087262 # number of overall hits +system.cpu.icache.overall_hits 59087131 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses -system.cpu.icache.overall_misses 920055 # number of overall misses +system.cpu.icache.overall_misses 920058 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -137,19 +137,19 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 919428 # number of replacements -system.cpu.icache.sampled_refs 919940 # Sample count of references to valid blocks. +system.cpu.icache.replacements 919431 # number of replacements +system.cpu.icache.sampled_refs 919943 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use -system.cpu.icache.total_refs 59087262 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 511.214823 # Cycle average of tags in use +system.cpu.icache.total_refs 59087131 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0.983588 # Percentage of idle cycles -system.cpu.itb.accesses 4979217 # ITB accesses +system.cpu.itb.accesses 4979228 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974211 # ITB hits +system.cpu.itb.hits 4974222 # ITB hits system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192139 # number of callpals executed +system.cpu.kern.callpal 192140 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -157,7 +157,7 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal_swpipl 175210 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_swpipl 175211 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed @@ -167,40 +167,40 @@ system.cpu.kern.callpal_rti 5202 2.71% 99.64% # nu system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211277 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211278 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed -system.cpu.kern.ipl_count 182521 # number of times we switched to this ipl +system.cpu.kern.ipl_count 182522 # number of times we switched to this ipl system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105598 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105599 57.86% 100.00% # number of times we switched to this ipl system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1828355288500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1811087557500 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks 1828355488000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087822500 99.06% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 17167360500 0.94% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.695543 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1908 -system.cpu.kern.mode_good_user 1737 +system.cpu.kern.ipl_used_31 0.695537 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1909 +system.cpu.kern.mode_good_user 1738 system.cpu.kern.mode_good_idle 171 system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches -system.cpu.kern.mode_switch_user 1737 # number of protection mode switches +system.cpu.kern.mode_switch_user 1738 # number of protection mode switches system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.402325 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.320780 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.402493 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320948 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1800056192000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 26834029500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 1465074000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056383500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -234,9 +234,9 @@ system.cpu.kern.syscall_132 4 1.23% 98.77% # nu system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles -system.cpu.numCycles 3656710883 # number of cpu cycles simulated -system.cpu.num_insts 59995479 # Number of instructions executed -system.cpu.num_refs 16302129 # Number of memory references +system.cpu.numCycles 3656711283 # number of cpu cycles simulated +system.cpu.num_insts 59995351 # Number of instructions executed +system.cpu.num_refs 16302128 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -303,37 +303,37 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41686 # number of replacements system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.226223 # Cycle average of tags in use +system.iocache.tagsinuse 1.226225 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses 304347 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304342 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2658874 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1696454 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.361965 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 962420 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 124941 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_misses 304347 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2658883 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1696464 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.361964 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 962419 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 124943 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 124941 # number of UpgradeReq misses -system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 428885 # number of Writeback hits +system.l2c.UpgradeReq_misses 124943 # number of UpgradeReq misses +system.l2c.Writeback_accesses 428892 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 428892 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.726821 # Average number of references to valid blocks. +system.l2c.avg_refs 1.726803 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2963216 # number of demand (read+write) accesses +system.l2c.demand_accesses 2963230 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1696454 # number of demand (read+write) hits +system.l2c.demand_hits 1696464 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.427496 # miss rate for demand accesses -system.l2c.demand_misses 1266762 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.427495 # miss rate for demand accesses +system.l2c.demand_misses 1266766 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -341,14 +341,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2963216 # number of overall (read+write) accesses +system.l2c.overall_accesses 2963230 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 1696454 # number of overall hits +system.l2c.overall_hits 1696464 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.427496 # miss rate for overall accesses -system.l2c.overall_misses 1266762 # number of overall misses +system.l2c.overall_miss_rate 0.427495 # miss rate for overall accesses +system.l2c.overall_misses 1266766 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -364,13 +364,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1050727 # number of replacements -system.l2c.sampled_refs 1081066 # Sample count of references to valid blocks. +system.l2c.replacements 1050731 # number of replacements +system.l2c.sampled_refs 1081071 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30223.986648 # Cycle average of tags in use -system.l2c.total_refs 1866807 # Total number of references to valid blocks. +system.l2c.tagsinuse 30223.992851 # Cycle average of tags in use +system.l2c.total_refs 1866797 # Total number of references to valid blocks. system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119145 # number of writebacks +system.l2c.writebacks 119150 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 7e35fafed..438bf9f24 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,4 +1,4 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +Listening for system connection on port 3459 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index ac8785088..8a31735d4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:27:21 -M5 started Mon Jul 21 20:27:46 2008 +M5 compiled Aug 2 2008 17:07:34 +M5 started Sat Aug 2 17:08:29 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1828355496000 because m5_exit instruction encountered +Exiting @ tick 1828355695500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 459187376..2985b82ee 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -405,7 +405,7 @@ pio=system.membus.default [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 85a08a7e2..3478349a5 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 647923 # Simulator instruction rate (inst/s) -host_mem_usage 252928 # Number of bytes of host memory used -host_seconds 97.63 # Real time elapsed on the host -host_tick_rate 20205445341 # Simulator tick rate (ticks/s) +host_inst_rate 1987058 # Simulator instruction rate (inst/s) +host_mem_usage 287224 # Number of bytes of host memory used +host_seconds 29.88 # Real time elapsed on the host +host_tick_rate 65994111033 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 63257216 # Number of instructions simulated -sim_seconds 1.972680 # Number of seconds simulated -sim_ticks 1972679592000 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 192278 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency 13965.504894 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10965.504894 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits 175522 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 234006000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate 0.087145 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16756 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 183738000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.087145 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16756 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 9119152 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 21251.410270 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 18251.386941 # average ReadReq mshr miss latency +sim_insts 59379829 # Number of instructions simulated +sim_seconds 1.972135 # Number of seconds simulated +sim_ticks 1972135479000 # Number of ticks simulated +system.cpu0.dcache.LoadLockedReq_accesses 192618 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14266.203842 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11266.203842 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 175909 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 238374000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.086747 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 16709 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086747 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16709 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 8482392 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 25694.187455 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.147984 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 7426037 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 35981081500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.185666 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1693115 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 30901697000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.185666 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 1693115 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 857399000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses 191314 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 26686.254525 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 23686.254525 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits 162861 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 759304000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate 0.148724 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 28453 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 673945000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.148724 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 28453 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 5834436 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 26949.612638 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 23949.612638 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 7443656 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 26689477500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.122458 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1038736 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 23573228500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122458 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1038736 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 868701000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 191654 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 55352.322833 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52352.322833 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 163305 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 1569183000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.147918 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 28349 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1484136000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147918 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 28349 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 5845269 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 55891.595936 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.595936 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits 5455075 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 10223632000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.065021 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 379361 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 9085549000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.065021 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 379361 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1211657000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_hits 5466012 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 21197279000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.064883 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 379257 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 20059508000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064883 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 379257 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1225890000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.692591 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 9.984583 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14953588 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 22294.450454 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 19294.431395 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12881112 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 46204713500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.138594 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2072476 # number of demand (read+write) misses +system.cpu0.dcache.demand_accesses 14327661 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 33770.798939 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 12909668 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 47886756500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.098969 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1417993 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 39987246000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.138594 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 2072476 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_miss_latency 43632736500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.098969 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1417993 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14953588 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 22294.450454 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 19294.431395 # average overall mshr miss latency +system.cpu0.dcache.overall_accesses 14327661 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 33770.798939 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12881112 # number of overall hits -system.cpu0.dcache.overall_miss_latency 46204713500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.138594 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2072476 # number of overall misses +system.cpu0.dcache.overall_hits 12909668 # number of overall hits +system.cpu0.dcache.overall_miss_latency 47886756500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.098969 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1417993 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 39987246000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.138594 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 2072476 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2069056000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_miss_latency 43632736500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.098969 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1417993 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2094591000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -97,69 +97,69 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1992967 # number of replacements -system.cpu0.dcache.sampled_refs 1993479 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1338626 # number of replacements +system.cpu0.dcache.sampled_refs 1339138 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 503.888732 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13341539 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 66395000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 403713 # number of writebacks -system.cpu0.dtb.accesses 719861 # DTB accesses +system.cpu0.dcache.tagsinuse 503.746259 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13370734 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 403562 # number of writebacks +system.cpu0.dtb.accesses 719860 # DTB accesses system.cpu0.dtb.acv 289 # DTB access violations -system.cpu0.dtb.hits 15321442 # DTB hits -system.cpu0.dtb.misses 8487 # DTB misses -system.cpu0.dtb.read_accesses 524202 # DTB read accesses +system.cpu0.dtb.hits 14696400 # DTB hits +system.cpu0.dtb.misses 8485 # DTB misses +system.cpu0.dtb.read_accesses 524201 # DTB read accesses system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 9294921 # DTB read hits -system.cpu0.dtb.read_misses 7689 # DTB read misses +system.cpu0.dtb.read_hits 8658591 # DTB read hits +system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.write_accesses 195659 # DTB write accesses system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 6026521 # DTB write hits +system.cpu0.dtb.write_hits 6037809 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57943269 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 14213.482115 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11212.730813 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 57028190 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 13006459000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.015793 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 915079 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 10260534500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.015793 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 915079 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_accesses 54124252 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 14681.475669 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.724759 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 53208030 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 13451491000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.016928 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 916222 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 10702137000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.016928 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 916222 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 62.327526 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 58.081472 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57943269 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 14213.482115 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11212.730813 # average overall mshr miss latency -system.cpu0.icache.demand_hits 57028190 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 13006459000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.015793 # miss rate for demand accesses -system.cpu0.icache.demand_misses 915079 # number of demand (read+write) misses +system.cpu0.icache.demand_accesses 54124252 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 14681.475669 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency +system.cpu0.icache.demand_hits 53208030 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 13451491000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.016928 # miss rate for demand accesses +system.cpu0.icache.demand_misses 916222 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 10260534500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.015793 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 915079 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_miss_latency 10702137000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.016928 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 916222 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57943269 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 14213.482115 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11212.730813 # average overall mshr miss latency +system.cpu0.icache.overall_accesses 54124252 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 14681.475669 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 57028190 # number of overall hits -system.cpu0.icache.overall_miss_latency 13006459000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.015793 # miss rate for overall accesses -system.cpu0.icache.overall_misses 915079 # number of overall misses +system.cpu0.icache.overall_hits 53208030 # number of overall hits +system.cpu0.icache.overall_miss_latency 13451491000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.016928 # miss rate for overall accesses +system.cpu0.icache.overall_misses 916222 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 10260534500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.015793 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 915079 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_miss_latency 10702137000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.016928 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 916222 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -171,76 +171,76 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 914464 # number of replacements -system.cpu0.icache.sampled_refs 914976 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 915582 # number of replacements +system.cpu0.icache.sampled_refs 916093 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 507.411447 # Cycle average of tags in use -system.cpu0.icache.total_refs 57028190 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 49269353000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tagsinuse 508.642784 # Cycle average of tags in use +system.cpu0.icache.total_refs 53208030 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.932800 # Percentage of idle cycles -system.cpu0.itb.accesses 3949472 # ITB accesses +system.cpu0.idle_fraction 0.933199 # Percentage of idle cycles +system.cpu0.itb.accesses 3953623 # ITB accesses system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 3945631 # ITB hits +system.cpu0.itb.hits 3949782 # ITB hits system.cpu0.itb.misses 3841 # ITB misses -system.cpu0.kern.callpal 187580 # number of callpals executed +system.cpu0.kern.callpal 187998 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 94 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3867 2.06% 2.11% # number of callpals executed -system.cpu0.kern.callpal_tbi 44 0.02% 2.14% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3868 2.06% 2.11% # number of callpals executed +system.cpu0.kern.callpal_tbi 44 0.02% 2.13% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 171680 91.52% 93.66% # number of callpals executed -system.cpu0.kern.callpal_rdps 6661 3.55% 97.22% # number of callpals executed +system.cpu0.kern.callpal_swpipl 172054 91.52% 93.65% # number of callpals executed +system.cpu0.kern.callpal_rdps 6698 3.56% 97.22% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_rti 4704 2.51% 99.73% # number of callpals executed +system.cpu0.kern.callpal_rti 4713 2.51% 99.73% # number of callpals executed system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 202457 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6163 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 178500 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 72488 40.61% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 131 0.07% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1977 1.11% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 7 0.00% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 103897 58.21% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 144346 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 71119 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.hwrei 202882 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6254 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 178892 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72633 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.07% 40.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1987 1.11% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 6 0.00% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 104135 58.21% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 144646 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 71264 49.27% 49.27% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1977 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 7 0.00% 50.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 71112 49.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1972678821000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1900126420500 96.32% 96.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 86973000 0.00% 96.33% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 568583000 0.03% 96.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 5546500 0.00% 96.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 71891298000 3.64% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.981114 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good_22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 71258 49.26% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1972134721000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1908424308500 96.77% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 96335500 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 576469500 0.03% 96.80% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.80% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 63032165000 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.981152 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684447 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1228 -system.cpu0.kern.mode_good_user 1229 +system.cpu0.kern.ipl_used_31 0.684285 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1232 +system.cpu0.kern.mode_good_user 1233 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7227 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1229 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7237 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1233 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.169918 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.170236 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1969223377000 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 3455442000 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1968330428000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3804291000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3868 # number of times the context was actually changed +system.cpu0.kern.swap_context 3869 # number of times the context was actually changed system.cpu0.kern.syscall 224 # number of syscalls executed system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed @@ -272,89 +272,89 @@ system.cpu0.kern.syscall_98 2 0.89% 97.77% # nu system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.067200 # Percentage of non-idle cycles -system.cpu0.numCycles 3945359184 # number of cpu cycles simulated -system.cpu0.num_insts 57934492 # Number of instructions executed -system.cpu0.num_refs 15562811 # Number of memory references -system.cpu1.dcache.LoadLockedReq_accesses 12625 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency 12190.944882 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9190.944882 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits 11609 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 12386000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate 0.080475 # miss rate for LoadLockedReq accesses +system.cpu0.not_idle_fraction 0.066801 # Percentage of non-idle cycles +system.cpu0.numCycles 3944270958 # number of cpu cycles simulated +system.cpu0.num_insts 54115477 # Number of instructions executed +system.cpu0.num_refs 14937789 # Number of memory references +system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13393.700787 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10393.700787 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 11318 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 13608000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.082374 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_misses 1016 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 9338000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.080475 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10560000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.082374 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_misses 1016 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 1030298 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 13948.255862 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10948.131577 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_accesses 1020508 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 15788.930188 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12788.832374 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 994091 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 505024500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.035142 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 36207 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 396399000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035142 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 36207 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 13393500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses 12560 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency 22874.692875 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 19874.692875 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits 10118 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 55860000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate 0.194427 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 2442 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 48534000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.194427 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 2442 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 657926 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 26378.844865 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 23378.844865 # average WriteReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 984726 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 564959500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.035063 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 35782 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 457610000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035063 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 35782 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses 12269 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 46915.603129 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43915.603129 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 9840 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 113958000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.197979 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 2429 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106671000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197979 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 2429 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 649988 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 54642.103265 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51642.103265 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits 631072 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 708377500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.040816 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 26854 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 627815500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040816 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 26854 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 305665000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_hits 623648 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 1439273000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.040524 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 26340 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1360253000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040524 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 26340 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303022000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 30.077708 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 30.126995 # Average number of references to valid blocks. system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1688224 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 19241.718336 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 16241.646977 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1625163 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 1213402000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.037353 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 63061 # number of demand (read+write) misses +system.cpu1.dcache.demand_accesses 1670496 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 32262.845691 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1608374 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 2004232500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.037188 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 62122 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 1024214500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.037353 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 63061 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_miss_latency 1817863000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.037188 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 62122 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1688224 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 19241.718336 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 16241.646977 # average overall mshr miss latency +system.cpu1.dcache.overall_accesses 1670496 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 32262.845691 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1625163 # number of overall hits -system.cpu1.dcache.overall_miss_latency 1213402000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.037353 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 63061 # number of overall misses +system.cpu1.dcache.overall_hits 1608374 # number of overall hits +system.cpu1.dcache.overall_miss_latency 2004232500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.037188 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 62122 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 1024214500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.037353 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 63061 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 319058500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_miss_latency 1817863000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.037188 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 62122 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 315548000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -365,69 +365,69 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 54390 # number of replacements -system.cpu1.dcache.sampled_refs 54808 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 53749 # number of replacements +system.cpu1.dcache.sampled_refs 54144 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 387.947804 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1648499 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1956976796000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 27227 # number of writebacks +system.cpu1.dcache.tagsinuse 388.873056 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1631196 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1954644714000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 26833 # number of writebacks system.cpu1.dtb.accesses 302878 # DTB accesses system.cpu1.dtb.acv 84 # DTB access violations -system.cpu1.dtb.hits 1712100 # DTB hits +system.cpu1.dtb.hits 1693796 # DTB hits system.cpu1.dtb.misses 3106 # DTB misses system.cpu1.dtb.read_accesses 205838 # DTB read accesses system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 1039743 # DTB read hits +system.cpu1.dtb.read_hits 1029675 # DTB read hits system.cpu1.dtb.read_misses 2750 # DTB read misses system.cpu1.dtb.write_accesses 97040 # DTB write accesses system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_hits 672357 # DTB write hits +system.cpu1.dtb.write_hits 664121 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5325914 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14299.912084 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11299.461372 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 5236056 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 1284961500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.016872 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 89858 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1015347000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.016872 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 89858 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_accesses 5267542 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 14619.415532 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11618.958024 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 5180112 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 1278175500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.016598 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 87430 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 1015845500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.016598 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 87430 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 58.288501 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 59.267660 # Average number of references to valid blocks. system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5325914 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14299.912084 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11299.461372 # average overall mshr miss latency -system.cpu1.icache.demand_hits 5236056 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 1284961500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.016872 # miss rate for demand accesses -system.cpu1.icache.demand_misses 89858 # number of demand (read+write) misses +system.cpu1.icache.demand_accesses 5267542 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 14619.415532 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency +system.cpu1.icache.demand_hits 5180112 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 1278175500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.016598 # miss rate for demand accesses +system.cpu1.icache.demand_misses 87430 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 1015347000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.016872 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 89858 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_miss_latency 1015845500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.016598 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 87430 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5325914 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14299.912084 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11299.461372 # average overall mshr miss latency +system.cpu1.icache.overall_accesses 5267542 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 14619.415532 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5236056 # number of overall hits -system.cpu1.icache.overall_miss_latency 1284961500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.016872 # miss rate for overall accesses -system.cpu1.icache.overall_misses 89858 # number of overall misses +system.cpu1.icache.overall_hits 5180112 # number of overall hits +system.cpu1.icache.overall_miss_latency 1278175500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.016598 # miss rate for overall accesses +system.cpu1.icache.overall_misses 87430 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 1015347000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.016872 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 89858 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_miss_latency 1015845500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.016598 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 87430 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -439,72 +439,72 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 89318 # number of replacements -system.cpu1.icache.sampled_refs 89830 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 86890 # number of replacements +system.cpu1.icache.sampled_refs 87402 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 419.412997 # Cycle average of tags in use -system.cpu1.icache.total_refs 5236056 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1957297672000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 419.405623 # Cycle average of tags in use +system.cpu1.icache.total_refs 5180112 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1967879772000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.995045 # Percentage of idle cycles -system.cpu1.itb.accesses 1398451 # ITB accesses +system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles +system.cpu1.itb.accesses 1397499 # ITB accesses system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 1397205 # ITB hits +system.cpu1.itb.hits 1396253 # ITB hits system.cpu1.itb.misses 1246 # ITB misses -system.cpu1.kern.callpal 29654 # number of callpals executed +system.cpu1.kern.callpal 29501 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 7 0.02% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 369 1.24% 1.28% # number of callpals executed -system.cpu1.kern.callpal_tbi 10 0.03% 1.31% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.02% 1.34% # number of callpals executed -system.cpu1.kern.callpal_swpipl 24277 81.87% 83.20% # number of callpals executed -system.cpu1.kern.callpal_rdps 2191 7.39% 90.59% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 90.59% # number of callpals executed -system.cpu1.kern.callpal_wrusp 3 0.01% 90.60% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.01% 90.61% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 90.62% # number of callpals executed -system.cpu1.kern.callpal_rti 2588 8.73% 99.35% # number of callpals executed -system.cpu1.kern.callpal_callsys 161 0.54% 99.89% # number of callpals executed -system.cpu1.kern.callpal_imb 31 0.10% 100.00% # number of callpals executed +system.cpu1.kern.callpal_swpctx 365 1.24% 1.27% # number of callpals executed +system.cpu1.kern.callpal_tbi 10 0.03% 1.30% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.33% # number of callpals executed +system.cpu1.kern.callpal_swpipl 24142 81.83% 83.16% # number of callpals executed +system.cpu1.kern.callpal_rdps 2172 7.36% 90.52% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 90.53% # number of callpals executed +system.cpu1.kern.callpal_wrusp 3 0.01% 90.54% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 90.54% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 90.55% # number of callpals executed +system.cpu1.kern.callpal_rti 2594 8.79% 99.35% # number of callpals executed +system.cpu1.kern.callpal_callsys 161 0.55% 99.89% # number of callpals executed +system.cpu1.kern.callpal_imb 31 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 36198 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2401 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 28931 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 9254 31.99% 31.99% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1971 6.81% 38.80% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 94 0.32% 39.12% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 17612 60.88% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 20463 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 9246 45.18% 45.18% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1971 9.63% 54.82% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 94 0.46% 55.28% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 9152 44.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1972666579000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1919200833000 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 508731500 0.03% 97.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 56757500 0.00% 97.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 52900257000 2.68% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.999136 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 36051 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 28808 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 9172 31.84% 31.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1980 6.87% 38.71% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 91 0.32% 39.03% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 17565 60.97% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 20308 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 9164 45.13% 45.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 9073 44.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1971683837000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1927969399500 97.78% 97.78% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 511268500 0.03% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 58584000 0.00% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 43144585000 2.19% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999128 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.519646 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 533 -system.cpu1.kern.mode_good_user 515 -system.cpu1.kern.mode_good_idle 18 -system.cpu1.kern.mode_switch_kernel 882 # number of protection mode switches -system.cpu1.kern.mode_switch_user 515 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2077 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.612975 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.604308 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.516539 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 532 +system.cpu1.kern.mode_good_user 516 +system.cpu1.kern.mode_good_idle 16 +system.cpu1.kern.mode_switch_kernel 880 # number of protection mode switches +system.cpu1.kern.mode_switch_user 516 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2081 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.612234 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.604545 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.008666 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 3978131000 0.20% 0.20% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1616488000 0.08% 0.28% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1966135435000 99.72% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 370 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good_idle 0.007689 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 4597806000 0.23% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1703603000 0.09% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1964669629000 99.68% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 366 # number of times the context was actually changed system.cpu1.kern.syscall 102 # number of syscalls executed system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed @@ -527,10 +527,10 @@ system.cpu1.kern.syscall_90 1 0.98% 95.10% # nu system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.004955 # Percentage of non-idle cycles -system.cpu1.numCycles 3945333218 # number of cpu cycles simulated -system.cpu1.num_insts 5322724 # Number of instructions executed -system.cpu1.num_refs 1722033 # Number of memory references +system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles +system.cpu1.numCycles 3943367734 # number of cpu cycles simulated +system.cpu1.num_insts 5264352 # Number of instructions executed +system.cpu1.num_refs 1703685 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -543,58 +543,58 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 113562.488636 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 61562.488636 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19986998 # number of ReadReq miss cycles +system.iocache.ReadReq_accesses 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency 115196.617978 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 176 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10834998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_misses 178 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 115053.879621 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 63053.711494 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 4780718806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137906.834954 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85903.204082 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5730304806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 2620007820 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3569449936 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 4173.944424 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6168.564107 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 2771 # number of cycles access was blocked +system.iocache.blocked_no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 11566000 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64517012 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41728 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 115047.589245 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 63047.421827 # average overall mshr miss latency +system.iocache.demand_accesses 41730 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 137809.964150 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 4800705804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5750809804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41728 # number of demand (read+write) misses +system.iocache.demand_misses 41730 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 2630842818 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3580698934 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41728 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 115047.589245 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 63047.421827 # average overall mshr miss latency +system.iocache.overall_accesses 41730 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 137809.964150 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 4800705804 # number of overall miss cycles +system.iocache.overall_miss_latency 5750809804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41728 # number of overall misses +system.iocache.overall_misses 41730 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 2630842818 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3580698934 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -606,83 +606,83 @@ system.iocache.prefetcher.num_hwpf_issued 0 # n system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.iocache.replacements 41696 # number of replacements -system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.replacements 41698 # number of replacements +system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.554980 # Cycle average of tags in use +system.iocache.tagsinuse 0.582076 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1766170681000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1762323729000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 307159 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 23004.538366 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 11004.538366 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 7066051000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 306796 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52002.653229 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40002.653229 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15954206000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 307159 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 3380143000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 306796 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12272654000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 307159 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2746067 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 23012.790348 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 11012.812299 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 306796 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2090247 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52016.274350 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.322096 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1782997 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 22162928000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.350709 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 963070 # number of ReadReq misses +system.l2c.ReadReq_hits 1782800 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15992247500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.147086 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 307447 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 10605988000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.350705 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 963059 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 779852500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 127459 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 22445.817871 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 11007.104245 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 2860921500 # number of UpgradeReq miss cycles +system.l2c.ReadReq_mshr_miss_latency 12302458000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.147081 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 307436 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 789200000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 127300 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 50741.146897 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40004.988217 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6459348000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 127459 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 1402954500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 127300 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5092635000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 127459 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 127300 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1370781000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430940 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430940 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1381237000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430395 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430395 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.813929 # Average number of references to valid blocks. +system.l2c.avg_refs 4.558799 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3053226 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 23010.794904 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 11010.811530 # average overall mshr miss latency -system.l2c.demand_hits 1782997 # number of demand (read+write) hits -system.l2c.demand_miss_latency 29228979000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.416028 # miss rate for demand accesses -system.l2c.demand_misses 1270229 # number of demand (read+write) misses +system.l2c.demand_accesses 2397043 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52009.471007 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency +system.l2c.demand_hits 1782800 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31946453500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.256250 # miss rate for demand accesses +system.l2c.demand_misses 614243 # number of demand (read+write) misses system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 13986131000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.416025 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 1270218 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24575112000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.256246 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 614232 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3053226 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 23010.794904 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 11010.811530 # average overall mshr miss latency +system.l2c.overall_accesses 2397043 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52009.471007 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1782997 # number of overall hits -system.l2c.overall_miss_latency 29228979000 # number of overall miss cycles -system.l2c.overall_miss_rate 0.416028 # miss rate for overall accesses -system.l2c.overall_misses 1270229 # number of overall misses +system.l2c.overall_hits 1782800 # number of overall hits +system.l2c.overall_miss_latency 31946453500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.256250 # miss rate for overall accesses +system.l2c.overall_misses 614243 # number of overall misses system.l2c.overall_mshr_hits 11 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 13986131000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.416025 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 1270218 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2150633500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24575112000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.256246 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 614232 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2170437000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -693,13 +693,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1055829 # number of replacements -system.l2c.sampled_refs 1087019 # Sample count of references to valid blocks. +system.l2c.replacements 399043 # number of replacements +system.l2c.sampled_refs 430765 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30866.493853 # Cycle average of tags in use -system.l2c.total_refs 1971775 # Total number of references to valid blocks. -system.l2c.warmup_cycle 7281125000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123132 # number of writebacks +system.l2c.tagsinuse 30865.823052 # Cycle average of tags in use +system.l2c.total_refs 1963771 # Total number of references to valid blocks. +system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 123178 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index b0bbb3d67..98c38c0d8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,6 +1,6 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +Listening for system connection on port 3458 +0: system.remote_gdb.listener: listening for remote gdb on port 7007 +0: system.remote_gdb.listener: listening for remote gdb on port 7008 warn: Entering event queue @ 0. Starting simulation... -warn: 478619000: Trying to launch CPU number 1! +warn: 591544000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 18467c41b..dff43c48d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:27:21 -M5 started Mon Jul 21 20:27:23 2008 +M5 compiled Aug 2 2008 17:07:34 +M5 started Sat Aug 2 17:07:43 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1972679592000 because m5_exit instruction encountered +Exiting @ tick 1972135479000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal index c2aeea3f1..6974143c8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal @@ -27,6 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 +
4096K Bcache detected; load hit latency 40 cycles, load miss latency 123 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 66d96d325..05eb9b89c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -297,7 +297,7 @@ pio=system.membus.default [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index fcddfbde2..7b835d1b3 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 827411 # Simulator instruction rate (inst/s) -host_mem_usage 316168 # Number of bytes of host memory used -host_seconds 72.58 # Real time elapsed on the host -host_tick_rate 26612603617 # Simulator tick rate (ticks/s) +host_inst_rate 1555255 # Simulator instruction rate (inst/s) +host_mem_usage 285892 # Number of bytes of host memory used +host_seconds 36.11 # Real time elapsed on the host +host_tick_rate 53447376481 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 60056349 # Number of instructions simulated -sim_seconds 1.931640 # Number of seconds simulated -sim_ticks 1931639667000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200273 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 14106.217767 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11106.217767 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 183016 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 243431000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.086167 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17257 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 191660000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086167 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17257 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 9530772 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21143.101090 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18143.074712 # average ReadReq mshr miss latency +sim_insts 56165112 # Number of instructions simulated +sim_seconds 1.930166 # Number of seconds simulated +sim_ticks 1930165791000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200388 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.212121 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.212121 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 183063 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 248808000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.086457 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17325 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196833000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086457 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17325 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 8882666 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 25452.857499 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.814515 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7805869 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36469798500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.180983 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1724903 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 31295044000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.180983 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1724903 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 837553000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 199252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 27003.604806 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 24003.604806 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 169292 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 809028000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.150362 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29960 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 719148000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150362 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 29960 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6154055 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27005.969289 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24005.969289 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7812517 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 27238350000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.120476 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1070149 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 24027857000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.120476 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1070149 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 847845000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 199368 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.365794 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.365794 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 169362 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1680467000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.150506 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 30006 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590449000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150506 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 30006 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6158164 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56004.032630 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.032630 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 5753421 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10819509500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.065101 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 400634 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 9617607500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.065101 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 400634 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1174669000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_hits 5757309 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 22449496500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.065093 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 21246931500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.065093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1186275000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.859082 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.091593 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15684827 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22248.169757 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19248.148350 # average overall mshr miss latency -system.cpu.dcache.demand_hits 13559290 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 47289308000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135515 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2125537 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 15040830 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33778.185851 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency +system.cpu.dcache.demand_hits 13569826 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 49687846500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.097801 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1471004 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 40912651500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.135515 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2125537 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 45274788500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.097801 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1471004 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15684827 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22248.169757 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19248.148350 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 15040830 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33778.185851 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13559290 # number of overall hits -system.cpu.dcache.overall_miss_latency 47289308000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135515 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2125537 # number of overall misses +system.cpu.dcache.overall_hits 13569826 # number of overall hits +system.cpu.dcache.overall_miss_latency 49687846500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.097801 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1471004 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 40912651500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.135515 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2125537 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2012222000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_miss_latency 45274788500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.097801 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1471004 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2034120000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -97,69 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2046082 # number of replacements -system.cpu.dcache.sampled_refs 2046594 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1391586 # number of replacements +system.cpu.dcache.sampled_refs 1392098 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.986722 # Cycle average of tags in use -system.cpu.dcache.total_refs 14037756 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 66420000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430195 # number of writebacks -system.cpu.dtb.accesses 1020787 # DTB accesses +system.cpu.dcache.tagsinuse 511.984141 # Cycle average of tags in use +system.cpu.dcache.total_refs 14048487 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 430461 # number of writebacks +system.cpu.dtb.accesses 1020784 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16064922 # DTB hits -system.cpu.dtb.misses 11471 # DTB misses -system.cpu.dtb.read_accesses 728856 # DTB read accesses +system.cpu.dtb.hits 15421361 # DTB hits +system.cpu.dtb.misses 11466 # DTB misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9711464 # DTB read hits -system.cpu.dtb.read_misses 10329 # DTB read misses +system.cpu.dtb.read_hits 9063577 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6353458 # DTB write hits +system.cpu.dtb.write_hits 6357784 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60068188 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14221.050037 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11220.318707 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 59139059 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13213190000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.015468 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 929129 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10425123500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.015468 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 929129 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 56176946 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14711.628674 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.898216 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 55246023 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13695393500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.016571 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 930923 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10901944500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.016571 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 930923 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 63.660961 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 59.355692 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60068188 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14221.050037 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11220.318707 # average overall mshr miss latency -system.cpu.icache.demand_hits 59139059 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13213190000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.015468 # miss rate for demand accesses -system.cpu.icache.demand_misses 929129 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 56176946 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14711.628674 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency +system.cpu.icache.demand_hits 55246023 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13695393500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.016571 # miss rate for demand accesses +system.cpu.icache.demand_misses 930923 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10425123500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.015468 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 929129 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 10901944500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.016571 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 930923 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60068188 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14221.050037 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11220.318707 # average overall mshr miss latency +system.cpu.icache.overall_accesses 56176946 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14711.628674 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59139059 # number of overall hits -system.cpu.icache.overall_miss_latency 13213190000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.015468 # miss rate for overall accesses -system.cpu.icache.overall_misses 929129 # number of overall misses +system.cpu.icache.overall_hits 55246023 # number of overall hits +system.cpu.icache.overall_miss_latency 13695393500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.016571 # miss rate for overall accesses +system.cpu.icache.overall_misses 930923 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10425123500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.015468 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 929129 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 10901944500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.016571 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 930923 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -171,71 +171,71 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 928458 # number of replacements -system.cpu.icache.sampled_refs 928969 # Sample count of references to valid blocks. +system.cpu.icache.replacements 930251 # number of replacements +system.cpu.icache.sampled_refs 930762 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 507.298573 # Cycle average of tags in use -system.cpu.icache.total_refs 59139059 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 48981308000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 508.559731 # Cycle average of tags in use +system.cpu.icache.total_refs 55246023 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.929252 # Percentage of idle cycles -system.cpu.itb.accesses 4979997 # ITB accesses +system.cpu.idle_fraction 0.929251 # Percentage of idle cycles +system.cpu.itb.accesses 4982832 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974991 # ITB hits -system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192947 # number of callpals executed +system.cpu.itb.hits 4977822 # ITB hits +system.cpu.itb.misses 5010 # ITB misses +system.cpu.kern.callpal 193204 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 175999 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal_rdps 6835 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed +system.cpu.kern.callpal_swpipl 176240 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal_rti 5159 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_rti 5169 2.68% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212042 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6180 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183224 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74910 40.88% 40.88% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1934 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106249 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149151 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73543 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73543 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1931638909000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1859511291500 96.27% 96.27% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 87343500 0.00% 96.27% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 557262000 0.03% 96.30% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 71483012000 3.70% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981751 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 212308 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6258 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183485 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74993 40.87% 40.87% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106417 58.00% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149327 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73626 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73626 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1930165033000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1867007591000 96.73% 96.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 96059500 0.00% 96.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 565327500 0.03% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 62496055000 3.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981772 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.692176 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1905 -system.cpu.kern.mode_good_user 1736 -system.cpu.kern.mode_good_idle 169 -system.cpu.kern.mode_switch_kernel 5906 # number of protection mode switches -system.cpu.kern.mode_switch_user 1736 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2093 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.403299 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.322553 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.691863 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1910 +system.cpu.kern.mode_good_user 1743 +system.cpu.kern.mode_good_idle 167 +system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches +system.cpu.kern.mode_switch_user 1743 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.402741 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.322799 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.080745 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 45112475000 2.34% 2.34% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 5048233000 0.26% 2.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1881478199000 97.40% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 48448667000 2.51% 2.51% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 5540662000 0.29% 2.80% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1876175702000 97.20% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4172 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed @@ -267,10 +267,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.070748 # Percentage of non-idle cycles -system.cpu.numCycles 3863279334 # number of cpu cycles simulated -system.cpu.num_insts 60056349 # Number of instructions executed -system.cpu.num_refs 16313052 # Number of memory references +system.cpu.not_idle_fraction 0.070749 # Percentage of non-idle cycles +system.cpu.numCycles 3860331582 # number of cpu cycles simulated +system.cpu.num_insts 56165112 # Number of instructions executed +system.cpu.num_refs 15669461 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -284,55 +284,55 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 113566.462428 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 61566.462428 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19646998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10650998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 115104.611234 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 63104.539180 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 4782826806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137880.578697 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85877.091981 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5729213806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 2622119812 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3568364926 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 4196.454414 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6163.865928 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 2764 # number of cycles access was blocked +system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 11599000 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64548004 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 115098.233769 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 63098.162013 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 137786.765824 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 4802473804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5749152804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 2632770810 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3579307924 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 115098.233769 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 63098.162013 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 137786.765824 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 4802473804 # number of overall miss cycles +system.iocache.overall_miss_latency 5749152804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 2632770810 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3579307924 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -349,79 +349,79 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.333347 # Cycle average of tags in use +system.iocache.tagsinuse 1.353410 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1766149259000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1762299198000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304436 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 23005.373872 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 11005.373872 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 7003664000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 304625 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52003.272876 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40003.272876 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15841497000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304436 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 3350432000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 304625 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12185997000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 304436 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2671270 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 23012.722595 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 11012.722595 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 304625 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2018377 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52016.376522 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.358642 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1708534 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 22155176500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.360404 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 962736 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 10602344500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.360404 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 962736 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 750102000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 126158 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 23005.275131 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 11006.915931 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 2902299500 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits 1710772 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16000497500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.152402 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 307605 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 12309232000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.152402 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 307605 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 759315000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 126236 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52001.881397 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.980861 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6564509500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 126158 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 1388610500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 126236 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5050195000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 126158 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 126236 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1061281000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430195 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430195 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1071771000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430461 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430461 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.743066 # Average number of references to valid blocks. +system.l2c.avg_refs 4.436452 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2975706 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 23010.957076 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 11010.957076 # average overall mshr miss latency -system.l2c.demand_hits 1708534 # number of demand (read+write) hits -system.l2c.demand_miss_latency 29158840500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.425839 # miss rate for demand accesses -system.l2c.demand_misses 1267172 # number of demand (read+write) misses +system.l2c.demand_accesses 2323002 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52009.856590 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency +system.l2c.demand_hits 1710772 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31841994500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.263551 # miss rate for demand accesses +system.l2c.demand_misses 612230 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 13952776500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.425839 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 1267172 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24495229000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.263551 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 612230 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2975706 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 23010.957076 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 11010.957076 # average overall mshr miss latency +system.l2c.overall_accesses 2323002 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52009.856590 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1708534 # number of overall hits -system.l2c.overall_miss_latency 29158840500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.425839 # miss rate for overall accesses -system.l2c.overall_misses 1267172 # number of overall misses +system.l2c.overall_hits 1710772 # number of overall hits +system.l2c.overall_miss_latency 31841994500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.263551 # miss rate for overall accesses +system.l2c.overall_misses 612230 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 13952776500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.425839 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 1267172 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1811383000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24495229000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.263551 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 612230 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1831086000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -432,13 +432,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1050085 # number of replacements -system.l2c.sampled_refs 1081030 # Sample count of references to valid blocks. +system.l2c.replacements 394925 # number of replacements +system.l2c.sampled_refs 425907 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30869.828292 # Cycle average of tags in use -system.l2c.total_refs 1884307 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5029142000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 118653 # number of writebacks +system.l2c.tagsinuse 30594.024615 # Cycle average of tags in use +system.l2c.total_refs 1889516 # Total number of references to valid blocks. +system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119047 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 408213e67..3aab2bec2 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,4 +1,4 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb on port 7004 +Listening for system connection on port 3458 +0: system.remote_gdb.listener: listening for remote gdb on port 7007 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index a429ac712..4d30d3925 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:27:21 -M5 started Mon Jul 21 20:28:11 2008 +M5 compiled Aug 2 2008 17:07:34 +M5 started Sat Aug 2 17:08:13 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1931639667000 because m5_exit instruction encountered +Exiting @ tick 1930165791000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal index 7930e9e46..3efa225a8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal @@ -24,6 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 +
4096K Bcache detected; load hit latency 40 cycles, load miss latency 124 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 |