diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:09 -0500 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:09 -0500 |
commit | ba265abbfd70060cc61a3b4a53b4b1cfcb7a96fe (patch) | |
tree | 5cf148fb600af2da5440a442d10170666ae8bbc9 /tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual | |
parent | c9d5985b8221459e4737c637910dc08513b05660 (diff) | |
download | gem5-ba265abbfd70060cc61a3b4a53b4b1cfcb7a96fe.tar.xz |
ARM: Add some MP regressions and clean up the disk images and kernels a bit
Diffstat (limited to 'tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual')
6 files changed, 1576 insertions, 0 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini new file mode 100644 index 000000000..9933a8e22 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -0,0 +1,846 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver +boot_cpu_frequency=500 +boot_loader=/chips/pd/randd/dist/binaries/boot.arm +boot_loader_mem=system.nvmem +boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +flags_addr=268435504 +gic_cpu_addr=520093952 +init_param=0 +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +load_addr_mask=268435455 +machine_type=RealView_PBX +mem_mode=atomic +memories=system.nvmem system.physmem +midr_regval=890224640 +physmem=system.physmem +readfile=tests/halt.sh +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 + +[system.bridge] +type=Bridge +delay=50000 +filter_ranges_a=0:18446744073709551615 +filter_ranges_b=0:268435455 +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img +read_only=true + +[system.cpu0] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu0.tracer +width=1 +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.toL2Bus.port[4] + +[system.cpu0.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.interrupts] +type=ArmInterrupts + +[system.cpu0.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.toL2Bus.port[3] + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu1] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=1 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu1.tracer +width=1 +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[6] + +[system.cpu1.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.toL2Bus.port[8] + +[system.cpu1.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[5] + +[system.cpu1.interrupts] +type=ArmInterrupts + +[system.cpu1.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.toL2Bus.port[7] + +[system.cpu1.tracer] +type=ExeTracer + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma + +[system.iocache] +type=BaseCache +addr_range=0:268435455 +assoc=8 +block_size=64 +forward_snoops=false +hash_delay=1 +is_top_level=false +latency=50000 +max_miss_count=0 +mshrs=20 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=500000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.port[25] +mem_side=system.membus.port[7] + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=92 +num_cpus=2 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[8] + +[system.membus] +type=Bus +children=badaddr_responder +block_size=64 +bus_id=1 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +default=system.membus.badaddr_responder.pio +port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +fake_mem=false +pio_addr=0 +pio_latency=1000 +pio_size=8 +platform=system.realview +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.nvmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=2147483648:2214592511 +zero=true +port=system.membus.port[1] + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=true +port=system.membus.port[2] + +[system.realview] +type=RealView +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +intrctrl=system.intrctrl +pci_cfg_base=0 +system=system + +[system.realview.a9scu] +type=A9SCU +pio_addr=520093696 +pio_latency=1000 +platform=system.realview +system=system +pio=system.membus.port[5] + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268451840 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[21] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=402653184 +BAR0LegacyIO=true +BAR0Size=16 +BAR1=402653440 +BAR1LegacyIO=true +BAR1Size=1 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +config_latency=20000 +ctrl_offset=2 +disks=system.cf0 +io_shift=1 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=2 +pci_dev=7 +pci_func=0 +pio_latency=1000 +platform=system.realview +system=system +config=system.iobus.port[26] +dma=system.iobus.port[27] +pio=system.iobus.port[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clock=41667 +gic=system.realview.gic +int_num=55 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pio_addr=268566528 +pio_latency=10000 +platform=system.realview +system=system +vnc=system.vncserver +dma=system.iobus.port[28] +pio=system.iobus.port[5] + +[system.realview.dmac_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268632064 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[9] + +[system.realview.flash_fake] +type=IsaFake +fake_mem=true +pio_addr=1073741824 +pio_latency=1000 +pio_size=536870912 +platform=system.realview +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[24] + +[system.realview.gic] +type=Gic +cpu_addr=520093952 +cpu_pio_delay=10000 +dist_addr=520097792 +dist_pio_delay=10000 +int_latency=10000 +it_lines=128 +platform=system.realview +system=system +pio=system.membus.port[3] + +[system.realview.gpio0_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268513280 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[16] + +[system.realview.gpio1_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268517376 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[17] + +[system.realview.gpio2_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268521472 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[18] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +gic=system.realview.gic +int_delay=1000000 +int_num=52 +is_mouse=false +pio_addr=268460032 +pio_latency=1000 +platform=system.realview +system=system +vnc=system.vncserver +pio=system.iobus.port[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +gic=system.realview.gic +int_delay=1000000 +int_num=53 +is_mouse=true +pio_addr=268464128 +pio_latency=1000 +platform=system.realview +system=system +vnc=system.vncserver +pio=system.iobus.port[7] + +[system.realview.l2x0_fake] +type=IsaFake +fake_mem=false +pio_addr=520101888 +pio_latency=1000 +pio_size=4095 +platform=system.realview +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.port[4] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clock=1000 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=520095232 +pio_latency=1000 +platform=system.realview +system=system +pio=system.membus.port[6] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268455936 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[22] + +[system.realview.realview_io] +type=RealViewCtrl +idreg=0 +pio_addr=268435456 +pio_latency=1000 +platform=system.realview +proc_id0=201326592 +proc_id1=201327138 +system=system +pio=system.iobus.port[2] + +[system.realview.rtc_fake] +type=AmbaFake +amba_id=266289 +ignore_access=false +pio_addr=268529664 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[23] + +[system.realview.sci_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268492800 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[20] + +[system.realview.smc_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=269357056 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[13] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +ignore_access=true +pio_addr=268439552 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[14] + +[system.realview.ssp_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268488704 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[19] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clock0=1000000 +clock1=1000000 +gic=system.realview.gic +int_num0=36 +int_num1=36 +pio_addr=268505088 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[3] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clock0=1000000 +clock1=1000000 +gic=system.realview.gic +int_num0=37 +int_num1=37 +pio_addr=268509184 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[4] + +[system.realview.uart] +type=Pl011 +end_on_eot=false +gic=system.realview.gic +int_delay=100000 +int_num=44 +pio_addr=268472320 +pio_latency=1000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.port[1] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268476416 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[10] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268480512 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[11] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268484608 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[12] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268500992 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[15] + +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port + +[system.vncserver] +type=VncServer +number=0 +port=5900 + diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr new file mode 100755 index 000000000..04178bb32 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr @@ -0,0 +1,18 @@ +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: The clidr register always reports 0 caches. +warn: clidr LoUIS field of 0b001 to match current ARM implementations. +warn: The csselr register isn't implemented. +warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr dccimvac' unimplemented +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented +warn: instruction 'mcr bpiallis' unimplemented +warn: LCD dual screen mode not supported +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout new file mode 100755 index 000000000..38da5afa6 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Aug 18 2011 16:54:46 +gem5 started Aug 18 2011 17:16:56 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: Using bootloader at address 0x80000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 2411694099500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt new file mode 100644 index 000000000..7f6e2a888 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -0,0 +1,699 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.411694 # Number of seconds simulated +sim_ticks 2411694099500 # Number of ticks simulated +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1186264 # Simulator instruction rate (inst/s) +host_tick_rate 35957520604 # Simulator tick rate (ticks/s) +host_mem_usage 417168 # Number of bytes of host memory used +host_seconds 67.07 # Real time elapsed on the host +sim_insts 79563488 # Number of instructions simulated +system.l2c.replacements 127720 # number of replacements +system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use +system.l2c.total_refs 1498989 # Total number of references to valid blocks. +system.l2c.sampled_refs 156132 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.600780 # Average number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 4404.089299 # Average occupied blocks per context +system.l2c.occ_blocks::1 6217.918720 # Average occupied blocks per context +system.l2c.occ_blocks::2 14925.912843 # Average occupied blocks per context +system.l2c.occ_percent::0 0.067201 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.094878 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.227751 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 706190 # number of ReadReq hits +system.l2c.ReadReq_hits::1 499815 # number of ReadReq hits +system.l2c.ReadReq_hits::2 12920 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits +system.l2c.Writeback_hits::0 580461 # number of Writeback hits +system.l2c.Writeback_hits::total 580461 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 776 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 523 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 147 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 202 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 349 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 64831 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 37797 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 102628 # number of ReadExReq hits +system.l2c.demand_hits::0 771021 # number of demand (read+write) hits +system.l2c.demand_hits::1 537612 # number of demand (read+write) hits +system.l2c.demand_hits::2 12920 # number of demand (read+write) hits +system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits +system.l2c.overall_hits::0 771021 # number of overall hits +system.l2c.overall_hits::1 537612 # number of overall hits +system.l2c.overall_hits::2 12920 # number of overall hits +system.l2c.overall_hits::total 1321553 # number of overall hits +system.l2c.ReadReq_misses::0 19675 # number of ReadReq misses +system.l2c.ReadReq_misses::1 15224 # number of ReadReq misses +system.l2c.ReadReq_misses::2 52 # number of ReadReq misses +system.l2c.ReadReq_misses::total 34951 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 6349 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 3492 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 9841 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 791 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 531 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1322 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 99048 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 48785 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 147833 # number of ReadExReq misses +system.l2c.demand_misses::0 118723 # number of demand (read+write) misses +system.l2c.demand_misses::1 64009 # number of demand (read+write) misses +system.l2c.demand_misses::2 52 # number of demand (read+write) misses +system.l2c.demand_misses::total 182784 # number of demand (read+write) misses +system.l2c.overall_misses::0 118723 # number of overall misses +system.l2c.overall_misses::1 64009 # number of overall misses +system.l2c.overall_misses::2 52 # number of overall misses +system.l2c.overall_misses::total 182784 # number of overall misses +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 725865 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 515039 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 12972 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 580461 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 7125 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 4015 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 938 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 733 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1671 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 163879 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 86582 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 250461 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 889744 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 601621 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 12972 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 889744 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 601621 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 12972 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027106 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.029559 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.004009 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.060673 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.891088 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.869738 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.843284 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.724420 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.604397 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.563454 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.133435 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.106394 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.004009 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.243838 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.133435 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.106394 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.004009 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.243838 # miss rate for overall accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks 111818 # number of writebacks +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses +system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 9339288 # DTB read hits +system.cpu0.dtb.read_misses 5153 # DTB read misses +system.cpu0.dtb.write_hits 6907876 # DTB write hits +system.cpu0.dtb.write_misses 1048 # DTB write misses +system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9344441 # DTB read accesses +system.cpu0.dtb.write_accesses 6908924 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 16247164 # DTB hits +system.cpu0.dtb.misses 6201 # DTB misses +system.cpu0.dtb.accesses 16253365 # DTB accesses +system.cpu0.itb.inst_hits 34822552 # ITB inst hits +system.cpu0.itb.inst_misses 2978 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses +system.cpu0.itb.hits 34822552 # DTB hits +system.cpu0.itb.misses 2978 # DTB misses +system.cpu0.itb.accesses 34825530 # DTB accesses +system.cpu0.numCycles 4823340800 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.num_insts 44975797 # Number of instructions executed +system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses +system.cpu0.num_func_calls 1311755 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4494669 # number of instructions that are conditional controls +system.cpu0.num_int_insts 39858123 # number of integer instructions +system.cpu0.num_fp_insts 4945 # number of float instructions +system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read +system.cpu0.num_int_register_writes 42204131 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written +system.cpu0.num_mem_refs 17030946 # number of memory refs +system.cpu0.num_load_insts 9786549 # Number of load instructions +system.cpu0.num_store_insts 7244397 # Number of store instructions +system.cpu0.num_idle_cycles 4777543068.852608 # Number of idle cycles +system.cpu0.num_busy_cycles 45797731.147393 # Number of busy cycles +system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed +system.cpu0.icache.replacements 504460 # number of replacements +system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use +system.cpu0.icache.total_refs 34319155 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.962491 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 511.627588 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.999273 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 34319155 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 34319155 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 34319155 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 34319155 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 34319155 # number of overall hits +system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::total 34319155 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 504973 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 504973 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 504973 # number of overall misses +system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::total 504973 # number of overall misses +system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 34824128 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 34824128 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 34824128 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 34824128 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 34824128 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 34824128 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.014501 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.014501 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::0 0.014501 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks 24728 # number of writebacks +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 380107 # number of replacements +system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use +system.cpu0.dcache.total_refs 14708286 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 38.643068 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::0 479.716402 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.936946 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::0 7803296 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7803296 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 6534059 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6534059 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 172314 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 174866 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 14337355 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 14337355 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 14337355 # number of overall hits +system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::total 14337355 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 237350 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 183580 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 183580 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 9878 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9878 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 7293 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7293 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 420930 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 420930 # number of overall misses +system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::total 420930 # number of overall misses +system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8040646 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8040646 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 6717639 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6717639 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 182192 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 182159 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14758285 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14758285 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14758285 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14758285 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.029519 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.027328 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.054218 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.040036 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.028522 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::0 0.028522 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks 339627 # number of writebacks +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 6258230 # DTB read hits +system.cpu1.dtb.read_misses 2159 # DTB read misses +system.cpu1.dtb.write_hits 4713962 # DTB write hits +system.cpu1.dtb.write_misses 1181 # DTB write misses +system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1498 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6260389 # DTB read accesses +system.cpu1.dtb.write_accesses 4715143 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 10972192 # DTB hits +system.cpu1.dtb.misses 3340 # DTB misses +system.cpu1.dtb.accesses 10975532 # DTB accesses +system.cpu1.itb.inst_hits 27739434 # ITB inst hits +system.cpu1.itb.inst_misses 1388 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 1342 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 27740822 # ITB inst accesses +system.cpu1.itb.hits 27739434 # DTB hits +system.cpu1.itb.misses 1388 # DTB misses +system.cpu1.itb.accesses 27740822 # DTB accesses +system.cpu1.numCycles 4822838236 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.num_insts 34587691 # Number of instructions executed +system.cpu1.num_int_alu_accesses 30998246 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses +system.cpu1.num_func_calls 758024 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3375080 # number of instructions that are conditional controls +system.cpu1.num_int_insts 30998246 # number of integer instructions +system.cpu1.num_fp_insts 5772 # number of float instructions +system.cpu1.num_int_register_reads 156835040 # number of times the integer registers were read +system.cpu1.num_int_register_writes 33469179 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written +system.cpu1.num_mem_refs 11415835 # number of memory refs +system.cpu1.num_load_insts 6478994 # Number of load instructions +system.cpu1.num_store_insts 4936841 # Number of store instructions +system.cpu1.num_idle_cycles 4787960178.177661 # Number of idle cycles +system.cpu1.num_busy_cycles 34878057.822339 # Number of busy cycles +system.cpu1.not_idle_fraction 0.007232 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.992768 # Percentage of idle cycles +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 33011 # number of quiesce instructions executed +system.cpu1.icache.replacements 374406 # number of replacements +system.cpu1.icache.tagsinuse 498.143079 # Cycle average of tags in use +system.cpu1.icache.total_refs 27365572 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 374918 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 72.990819 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 69956143000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 498.143079 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.972936 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 27365572 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 27365572 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 27365572 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 27365572 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 27365572 # number of overall hits +system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::total 27365572 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 374920 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 374920 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 374920 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 374920 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 374920 # number of overall misses +system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::total 374920 # number of overall misses +system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 27740492 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 27740492 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 27740492 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 27740492 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 27740492 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 27740492 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.013515 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.013515 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::0 0.013515 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks 13905 # number of writebacks +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.replacements 247434 # number of replacements +system.cpu1.dcache.tagsinuse 444.903488 # Cycle average of tags in use +system.cpu1.dcache.total_refs 9876826 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 247805 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 39.857251 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 69253206000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 444.903488 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.868952 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 5955973 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5955973 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 3777038 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3777038 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 59593 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 60090 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 9733011 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9733011 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 9733011 # number of overall hits +system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::total 9733011 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 165799 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 165799 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 111467 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 10725 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 10198 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 277266 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 277266 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 277266 # number of overall misses +system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::total 277266 # number of overall misses +system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 6121772 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6121772 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 3888505 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3888505 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 70318 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 70288 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 10010277 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 10010277 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 10010277 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 10010277 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.027083 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.028666 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.152521 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.145089 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.027698 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::0 0.027698 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks 202201 # number of writebacks +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.replacements 0 # number of replacements +system.iocache.tagsinuse 0 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.avg_refs no_value # Average number of references to valid blocks. +system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 0 # number of demand (read+write) misses +system.iocache.demand_misses::total 0 # number of demand (read+write) misses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 0 # number of overall misses +system.iocache.overall_misses::total 0 # number of overall misses +system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 0 # number of overall miss cycles +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks 0 # number of writebacks +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 0 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status new file mode 100644 index 000000000..10632c381 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status @@ -0,0 +1 @@ +build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual FAILED! diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal Binary files differnew file mode 100644 index 000000000..ac162c148 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal |