diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
commit | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (patch) | |
tree | f3dada322d407488b3081a6b9139948b42a610b3 /tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini | |
parent | ccaaa98b4916f730e5eee0cb1d206dca21cb802d (diff) | |
download | gem5-63eb337b3b93ab71ab3157ec6487901d4fc6cda6.tar.xz |
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
Diffstat (limited to 'tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini')
-rw-r--r-- | tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 859778cbe..9699a97a6 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -78,6 +78,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -122,6 +123,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -173,7 +175,7 @@ latency_var=0 null=false range=134217728:268435455 zero=false -port=system.membus.port[2] +port=system.membus.port[1] [system.intrctrl] type=IntrControl @@ -196,6 +198,7 @@ assoc=8 block_size=64 forward_snoops=false hash_delay=1 +is_top_level=false latency=50000 max_miss_count=0 mshrs=20 @@ -227,6 +230,7 @@ assoc=8 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=92 @@ -261,7 +265,7 @@ header_cycles=1 use_default_range=false width=64 default=system.membus.badaddr_responder.pio -port=system.bridge.side_b system.physmem.port[0] system.diskmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side +port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -287,7 +291,7 @@ latency_var=0 null=false range=0:134217727 zero=true -port=system.membus.port[1] +port=system.membus.port[2] [system.realview] type=RealView |