diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:09 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:09 -0500 |
| commit | ba265abbfd70060cc61a3b4a53b4b1cfcb7a96fe (patch) | |
| tree | 5cf148fb600af2da5440a442d10170666ae8bbc9 /tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing | |
| parent | c9d5985b8221459e4737c637910dc08513b05660 (diff) | |
| download | gem5-ba265abbfd70060cc61a3b4a53b4b1cfcb7a96fe.tar.xz | |
ARM: Add some MP regressions and clean up the disk images and kernels a bit
Diffstat (limited to 'tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing')
6 files changed, 547 insertions, 522 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 8d1301d9c..8c21a92dd 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -7,19 +7,20 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 -boot_loader= -boot_loader_mem=Null -boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0 -flags_addr=0 -gic_cpu_addr=0 +boot_loader=/chips/pd/randd/dist/binaries/boot.arm +boot_loader_mem=system.nvmem +boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +flags_addr=268435504 +gic_cpu_addr=520093952 init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux.arm +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -midr_regval=890236928 +memories=system.nvmem system.physmem +midr_regval=890224640 physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -35,7 +36,7 @@ work_item_id=-1 type=Bridge delay=50000 filter_ranges_a=0:18446744073709551615 -filter_ranges_b=0:134217727 +filter_ranges_b=0:268435455 nack_delay=4000 req_size_a=16 req_size_b=16 @@ -45,6 +46,26 @@ write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img +read_only=true + [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts itb tracer @@ -169,16 +190,6 @@ port=system.toL2Bus.port[3] [system.cpu.tracer] type=ExeTracer -[system.diskmem] -type=PhysicalMemory -file=/chips/pd/randd/dist/disks/ael-arm.ext2 -latency=30000 -latency_var=0 -null=false -range=134217728:268435455 -zero=false -port=system.membus.port[1] - [system.intrctrl] type=IntrControl sys=system @@ -195,7 +206,7 @@ port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.p [system.iocache] type=BaseCache -addr_range=0:134217727 +addr_range=0:268435455 assoc=8 block_size=64 forward_snoops=false @@ -223,7 +234,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.port[25] -mem_side=system.membus.port[6] +mem_side=system.membus.port[7] [system.l2c] type=BaseCache @@ -255,7 +266,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.port[0] -mem_side=system.membus.port[7] +mem_side=system.membus.port[8] [system.membus] type=Bus @@ -267,10 +278,11 @@ header_cycles=1 use_default_range=false width=64 default=system.membus.badaddr_responder.pio -port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side +port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake +fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 @@ -285,6 +297,16 @@ update_data=false warn_access=warn pio=system.membus.default +[system.nvmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=2147483648:2214592511 +zero=true +port=system.membus.port[1] + [system.physmem] type=PhysicalMemory file= @@ -297,8 +319,9 @@ port=system.membus.port[2] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl +pci_cfg_base=0 system=system [system.realview.a9scu] @@ -361,12 +384,12 @@ SubsystemVendorID=0 VendorID=32902 config_latency=20000 ctrl_offset=2 -disks= +disks=system.cf0 io_shift=1 max_backoff_delay=10000000 min_backoff_delay=4000 -pci_bus=0 -pci_dev=0 +pci_bus=2 +pci_dev=7 pci_func=0 pio_latency=1000 platform=system.realview @@ -403,6 +426,7 @@ pio=system.iobus.port[9] [system.realview.flash_fake] type=IsaFake +fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 @@ -489,6 +513,7 @@ pio=system.iobus.port[7] [system.realview.l2x0_fake] type=IsaFake +fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 @@ -503,6 +528,18 @@ update_data=false warn_access= pio=system.membus.port[4] +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clock=1000 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=520095232 +pio_latency=1000 +platform=system.realview +system=system +pio=system.membus.port[6] + [system.realview.mmc_fake] type=AmbaFake amba_id=0 @@ -519,7 +556,8 @@ idreg=0 pio_addr=268435456 pio_latency=1000 platform=system.realview -proc_id=201326592 +proc_id0=201326592 +proc_id1=201327138 system=system pio=system.iobus.port[2] diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index a758a5804..9a28ceb37 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -1,35 +1,17 @@ warn: Sockets disabled, not accepting vnc client connections -For more information see: http://www.m5sim.org/warn/af6a84f6 warn: Sockets disabled, not accepting terminal connections -For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: The clidr register always reports 0 caches. -For more information see: http://www.m5sim.org/warn/23a3c326 +warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -For more information see: http://www.m5sim.org/warn/c0c486b8 -warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb warn: The ccsidr register isn't implemented and always reads as 0. -For more information see: http://www.m5sim.org/warn/2c4acb9c +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb -warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr dccmvau' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr icimvau' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb -warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb -warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb +warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -For more information see: http://www.m5sim.org/warn/7998f2ea -warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb -warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb -warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index e8aae375a..8eb08f81f 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,15 +1,12 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 2 2011 15:06:32 -M5 started May 2 2011 15:06:36 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing +gem5 compiled Aug 18 2011 16:54:46 +gem5 started Aug 18 2011 17:16:56 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 114316622000 because m5_exit instruction encountered +Exiting @ tick 2591441692000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 2a2d9df74..6e7850295 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,495 +1,503 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1455036 # Simulator instruction rate (inst/s) -host_mem_usage 382532 # Number of bytes of host memory used -host_seconds 35.16 # Real time elapsed on the host -host_tick_rate 3251070052 # Simulator tick rate (ticks/s) +sim_seconds 2.591442 # Number of seconds simulated +sim_ticks 2591441692000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 51162775 # Number of instructions simulated -sim_seconds 0.114317 # Number of seconds simulated -sim_ticks 114316622000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 100301 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 100301 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14594.610314 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11594.610314 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 95143 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 95143 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 75279000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051425 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 5158 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 5158 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 59805000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051425 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5158 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 7815759 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7815759 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 15651.214184 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12650.891296 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7577286 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7577286 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3732392000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.030512 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 238473 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 238473 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3016896000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030512 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 238473 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38196735000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 100300 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 100300 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 100300 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 100300 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6667481 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6667481 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 40727.618008 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37727.411843 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 6495289 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6495289 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7012970000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.025826 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 172192 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 172192 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 6496358500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025826 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 172192 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 931126000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.469586 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14483240 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14483240 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26165.760413 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23165.486467 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14072575 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14072575 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10745362000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028354 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 410665 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 410665 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9513254500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.028354 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 410665 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 509.189203 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994510 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses::0 14483240 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14483240 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26165.760413 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23165.486467 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14072575 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14072575 # number of overall hits -system.cpu.dcache.overall_miss_latency 10745362000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028354 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 410665 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 410665 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9513254500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.028354 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 410665 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39127861000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 413472 # number of replacements -system.cpu.dcache.sampled_refs 413984 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 509.189203 # Cycle average of tags in use -system.cpu.dcache.total_refs 14269857 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 382812 # number of writebacks -system.cpu.dtb.accesses 15512082 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2208 # Number of entries that have been flushed from TLB +host_inst_rate 610490 # Simulator instruction rate (inst/s) +host_tick_rate 20960550015 # Simulator tick rate (ticks/s) +host_mem_usage 417836 # Number of bytes of host memory used +host_seconds 123.63 # Real time elapsed on the host +sim_insts 75477515 # Number of instructions simulated +system.l2c.replacements 117809 # number of replacements +system.l2c.tagsinuse 24928.376904 # Cycle average of tags in use +system.l2c.total_refs 1535240 # Total number of references to valid blocks. +system.l2c.sampled_refs 146709 # Sample count of references to valid blocks. +system.l2c.avg_refs 10.464525 # Average number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 10331.534348 # Average occupied blocks per context +system.l2c.occ_blocks::1 14596.842556 # Average occupied blocks per context +system.l2c.occ_percent::0 0.157647 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.222730 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1198360 # number of ReadReq hits +system.l2c.ReadReq_hits::1 12495 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1210855 # number of ReadReq hits +system.l2c.Writeback_hits::0 610049 # number of Writeback hits +system.l2c.Writeback_hits::total 610049 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 106473 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106473 # number of ReadExReq hits +system.l2c.demand_hits::0 1304833 # number of demand (read+write) hits +system.l2c.demand_hits::1 12495 # number of demand (read+write) hits +system.l2c.demand_hits::total 1317328 # number of demand (read+write) hits +system.l2c.overall_hits::0 1304833 # number of overall hits +system.l2c.overall_hits::1 12495 # number of overall hits +system.l2c.overall_hits::total 1317328 # number of overall hits +system.l2c.ReadReq_misses::0 31685 # number of ReadReq misses +system.l2c.ReadReq_misses::1 37 # number of ReadReq misses +system.l2c.ReadReq_misses::total 31722 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 2875 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 140928 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140928 # number of ReadExReq misses +system.l2c.demand_misses::0 172613 # number of demand (read+write) misses +system.l2c.demand_misses::1 37 # number of demand (read+write) misses +system.l2c.demand_misses::total 172650 # number of demand (read+write) misses +system.l2c.overall_misses::0 172613 # number of overall misses +system.l2c.overall_misses::1 37 # number of overall misses +system.l2c.overall_misses::total 172650 # number of overall misses +system.l2c.ReadReq_miss_latency 1654516000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 1040000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7338006500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 8992522500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 8992522500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 1230045 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 12532 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1242577 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 610049 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 610049 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2901 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 247401 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247401 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 1477446 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 12532 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1489978 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 1477446 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 12532 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1489978 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.025759 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.002952 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028712 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.991038 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.569634 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.116832 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.002952 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.119784 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.116832 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.002952 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.119784 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52217.642418 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 44716648.648649 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 44768866.291066 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 361.739130 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52069.187812 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::0 52096.438275 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 243041148.648649 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 243093245.086924 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52096.438275 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 243041148.648649 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 243093245.086924 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks 103410 # number of writebacks +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 31722 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 2875 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 140928 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 172650 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 172650 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency 1273844000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 115156000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5646870000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 6920714000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 6920714000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131817513000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 31206766500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 163024279500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.025789 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.531280 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 2.557069 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.991038 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.569634 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::0 0.116857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 13.776732 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 13.893589 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.116857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 13.776732 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 13.893589 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40156.484459 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40054.260870 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40069.184264 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 14970647 # DTB read hits +system.cpu.dtb.read_misses 7343 # DTB read misses +system.cpu.dtb.write_hits 11215605 # DTB write hits +system.cpu.dtb.write_misses 2208 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15506431 # DTB hits +system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 183 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 14977990 # DTB read accesses +system.cpu.dtb.write_accesses 11217813 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5651 # DTB misses -system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 801 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8731607 # DTB read accesses -system.cpu.dtb.read_hits 8726923 # DTB read hits -system.cpu.dtb.read_misses 4684 # DTB read misses -system.cpu.dtb.write_accesses 6780475 # DTB write accesses -system.cpu.dtb.write_hits 6779508 # DTB write hits -system.cpu.dtb.write_misses 967 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41483736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41483736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14791.732049 # average ReadReq miss latency +system.cpu.dtb.hits 26186252 # DTB hits +system.cpu.dtb.misses 9551 # DTB misses +system.cpu.dtb.accesses 26195803 # DTB accesses +system.cpu.itb.inst_hits 60357722 # ITB inst hits +system.cpu.itb.inst_misses 4471 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 60362193 # ITB inst accesses +system.cpu.itb.hits 60357722 # DTB hits +system.cpu.itb.misses 4471 # DTB misses +system.cpu.itb.accesses 60362193 # DTB accesses +system.cpu.numCycles 5182883384 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 75477515 # Number of instructions executed +system.cpu.num_int_alu_accesses 68255270 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses +system.cpu.num_func_calls 1975579 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7580611 # number of instructions that are conditional controls +system.cpu.num_int_insts 68255270 # number of integer instructions +system.cpu.num_fp_insts 10269 # number of float instructions +system.cpu.num_int_register_reads 390835391 # number of times the integer registers were read +system.cpu.num_int_register_writes 72984158 # number of times the integer registers were written +system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written +system.cpu.num_mem_refs 27351734 # number of memory refs +system.cpu.num_load_insts 15632521 # Number of load instructions +system.cpu.num_store_insts 11719213 # Number of store instructions +system.cpu.num_idle_cycles 4574345772.482235 # Number of idle cycles +system.cpu.num_busy_cycles 608537611.517765 # Number of busy cycles +system.cpu.not_idle_fraction 0.117413 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.882587 # Percentage of idle cycles +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 82953 # number of quiesce instructions executed +system.cpu.icache.replacements 852971 # number of replacements +system.cpu.icache.tagsinuse 510.943281 # Cycle average of tags in use +system.cpu.icache.total_refs 59504239 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 853483 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 69.719302 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18512998000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.943281 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.997936 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 59504239 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59504239 # number of ReadReq hits +system.cpu.icache.demand_hits::0 59504239 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59504239 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 59504239 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 59504239 # number of overall hits +system.cpu.icache.ReadReq_misses::0 853483 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 853483 # number of ReadReq misses +system.cpu.icache.demand_misses::0 853483 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 853483 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 853483 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 853483 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 12547128000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 12547128000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 12547128000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 60357722 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60357722 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 60357722 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60357722 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 60357722 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60357722 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.014140 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.014140 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::0 0.014140 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::0 14701.087192 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11790.415195 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 41049747 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41049747 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6419449000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.010462 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 433989 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433989 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 5116910500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010462 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 433989 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.587068 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.demand_avg_miss_latency::0 14701.087192 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14701.087192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41483736 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41483736 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14791.732049 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11790.415195 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 41049747 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41049747 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6419449000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010462 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 433989 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433989 # number of demand (read+write) misses +system.cpu.icache.writebacks 45661 # number of writebacks system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 5116910500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.010462 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 853483 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 853483 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 853483 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 9984295500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9984295500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9984295500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency 350913000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency 350913000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.014140 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.014140 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 433989 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 484.311851 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.945922 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses::0 41483736 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41483736 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14791.732049 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11790.415195 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 41049747 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 41049747 # number of overall hits -system.cpu.icache.overall_miss_latency 6419449000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010462 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 433989 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 433989 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 5116910500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.010462 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.014140 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 433989 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 433477 # number of replacements -system.cpu.icache.sampled_refs 433989 # Sample count of references to valid blocks. +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11698.294518 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 484.311851 # Cycle average of tags in use -system.cpu.icache.total_refs 41049747 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 14247556000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 34328 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41486666 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41483736 # DTB hits -system.cpu.itb.inst_accesses 41486666 # ITB inst accesses -system.cpu.itb.inst_hits 41483736 # ITB inst hits -system.cpu.itb.inst_misses 2930 # ITB inst misses -system.cpu.itb.misses 2930 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 228633244 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 228633244 # Number of busy cycles -system.cpu.num_conditional_control_insts 7015568 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses -system.cpu.num_fp_insts 6058 # number of float instructions -system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written -system.cpu.num_func_calls 1109778 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 51162775 # Number of instructions executed -system.cpu.num_int_alu_accesses 42435662 # Number of integer alu accesses -system.cpu.num_int_insts 42435662 # number of integer instructions -system.cpu.num_int_register_reads 248572490 # number of times the integer registers were read -system.cpu.num_int_register_writes 49713526 # number of times the integer registers were written -system.cpu.num_load_insts 9182978 # Number of load instructions -system.cpu.num_mem_refs 16261071 # number of memory refs -system.cpu.num_store_insts 7078093 # Number of store instructions -system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 626903 # number of replacements +system.cpu.dcache.tagsinuse 511.875592 # Cycle average of tags in use +system.cpu.dcache.total_refs 23615096 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627415 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.638718 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 511.875592 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999757 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 13170367 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13170367 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 9958094 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9958094 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 236142 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236142 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 247592 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247592 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 23128461 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23128461 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 23128461 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 23128461 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 368563 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368563 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 250302 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250302 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 11451 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11451 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::0 618865 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618865 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 618865 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 618865 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5846897000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 9551170500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 186076500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 15398067500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 15398067500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13538930 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13538930 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 10208396 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10208396 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 247593 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 247592 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 23747326 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23747326 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 23747326 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23747326 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.027222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.024519 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.046249 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::0 0.026060 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::0 0.026060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::0 15864.036813 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 38158.586428 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16249.803511 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::0 24881.141283 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 24881.141283 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 564388 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 368563 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 250302 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 11451 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses 618865 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 618865 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 4741074500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8800219500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 151723500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 13541294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 13541294000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 146946835000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 40367455500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 187314290500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.027222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024519 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.046249 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.026060 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.026060 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12863.674596 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35158.406645 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13249.803511 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.replacements 0 # number of replacements +system.iocache.tagsinuse 0 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits system.iocache.demand_misses::0 0 # number of demand (read+write) misses system.iocache.demand_misses::1 0 # number of demand (read+write) misses system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 0 # number of overall misses +system.iocache.overall_misses::total 0 # number of overall misses +system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 0 # number of overall miss cycles +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 0 # number of overall miss cycles +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks 0 # number of writebacks +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 0 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1341941439938 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1341941439938 # number of overall MSHR uncacheable cycles +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 0 # number of replacements -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 0 # number of writebacks -system.l2c.ReadExReq_accesses::0 170353 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 170353 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 62556 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 62556 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5605444000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.632786 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 107797 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107797 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4311880000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.632786 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 107797 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 675448 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 6192 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 681640 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52063.722222 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 42597590.909091 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 42649654.631313 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 657448 # number of ReadReq hits -system.l2c.ReadReq_hits::1 6170 # number of ReadReq hits -system.l2c.ReadReq_hits::total 663618 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 937147000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.026649 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.003553 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.030202 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 18000 # number of ReadReq misses -system.l2c.ReadReq_misses::1 22 # number of ReadReq misses -system.l2c.ReadReq_misses::total 18022 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 720880000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026682 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.910530 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 2.937211 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 18022 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 29204423000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1839 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1839 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 313.940724 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.990756 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 72880000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.990756 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1822 # number of UpgradeReq MSHR misses -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 743252000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 417140 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 417140 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 417140 # number of Writeback hits -system.l2c.Writeback_hits::total 417140 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 7.067586 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 845801 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 6192 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 851993 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52009.117864 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 297390500 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 297442509.117864 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.l2c.demand_hits::0 720004 # number of demand (read+write) hits -system.l2c.demand_hits::1 6170 # number of demand (read+write) hits -system.l2c.demand_hits::total 726174 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6542591000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.148731 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.003553 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.152284 # miss rate for demand accesses -system.l2c.demand_misses::0 125797 # number of demand (read+write) misses -system.l2c.demand_misses::1 22 # number of demand (read+write) misses -system.l2c.demand_misses::total 125819 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5032760000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.148757 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 20.319606 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 20.468363 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 125819 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 5338.058091 # Average occupied blocks per context -system.l2c.occ_blocks::1 31318.757980 # Average occupied blocks per context -system.l2c.occ_percent::0 0.081452 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.477886 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 845801 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 6192 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 851993 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52009.117864 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 297390500 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 297442509.117864 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 720004 # number of overall hits -system.l2c.overall_hits::1 6170 # number of overall hits -system.l2c.overall_hits::total 726174 # number of overall hits -system.l2c.overall_miss_latency 6542591000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.148731 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.003553 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.152284 # miss rate for overall accesses -system.l2c.overall_misses::0 125797 # number of overall misses -system.l2c.overall_misses::1 22 # number of overall misses -system.l2c.overall_misses::total 125819 # number of overall misses -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5032760000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.148757 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 20.319606 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 20.468363 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 125819 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29947675000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 93111 # number of replacements -system.l2c.sampled_refs 124568 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36656.816071 # Cycle average of tags in use -system.l2c.total_refs 880395 # Total number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87350 # number of writebacks +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status index 624e9a5f7..8953751c2 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status @@ -1 +1 @@ -build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED! +build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED! diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal Binary files differindex d2aa844f8..33e436852 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal |