SE/FS: Make both SE and FS tests available all the time.

--HG--
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py
rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE
rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
rename : tests/quick/10.linux-boot/test.py => tests/quick/fs/10.linux-boot/test.py
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
rename : tests/quick/80.netperf-stream/test.py => tests/quick/fs/80.netperf-stream/test.py
rename : tests/quick/00.hello.mp/test.py => tests/quick/se/00.hello.mp/test.py
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
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rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
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rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
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rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
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rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py

10 files changed, 0 insertions, 3941 deletions

diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
deleted file mode 100644
index 91a089b4b..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ /dev/null
@@ -1,1210 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_cpu_frequency=500
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-e820_table=system.e820_table
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-load_addr_mask=18446744073709551615
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-readfile=tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[3]
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[1]
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.dtb_walker_cache.cpu_side
-
-[system.cpu.dtb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dtb.walker.port
-mem_side=system.toL2Bus.port[4]
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu.interrupts]
-type=X86LocalApic
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.itb_walker_cache.cpu_side
-
-[system.cpu.itb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.itb.walker.port
-mem_side=system.toL2Bus.port[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1
-entries=system.e820_table.entries0 system.e820_table.entries1
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-range_type=2
-size=1048576
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=1048576
-range_type=1
-size=133169152
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-id=1
-version=17
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPBus
-bus_id=0
-bus_type=ISA
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=1
-bus_type=PCI
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=16
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=2
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=1
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=3
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=4
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=5
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=6
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=7
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=8
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=9
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=10
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=11
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=12
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=13
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=14
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=0
-parent_bus=1
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=true
-width=64
-default=system.pc.pciconfig.pio
-port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:134217727
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=true
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[21]
-mem_side=system.membus.port[4]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[5]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854779128
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[15]
-
-[system.pc.com_1]
-type=Uart8250
-children=terminal
-pio_addr=9223372036854776824
-pio_latency=1000
-platform=system.pc
-system=system
-terminal=system.pc.com_1.terminal
-pio=system.iobus.port[16]
-
-[system.pc.com_1.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.com_1.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.fake_com_2]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776568
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[17]
-
-[system.pc.fake_com_3]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776808
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[18]
-
-[system.pc.fake_com_4]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776552
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[19]
-
-[system.pc.fake_floppy]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776818
-pio_latency=1000
-pio_size=2
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[20]
-
-[system.pc.i_dont_exist]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854775936
-pio_latency=1000
-pio_size=1
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[14]
-
-[system.pc.pciconfig]
-type=PciConfigAll
-bus=0
-pio_latency=1
-platform=system.pc
-size=16777216
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pio_latency=1000
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-children=int_pin
-int_pin=system.pc.south_bridge.cmos.int_pin
-pio_addr=9223372036854775920
-pio_latency=1000
-platform=system.pc
-system=system
-time=Sun Jan  1 00:00:00 2012
-pio=system.iobus.port[2]
-
-[system.pc.south_bridge.cmos.int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.dma1]
-type=I8237
-pio_addr=9223372036854775808
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[3]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=1000
-platform=system.pc
-system=system
-config=system.iobus.port[5]
-dma=system.iobus.port[6]
-pio=system.iobus.port[4]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.pic1.output
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=0
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.pic2.output
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=2
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.cmos.int_pin
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-number=0
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=0
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.keyboard.keyboard_int_pin
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=1
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.keyboard.mouse_int_pin
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=12
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=1
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.iobus.port[13]
-pio=system.iobus.port[12]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-children=keyboard_int_pin mouse_int_pin
-command_port=9223372036854775908
-data_port=9223372036854775904
-keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
-mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
-pio_addr=0
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[7]
-
-[system.pc.south_bridge.keyboard.keyboard_int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.keyboard.mouse_int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pic1]
-type=I8259
-children=output
-mode=I8259Master
-output=system.pc.south_bridge.pic1.output
-pio_addr=9223372036854775840
-pio_latency=1000
-platform=system.pc
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.port[8]
-
-[system.pc.south_bridge.pic1.output]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pic2]
-type=I8259
-children=output
-mode=I8259Slave
-output=system.pc.south_bridge.pic2.output
-pio_addr=9223372036854775968
-pio_latency=1000
-platform=system.pc
-slave=Null
-system=system
-pio=system.iobus.port[9]
-
-[system.pc.south_bridge.pic2.output]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pit]
-type=I8254
-children=int_pin
-int_pin=system.pc.south_bridge.pit.int_pin
-pio_addr=9223372036854775872
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[10]
-
-[system.pc.south_bridge.pit.int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[11]
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
-
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
deleted file mode 100755
index fd09f1faf..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
+++ /dev/null
@@ -1,9 +0,0 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Reading current count from inactive timer.
-warn: Sockets disabled, not accepting gdb connections
-warn: Don't know what interrupt to clear for console.
-warn: instruction 'fxsave' unimplemented
-warn: Tried to clear PCI interrupt 14
-warn: Unknown mouse command 0xe1.
-warn: instruction 'wbinvd' unimplemented
-hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
deleted file mode 100755
index 23cf47db2..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ /dev/null
@@ -1,13 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:12:17
-gem5 started Jan 23 2012 04:24:46
-gem5 executing on zizzer
-command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-atomic
-warning: add_child('terminal'): child 'terminal' already has parent
-Global frequency set at 1000000000000 ticks per second
-      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5112043255000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
deleted file mode 100644
index 324bf8929..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ /dev/null
@@ -1,553 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  5.112043                       # Number of seconds simulated
-sim_ticks                                5112043255000                       # Number of ticks simulated
-final_tick                               5112043255000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2850135                       # Simulator instruction rate (inst/s)
-host_tick_rate                            35611898535                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 353172                       # Number of bytes of host memory used
-host_seconds                                   143.55                       # Real time elapsed on the host
-sim_insts                                   409133277                       # Number of instructions simulated
-system.physmem.bytes_read                    15568704                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 972736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 12232896                       # Number of bytes written to this memory
-system.physmem.num_reads                       243261                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      191139                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        3045495                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    190283                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       2392956                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       5438452                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        164044                       # number of replacements
-system.l2c.tagsinuse                     36842.944085                       # Cycle average of tags in use
-system.l2c.total_refs                         3332458                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        196390                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         16.968573                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                  9701.563280                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 27141.380805                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.148034                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.414145                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    2042917                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                       9538                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2052455                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                  1529403                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1529403                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                      31                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  31                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                   168948                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               168948                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     2211865                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                        9538                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2221403                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    2211865                       # number of overall hits
-system.l2c.overall_hits::1                       9538                       # number of overall hits
-system.l2c.overall_hits::total                2221403                       # number of overall hits
-system.l2c.ReadReq_misses::0                    55972                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       27                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                55999                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  1792                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1792                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 144639                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             144639                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    200611                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        27                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                200638                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   200611                       # number of overall misses
-system.l2c.overall_misses::1                       27                       # number of overall misses
-system.l2c.overall_misses::total               200638                       # number of overall misses
-system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2098889                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                   9565                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2108454                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0              1529403                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1529403                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                1823                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1823                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               313587                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           313587                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2412476                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                    9565                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2422041                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2412476                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                   9565                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2422041                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.026667                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.002823                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.029490                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.982995                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.461240                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.083156                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.002823                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.085978                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.083156                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.002823                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.085978                       # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total            0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total            0                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          144472                       # number of writebacks
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total             0                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total            0                       # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     47570                       # number of replacements
-system.iocache.tagsinuse                     0.042409                       # Cycle average of tags in use
-system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47586                       # Sample count of references to valid blocks.
-system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              4994776740009                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 0.042409                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.002651                       # Average percentage of cache occupancy
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  905                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              905                       # number of ReadReq misses
-system.iocache.WriteReq_misses::1               46720                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 47625                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47625                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                47625                       # number of overall misses
-system.iocache.overall_misses::total            47625                       # number of overall misses
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                905                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            905                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1             46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               47625                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47625                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              47625                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47625                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       46667                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             0                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                      10224086531                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        409133277                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             374297244                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     39954968                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    374297244                       # number of integer instructions
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           801267455                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          401624559                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      35626519                       # number of memory refs
-system.cpu.num_load_insts                    27217784                       # Number of load instructions
-system.cpu.num_store_insts                    8408735                       # Number of store instructions
-system.cpu.num_idle_cycles               9770605338.086651                       # Number of idle cycles
-system.cpu.num_busy_cycles               453481192.913350                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.044354                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.955646                       # Percentage of idle cycles
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.icache.replacements                 790795                       # number of replacements
-system.cpu.icache.tagsinuse                510.627676                       # Cycle average of tags in use
-system.cpu.icache.total_refs                243365777                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 791307                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 307.549127                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle           148763105500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            510.627676                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.997320                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0           243365777                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       243365777                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0            243365777                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        243365777                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0           243365777                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total       243365777                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0            791314                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        791314                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0             791314                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         791314                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0            791314                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total        791314                       # number of overall misses
-system.cpu.icache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0       244157091                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    244157091                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0        244157091                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    244157091                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0       244157091                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    244157091                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.003241                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.003241                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.003241                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                      809                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses               0                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements         3435                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        3.021701                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs           7940                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs         3444                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         2.305459                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5105275407500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::1     3.021701                       # Average occupied blocks per context
-system.cpu.itb_walker_cache.occ_percent::1     0.188856                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::1         7947                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total         7947                       # number of ReadReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::1            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::1         7949                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total         7949                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::1         7949                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total         7949                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::1         4278                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         4278                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::1         4278                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         4278                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::1         4278                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         4278                       # number of overall misses
-system.cpu.itb_walker_cache.demand_miss_latency            0                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency            0                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::1        12225                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        12225                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::1            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::1        12227                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        12227                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::1        12227                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        12227                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.349939                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::1     0.349881                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::1     0.349881                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
-system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks            518                       # number of writebacks
-system.cpu.itb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
-system.cpu.itb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.itb_walker_cache.demand_mshr_misses            0                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses            0                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.itb_walker_cache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::0     no_value                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::1            0                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
-system.cpu.itb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements         7755                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse        5.010998                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs          12854                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs         7767                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.654950                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5101232849000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::1     5.010998                       # Average occupied blocks per context
-system.cpu.dtb_walker_cache.occ_percent::1     0.313187                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::1        12875                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        12875                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::1        12875                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        12875                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1        12875                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        12875                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::1         8933                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total         8933                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::1         8933                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total         8933                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1         8933                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total         8933                       # number of overall misses
-system.cpu.dtb_walker_cache.demand_miss_latency            0                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency            0                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::1        21808                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        21808                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::1        21808                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        21808                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::1        21808                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        21808                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.409620                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::1     0.409620                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1     0.409620                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
-system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks           2517                       # number of writebacks
-system.cpu.dtb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
-system.cpu.dtb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.dtb_walker_cache.demand_mshr_misses            0                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses            0                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0     no_value                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1            0                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
-system.cpu.dtb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1621277                       # number of replacements
-system.cpu.dcache.tagsinuse                511.999417                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 20142220                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1621789                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  12.419754                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                7549500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.999417                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999999                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0            12057024                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        12057024                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            8082938                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8082938                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::0             20139962                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20139962                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            20139962                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20139962                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0           1308207                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1308207                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0           315850                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       315850                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::0            1624057                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1624057                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           1624057                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1624057                       # number of overall misses
-system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0        13365231                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13365231                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        8398788                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8398788                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         21764019                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21764019                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        21764019                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21764019                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.097881                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.037607                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.074621                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.074621                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1525559                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses               0                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
deleted file mode 100644
index ab8215fe1..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
+++ /dev/null
@@ -1,133 +0,0 @@
-Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007

-Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

-BIOS-provided physical RAM map:

- BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)

- BIOS-e820: 0000000000100000 - 0000000008000000 (usable)

-end_pfn_map = 32768

-kernel direct mapping tables up to 8000000 @ 100000-102000

-DMI 2.5 present.

-Zone PFN ranges:

-  DMA           256 ->     4096

-  DMA32        4096 ->  1048576

-  Normal    1048576 ->  1048576

-early_node_map[1] active PFN ranges

-    0:      256 ->    32768

-Intel MultiProcessor Specification v1.4

-MPTABLE: OEM ID:  MPTABLE: Product ID:  MPTABLE: APIC at: 0xFEE00000

-Processor #0 (Bootup-CPU)

-I/O APIC #1 at 0xFEC00000.

-Setting APIC routing to flat

-Processors: 1

-Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)

-Built 1 zonelists.  Total pages: 30458

-Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

-Initializing CPU#0

-PID hash table entries: 512 (order: 9, 4096 bytes)

-time.c: Detected 1999.998 MHz processor.

-Console: colour dummy device 80x25

-console handover: boot [earlyser0] -> real [ttyS0]

-Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)

-Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)

-Checking aperture...

-Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)

-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset

-Mount-cache hash table entries: 256

-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)

-CPU: L2 Cache: 1024K (64 bytes/line)

-CPU: Fake M5 x86_64 CPU stepping 01

-ACPI: Core revision 20070126

-ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]

-ACPI: Unable to load the System Description Tables

-Using local APIC timer interrupts.

-result 7812490

-Detected 7.812 MHz APIC timer.

-NET: Registered protocol family 16

-PCI: Using configuration type 1

-ACPI: Interpreter disabled.

-Linux Plug and Play Support v0.97 (c) Adam Belay

-pnp: PnP ACPI: disabled

-SCSI subsystem initialized

-usbcore: registered new interface driver usbfs

-usbcore: registered new interface driver hub

-usbcore: registered new device driver usb

-PCI: Probing PCI hardware

-PCI-GART: No AMD northbridge found.

-NET: Registered protocol family 2

-Time: tsc clocksource has been installed.

-IP route cache hash table entries: 1024 (order: 1, 8192 bytes)

-TCP established hash table entries: 4096 (order: 4, 65536 bytes)

-TCP bind hash table entries: 4096 (order: 3, 32768 bytes)

-TCP: Hash tables configured (established 4096 bind 4096)

-TCP reno registered

-Total HugeTLB memory allocated, 0

-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).

-io scheduler noop registered

-io scheduler deadline registered

-io scheduler cfq registered (default)

-Real Time Clock Driver v1.12ac

-Linux agpgart interface v0.102 (c) Dave Jones

-Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled

-serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250

-floppy0: no floppy controllers found

-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize

-loop: module loaded

-Intel(R) PRO/1000 Network Driver - version 7.3.20-k2

-Copyright (c) 1999-2006 Intel Corporation.

-e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI

-e100: Copyright(c) 1999-2006 Intel Corporation

-forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.

-tun: Universal TUN/TAP device driver, 1.6

-tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>

-netconsole: not configured, aborting

-Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2

-ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx

-PIIX4: IDE controller at PCI slot 0000:00:04.0

-PCI: Enabling device 0000:00:04.0 (0000 -> 0001)

-PIIX4: chipset revision 0

-PIIX4: not 100% native mode: will probe irqs later

-    ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA

-    ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA

-hda: M5 IDE Disk, ATA DISK drive

-hdb: M5 IDE Disk, ATA DISK drive

-ide0 at 0x1f0-0x1f7,0x3f6 on irq 14

-hda: max request size: 128KiB

-hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)

- hda: hda1

-hdb: max request size: 128KiB

-hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)

- hdb: unknown partition table

-megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)

-megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)

-megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007

-Fusion MPT base driver 3.04.04

-Copyright (c) 1999-2007 LSI Logic Corporation

-Fusion MPT SPI Host driver 3.04.04

-Fusion MPT SAS Host driver 3.04.04

-ieee1394: raw1394: /dev/raw1394 device initialized

-USB Universal Host Controller Interface driver v3.0

-usbcore: registered new interface driver usblp

-drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver

-Initializing USB Mass Storage driver...

-usbcore: registered new interface driver usb-storage

-USB Mass Storage support registered.

-PNP: No PS/2 controller found. Probing ports directly.

-serio: i8042 KBD port at 0x60,0x64 irq 1

-serio: i8042 AUX port at 0x60,0x64 irq 12

-mice: PS/2 mouse device common for all mice

-input: AT Translated Set 2 keyboard as /class/input/input0

-device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com

-input: PS/2 Generic Mouse as /class/input/input1

-usbcore: registered new interface driver usbhid

-drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver

-oprofile: using timer interrupt.

-TCP cubic registered

-NET: Registered protocol family 1

-NET: Registered protocol family 10

-IPv6 over IPv4 tunneling driver

-NET: Registered protocol family 17

-EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended

-VFS: Mounted root (ext2 filesystem).

-Freeing unused kernel memory: 232k freed

-
INIT: version 2.86 booting


-mounting filesystems...

-loading script...

diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
deleted file mode 100644
index e3a339662..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ /dev/null
@@ -1,1207 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_cpu_frequency=500
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-e820_table=system.e820_table
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-load_addr_mask=18446744073709551615
-mem_mode=timing
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-readfile=tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[3]
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[1]
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-system=system
-tracer=system.cpu.tracer
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.dtb_walker_cache.cpu_side
-
-[system.cpu.dtb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dtb.walker.port
-mem_side=system.toL2Bus.port[4]
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu.interrupts]
-type=X86LocalApic
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.itb_walker_cache.cpu_side
-
-[system.cpu.itb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.itb.walker.port
-mem_side=system.toL2Bus.port[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1
-entries=system.e820_table.entries0 system.e820_table.entries1
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-range_type=2
-size=1048576
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=1048576
-range_type=1
-size=133169152
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-id=1
-version=17
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPBus
-bus_id=0
-bus_type=ISA
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=1
-bus_type=PCI
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=16
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=2
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=1
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=3
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=4
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=5
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=6
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=7
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=8
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=9
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=10
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=11
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=12
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=13
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=14
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=0
-parent_bus=1
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=true
-width=64
-default=system.pc.pciconfig.pio
-port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:134217727
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=false
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[21]
-mem_side=system.membus.port[4]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[5]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854779128
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[15]
-
-[system.pc.com_1]
-type=Uart8250
-children=terminal
-pio_addr=9223372036854776824
-pio_latency=1000
-platform=system.pc
-system=system
-terminal=system.pc.com_1.terminal
-pio=system.iobus.port[16]
-
-[system.pc.com_1.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.com_1.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.fake_com_2]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776568
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[17]
-
-[system.pc.fake_com_3]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776808
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[18]
-
-[system.pc.fake_com_4]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776552
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[19]
-
-[system.pc.fake_floppy]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776818
-pio_latency=1000
-pio_size=2
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[20]
-
-[system.pc.i_dont_exist]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854775936
-pio_latency=1000
-pio_size=1
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[14]
-
-[system.pc.pciconfig]
-type=PciConfigAll
-bus=0
-pio_latency=1
-platform=system.pc
-size=16777216
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pio_latency=1000
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-children=int_pin
-int_pin=system.pc.south_bridge.cmos.int_pin
-pio_addr=9223372036854775920
-pio_latency=1000
-platform=system.pc
-system=system
-time=Sun Jan  1 00:00:00 2012
-pio=system.iobus.port[2]
-
-[system.pc.south_bridge.cmos.int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.dma1]
-type=I8237
-pio_addr=9223372036854775808
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[3]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=1000
-platform=system.pc
-system=system
-config=system.iobus.port[5]
-dma=system.iobus.port[6]
-pio=system.iobus.port[4]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.pic1.output
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=0
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.pic2.output
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=2
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.cmos.int_pin
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-number=0
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=0
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.keyboard.keyboard_int_pin
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=1
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.keyboard.mouse_int_pin
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=12
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=1
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.iobus.port[13]
-pio=system.iobus.port[12]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-children=keyboard_int_pin mouse_int_pin
-command_port=9223372036854775908
-data_port=9223372036854775904
-keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
-mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
-pio_addr=0
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[7]
-
-[system.pc.south_bridge.keyboard.keyboard_int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.keyboard.mouse_int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pic1]
-type=I8259
-children=output
-mode=I8259Master
-output=system.pc.south_bridge.pic1.output
-pio_addr=9223372036854775840
-pio_latency=1000
-platform=system.pc
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.port[8]
-
-[system.pc.south_bridge.pic1.output]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pic2]
-type=I8259
-children=output
-mode=I8259Slave
-output=system.pc.south_bridge.pic2.output
-pio_addr=9223372036854775968
-pio_latency=1000
-platform=system.pc
-slave=Null
-system=system
-pio=system.iobus.port[9]
-
-[system.pc.south_bridge.pic2.output]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pit]
-type=I8254
-children=int_pin
-int_pin=system.pc.south_bridge.pit.int_pin
-pio_addr=9223372036854775872
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[10]
-
-[system.pc.south_bridge.pit.int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[11]
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
-
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
deleted file mode 100755
index fd09f1faf..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
+++ /dev/null
@@ -1,9 +0,0 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Reading current count from inactive timer.
-warn: Sockets disabled, not accepting gdb connections
-warn: Don't know what interrupt to clear for console.
-warn: instruction 'fxsave' unimplemented
-warn: Tried to clear PCI interrupt 14
-warn: Unknown mouse command 0xe1.
-warn: instruction 'wbinvd' unimplemented
-hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
deleted file mode 100755
index 5dde537a2..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ /dev/null
@@ -1,13 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:12:17
-gem5 started Jan 23 2012 04:24:49
-gem5 executing on zizzer
-command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-timing
-warning: add_child('terminal'): child 'terminal' already has parent
-Global frequency set at 1000000000000 ticks per second
-      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5195470393000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
deleted file mode 100644
index c4a248e5e..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ /dev/null
@@ -1,661 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  5.195470                       # Number of seconds simulated
-sim_ticks                                5195470393000                       # Number of ticks simulated
-final_tick                               5195470393000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1681123                       # Simulator instruction rate (inst/s)
-host_tick_rate                            32940960656                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 349824                       # Number of bytes of host memory used
-host_seconds                                   157.72                       # Real time elapsed on the host
-sim_insts                                   265147881                       # Number of instructions simulated
-system.physmem.bytes_read                    13764096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 974400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10427072                       # Number of bytes written to this memory
-system.physmem.num_reads                       215064                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      162923                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        2649249                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    187548                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       2006954                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       4656204                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        136133                       # number of replacements
-system.l2c.tagsinuse                     31389.895470                       # Cycle average of tags in use
-system.l2c.total_refs                         3363370                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        168244                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         19.991025                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                  7910.895776                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 23478.999694                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.120711                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.358261                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    2047882                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                       9561                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2057443                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                  1534567                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1534567                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     320                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 320                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                   192958                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               192958                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     2240840                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                        9561                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2250401                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    2240840                       # number of overall hits
-system.l2c.overall_hits::1                       9561                       # number of overall hits
-system.l2c.overall_hits::total                2250401                       # number of overall hits
-system.l2c.ReadReq_misses::0                    50807                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       23                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                50830                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  1369                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1369                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 120168                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             120168                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    170975                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        23                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                170998                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   170975                       # number of overall misses
-system.l2c.overall_misses::1                       23                       # number of overall misses
-system.l2c.overall_misses::total               170998                       # number of overall misses
-system.l2c.ReadReq_miss_latency            2656122500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency           33778000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          6249324500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency             8905447000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency            8905447000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2098689                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                   9584                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2108273                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0              1534567                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1534567                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                1689                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1689                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               313126                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           313126                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2411815                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                    9584                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2421399                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2411815                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                   9584                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2421399                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.024209                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.002400                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.026609                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.810539                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.383769                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.070891                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.002400                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.073290                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.070891                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.002400                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.073290                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52278.672230                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   115483586.956522                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 115535865.628752                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 24673.484295                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52004.897310                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    52086.252376                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    387193347.826087                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 387245434.078463                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   52086.252376                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   387193347.826087                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 387245434.078463                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          116255                       # number of writebacks
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                  50830                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                1369                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               120168                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  170998                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 170998                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency       2046144000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency      55109000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     4807305000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency        6853449000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency       6853449000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency  56051785000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1218050000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency  57269835000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.024220                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         5.303631                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     5.327851                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.810539                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.383769                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.070900                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1         17.842028                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total     17.912929                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.070900                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1        17.842028                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total    17.912929                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40254.652764                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40254.930606                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40004.868185                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40079.117884                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40079.117884                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     47510                       # number of replacements
-system.iocache.tagsinuse                     0.120586                       # Cycle average of tags in use
-system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47526                       # Sample count of references to valid blocks.
-system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              5048756072000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 0.120586                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.007537                       # Average percentage of cache occupancy
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  844                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              844                       # number of ReadReq misses
-system.iocache.WriteReq_misses::1               46720                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 47564                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47564                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                47564                       # number of overall misses
-system.iocache.overall_misses::total            47564                       # number of overall misses
-system.iocache.ReadReq_miss_latency         106575932                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency       6391379160                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency         6497955092                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency        6497955092                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                844                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            844                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1             46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               47564                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47564                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              47564                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47564                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 126274.800948                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 136801.779966                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 136614.983853                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 136614.983853                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      69564644                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                11299                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  6156.708027                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       46668                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses                844                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses             46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses               47564                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses              47564                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency     62666978                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency   3961676998                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency    4024343976                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency   4024343976                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 74249.973934                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 84796.168622                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 84609.031536                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 84609.031536                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                      10390940786                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        265147881                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             249556386                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     24882695                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    249556386                       # number of integer instructions
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           543487907                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          266037487                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      23169904                       # number of memory refs
-system.cpu.num_load_insts                    14812525                       # Number of load instructions
-system.cpu.num_store_insts                    8357379                       # Number of store instructions
-system.cpu.num_idle_cycles               9787777240.878117                       # Number of idle cycles
-system.cpu.num_busy_cycles               603163545.121884                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.058047                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.941953                       # Percentage of idle cycles
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.icache.replacements                 788139                       # number of replacements
-system.cpu.icache.tagsinuse                510.361283                       # Cycle average of tags in use
-system.cpu.icache.total_refs                158433932                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 788651                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 200.892324                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle           160047116000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            510.361283                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.996799                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0           158433932                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       158433932                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0            158433932                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        158433932                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0           158433932                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total       158433932                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0            788658                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        788658                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0             788658                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         788658                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0            788658                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total        788658                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency    11681762500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency     11681762500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency    11681762500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0       159222590                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    159222590                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0        159222590                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    159222590                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0       159222590                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    159222590                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.004953                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.004953                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.004953                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14812.203135                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14812.203135                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14812.203135                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                      805                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses          788658                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses           788658                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses          788658                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency   9314744000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency   9314744000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency   9314744000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.004953                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.004953                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.004953                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11810.878733                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11810.878733                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11810.878733                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements         3754                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        3.070606                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs           7549                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs         3765                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         2.005046                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5178573163000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::1     3.070606                       # Average occupied blocks per context
-system.cpu.itb_walker_cache.occ_percent::1     0.191913                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::1         7619                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total         7619                       # number of ReadReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::1            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::1         7621                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total         7621                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::1         7621                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total         7621                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::1         4602                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         4602                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::1         4602                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         4602                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::1         4602                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         4602                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency     50817000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency     50817000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency     50817000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::1        12221                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        12221                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::1            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::1        12223                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        12223                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::1        12223                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        12223                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.376565                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::1     0.376503                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::1     0.376503                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 11042.372881                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::1 11042.372881                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::1 11042.372881                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
-system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks            826                       # number of writebacks
-system.cpu.itb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
-system.cpu.itb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.itb_walker_cache.ReadReq_mshr_misses         4602                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses         4602                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses         4602                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency     37011000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency     37011000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency     37011000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1     0.376565                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::1     0.376503                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::1     0.376503                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency  8042.372881                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency  8042.372881                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency  8042.372881                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
-system.cpu.itb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements         7704                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse        5.052403                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs          13051                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs         7716                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.691420                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5160674969000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::1     5.052403                       # Average occupied blocks per context
-system.cpu.dtb_walker_cache.occ_percent::1     0.315775                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::1        13051                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        13051                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::1        13051                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        13051                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1        13051                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        13051                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::1         8896                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total         8896                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::1         8896                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total         8896                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1         8896                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total         8896                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency    103895500                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency    103895500                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency    103895500                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::1        21947                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        21947                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::1        21947                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        21947                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::1        21947                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        21947                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.405340                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::1     0.405340                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1     0.405340                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 11678.900629                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 11678.900629                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 11678.900629                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
-system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks           2985                       # number of writebacks
-system.cpu.dtb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
-system.cpu.dtb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses         8896                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses         8896                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses         8896                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency     77207000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency     77207000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency     77207000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1     0.405340                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1     0.405340                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1     0.405340                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency  8678.844424                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency  8678.844424                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency  8678.844424                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
-system.cpu.dtb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1623424                       # number of replacements
-system.cpu.dcache.tagsinuse                511.997312                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 20011404                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1623936                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  12.322779                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               44345000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.997312                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999995                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0            11977182                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11977182                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            8032009                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8032009                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::0             20009191                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20009191                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            20009191                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20009191                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0           1310824                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1310824                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0           315344                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       315344                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::0            1626168                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1626168                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           1626168                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1626168                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    19851809000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    9514837000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     29366646000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    29366646000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0        13288006                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13288006                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        8347353                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8347353                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         21635359                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21635359                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        21635359                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21635359                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.098647                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.037778                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.075163                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.075163                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15144.526649                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 30172.881044                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 18058.802043                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 18058.802043                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1529951                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1310824                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         315344                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1626168                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1626168                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  15919294500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   8568794500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  24488089000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  24488089000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency  75925324500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1379728500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency  77305053000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.098647                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.037778                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.075163                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.075163                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12144.494227                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27172.847747                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 15058.769451                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 15058.769451                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
deleted file mode 100644
index a1c03790e..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
+++ /dev/null
@@ -1,133 +0,0 @@
-Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007

-Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

-BIOS-provided physical RAM map:

- BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)

- BIOS-e820: 0000000000100000 - 0000000008000000 (usable)

-end_pfn_map = 32768

-kernel direct mapping tables up to 8000000 @ 100000-102000

-DMI 2.5 present.

-Zone PFN ranges:

-  DMA           256 ->     4096

-  DMA32        4096 ->  1048576

-  Normal    1048576 ->  1048576

-early_node_map[1] active PFN ranges

-    0:      256 ->    32768

-Intel MultiProcessor Specification v1.4

-MPTABLE: OEM ID:  MPTABLE: Product ID:  MPTABLE: APIC at: 0xFEE00000

-Processor #0 (Bootup-CPU)

-I/O APIC #1 at 0xFEC00000.

-Setting APIC routing to flat

-Processors: 1

-Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)

-Built 1 zonelists.  Total pages: 30458

-Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

-Initializing CPU#0

-PID hash table entries: 512 (order: 9, 4096 bytes)

-time.c: Detected 1999.998 MHz processor.

-Console: colour dummy device 80x25

-console handover: boot [earlyser0] -> real [ttyS0]

-Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)

-Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)

-Checking aperture...

-Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)

-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset

-Mount-cache hash table entries: 256

-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)

-CPU: L2 Cache: 1024K (64 bytes/line)

-CPU: Fake M5 x86_64 CPU stepping 01

-ACPI: Core revision 20070126

-ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]

-ACPI: Unable to load the System Description Tables

-Using local APIC timer interrupts.

-result 7812489

-Detected 7.812 MHz APIC timer.

-NET: Registered protocol family 16

-PCI: Using configuration type 1

-ACPI: Interpreter disabled.

-Linux Plug and Play Support v0.97 (c) Adam Belay

-pnp: PnP ACPI: disabled

-SCSI subsystem initialized

-usbcore: registered new interface driver usbfs

-usbcore: registered new interface driver hub

-usbcore: registered new device driver usb

-PCI: Probing PCI hardware

-PCI-GART: No AMD northbridge found.

-Time: tsc clocksource has been installed.

-NET: Registered protocol family 2

-IP route cache hash table entries: 1024 (order: 1, 8192 bytes)

-TCP established hash table entries: 4096 (order: 4, 65536 bytes)

-TCP bind hash table entries: 4096 (order: 3, 32768 bytes)

-TCP: Hash tables configured (established 4096 bind 4096)

-TCP reno registered

-Total HugeTLB memory allocated, 0

-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).

-io scheduler noop registered

-io scheduler deadline registered

-io scheduler cfq registered (default)

-Real Time Clock Driver v1.12ac

-Linux agpgart interface v0.102 (c) Dave Jones

-Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled

-serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250

-floppy0: no floppy controllers found

-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize

-loop: module loaded

-Intel(R) PRO/1000 Network Driver - version 7.3.20-k2

-Copyright (c) 1999-2006 Intel Corporation.

-e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI

-e100: Copyright(c) 1999-2006 Intel Corporation

-forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.

-tun: Universal TUN/TAP device driver, 1.6

-tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>

-netconsole: not configured, aborting

-Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2

-ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx

-PIIX4: IDE controller at PCI slot 0000:00:04.0

-PCI: Enabling device 0000:00:04.0 (0000 -> 0001)

-PIIX4: chipset revision 0

-PIIX4: not 100% native mode: will probe irqs later

-    ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA

-    ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA

-hda: M5 IDE Disk, ATA DISK drive

-hdb: M5 IDE Disk, ATA DISK drive

-ide0 at 0x1f0-0x1f7,0x3f6 on irq 14

-hda: max request size: 128KiB

-hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)

- hda: hda1

-hdb: max request size: 128KiB

-hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)

- hdb: unknown partition table

-megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)

-megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)

-megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007

-Fusion MPT base driver 3.04.04

-Copyright (c) 1999-2007 LSI Logic Corporation

-Fusion MPT SPI Host driver 3.04.04

-Fusion MPT SAS Host driver 3.04.04

-ieee1394: raw1394: /dev/raw1394 device initialized

-USB Universal Host Controller Interface driver v3.0

-usbcore: registered new interface driver usblp

-drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver

-Initializing USB Mass Storage driver...

-usbcore: registered new interface driver usb-storage

-USB Mass Storage support registered.

-PNP: No PS/2 controller found. Probing ports directly.

-serio: i8042 KBD port at 0x60,0x64 irq 1

-serio: i8042 AUX port at 0x60,0x64 irq 12

-mice: PS/2 mouse device common for all mice

-input: AT Translated Set 2 keyboard as /class/input/input0

-device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com

-input: PS/2 Generic Mouse as /class/input/input1

-usbcore: registered new interface driver usbhid

-drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver

-oprofile: using timer interrupt.

-TCP cubic registered

-NET: Registered protocol family 1

-NET: Registered protocol family 10

-IPv6 over IPv4 tunneling driver

-NET: Registered protocol family 17

-EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended

-VFS: Mounted root (ext2 filesystem).

-Freeing unused kernel memory: 232k freed

-
INIT: version 2.86 booting


-mounting filesystems...

-loading script...