tests: update stats for name changes

6 files changed, 42 insertions, 34 deletions

diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index 46cc1ee8d..1f83b404b 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -99,6 +99,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -141,6 +142,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -172,6 +174,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -224,6 +227,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -632,6 +636,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -663,6 +668,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index 3d2440746..b12d01305 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 26 2011 16:13:31
-M5 revision 412ef0f728a5 8092 default qtip tip updatefsstats.patch
-M5 started Feb 26 2011 16:13:35
-M5 executing on burrito
-command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic
+M5 compiled Apr 19 2011 12:44:38
+M5 started Apr 19 2011 12:44:44
+M5 executing on maize
+command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5112051446000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 432acc1f0..d1e2ef704 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2446370                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 368136                       # Number of bytes of host memory used
-host_seconds                                   166.22                       # Real time elapsed on the host
-host_tick_rate                            30755543746                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3814417                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 349920                       # Number of bytes of host memory used
+host_seconds                                   106.60                       # Real time elapsed on the host
+host_tick_rate                            47954478135                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   406624458                       # Number of instructions simulated
 sim_seconds                                  5.112051                       # Number of seconds simulated
@@ -56,8 +56,8 @@ system.cpu.dcache.demand_mshr_misses                0                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999999                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            511.999375                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999999                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses::0        21771105                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     21771105                       # number of overall (read+write) accesses
@@ -132,8 +132,8 @@ system.cpu.dtb_walker_cache.demand_mshr_misses            0
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.occ_%::1         0.313148                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.occ_blocks::1     5.010366                       # Average occupied blocks per context
+system.cpu.dtb_walker_cache.occ_percent::1     0.313148                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::1        21821                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::total        21821                       # number of overall (read+write) accesses
@@ -208,8 +208,8 @@ system.cpu.icache.demand_mshr_misses                0                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.997320                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            510.627884                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.997320                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses::0       254189385                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    254189385                       # number of overall (read+write) accesses
@@ -289,8 +289,8 @@ system.cpu.itb_walker_cache.demand_mshr_misses            0
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.occ_%::1         0.188799                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.occ_blocks::1     3.020778                       # Average occupied blocks per context
+system.cpu.itb_walker_cache.occ_percent::1     0.188799                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::1        12219                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::total        12219                       # number of overall (read+write) accesses
@@ -390,8 +390,8 @@ system.iocache.demand_mshr_misses                   0                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.002653                       # Average percentage of cache occupancy
 system.iocache.occ_blocks::1                 0.042448                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.002653                       # Average percentage of cache occupancy
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              47629                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          47629                       # number of overall (read+write) accesses
@@ -489,10 +489,10 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.147971                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.414180                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                  9697.448079                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                 27143.733047                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.147971                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.414180                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                2414301                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                  10262                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2424563                       # number of overall (read+write) accesses
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 0541c10f2..f05a137d3 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -96,6 +96,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -138,6 +139,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -169,6 +171,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -221,6 +224,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -629,6 +633,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=false
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -660,6 +665,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index 62b97bfb9..f1baa96ff 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 26 2011 16:13:31
-M5 revision 412ef0f728a5 8092 default qtip tip updatefsstats.patch
-M5 started Feb 26 2011 16:13:35
-M5 executing on burrito
-command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing
+M5 compiled Apr 19 2011 12:44:38
+M5 started Apr 19 2011 12:46:29
+M5 executing on maize
+command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5195470393000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 8b571b3ea..5e1d5b2a8 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1546136                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 364716                       # Number of bytes of host memory used
-host_seconds                                   170.97                       # Real time elapsed on the host
-host_tick_rate                            30388572127                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2432424                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 346476                       # Number of bytes of host memory used
+host_seconds                                   108.67                       # Real time elapsed on the host
+host_tick_rate                            47808116930                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   264339287                       # Number of instructions simulated
 sim_seconds                                  5.195470                       # Number of seconds simulated
@@ -80,8 +80,8 @@ system.cpu.dcache.demand_mshr_misses          1626168                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999995                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            511.997312                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999995                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses::0        21635359                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     21635359                       # number of overall (read+write) accesses
@@ -166,8 +166,8 @@ system.cpu.dtb_walker_cache.demand_mshr_misses         8896
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.occ_%::1         0.315775                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.occ_blocks::1     5.052403                       # Average occupied blocks per context
+system.cpu.dtb_walker_cache.occ_percent::1     0.315775                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::1        21947                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::total        21947                       # number of overall (read+write) accesses
@@ -252,8 +252,8 @@ system.cpu.icache.demand_mshr_misses           788658                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.996799                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            510.361283                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.996799                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses::0       159222590                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    159222590                       # number of overall (read+write) accesses
@@ -343,8 +343,8 @@ system.cpu.itb_walker_cache.demand_mshr_misses         4602
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.occ_%::1         0.191913                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.occ_blocks::1     3.070606                       # Average occupied blocks per context
+system.cpu.itb_walker_cache.occ_percent::1     0.191913                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::1        12223                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::total        12223                       # number of overall (read+write) accesses
@@ -464,8 +464,8 @@ system.iocache.demand_mshr_misses               47564                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.007537                       # Average percentage of cache occupancy
 system.iocache.occ_blocks::1                 0.120586                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.007537                       # Average percentage of cache occupancy
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              47564                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          47564                       # number of overall (read+write) accesses
@@ -597,10 +597,10 @@ system.l2c.demand_mshr_misses                  170998                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.120711                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.358261                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                  7910.895776                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                 23478.999694                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.120711                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.358261                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                2411815                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                   9584                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2421399                       # number of overall (read+write) accesses