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authorGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:45 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:45 -0800
commit57e07ac2d2daaa7469241372510395e43ebe14c0 (patch)
treedc338f4fbe8b26f7d7d3532ea0abe324846ca33d /tests/quick/10.linux-boot/ref
parentec20ee2f7cdaff22e63a5ae492f925d0d4839849 (diff)
downloadgem5-57e07ac2d2daaa7469241372510395e43ebe14c0.tar.xz
SE/FS: Make both SE and FS tests available all the time.
--HG-- rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr rename : 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tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simout => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout rename : tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini => 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tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simout => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout rename : tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr => 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tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simout => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout rename : tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/mips/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing/simout => tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/power/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/power/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/power/linux/o3-timing/simout => tests/quick/se/00.hello/ref/power/linux/o3-timing/simout rename : tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/power/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/power/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simout => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout rename : tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/x86/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing/simout => tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt rename : tests/quick/00.hello/test.py => tests/quick/se/00.hello/test.py rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/simout => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simout rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py
Diffstat (limited to 'tests/quick/10.linux-boot/ref')
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini973
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr5
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout13
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt891
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal112
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini864
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr5
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-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt548
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal107
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini967
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr5
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout13
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt1068
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal113
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini861
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr5
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout12
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt646
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal108
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini846
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr18
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout12
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt719
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status1
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminalbin6037 -> 0 bytes
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini719
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr17
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout12
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt441
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status1
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminalbin5878 -> 0 bytes
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini840
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr18
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout12
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt888
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status1
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminalbin6036 -> 0 bytes
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini716
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr17
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout12
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt523
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status1
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminalbin5878 -> 0 bytes
-rw-r--r--tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini1210
-rwxr-xr-xtests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr9
-rwxr-xr-xtests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout13
-rw-r--r--tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt553
-rw-r--r--tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal133
-rw-r--r--tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini1207
-rwxr-xr-xtests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr9
-rwxr-xr-xtests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout13
-rw-r--r--tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt661
-rw-r--r--tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal133
54 files changed, 0 insertions, 17083 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
deleted file mode 100644
index bd95bae49..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ /dev/null
@@ -1,973 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxAlphaSystem
-children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
-boot_cpu_frequency=500
-boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
-init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
-load_addr_mask=1099511627775
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
-physmem=system.physmem
-readfile=tests/halt.sh
-symbolfile=
-system_rev=1024
-system_type=34
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[2]
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=8796093022208:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu0.dtb]
-type=AlphaTLB
-size=64
-
-[system.cpu0.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu0.interrupts]
-type=AlphaInterrupts
-
-[system.cpu0.itb]
-type=AlphaTLB
-size=48
-
-[system.cpu0.tracer]
-type=ExeTracer
-
-[system.cpu1]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
-checker=Null
-clock=500
-cpu_id=1
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu1.tracer
-width=1
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
-
-[system.cpu1.dtb]
-type=AlphaTLB
-size=64
-
-[system.cpu1.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
-
-[system.cpu1.interrupts]
-type=AlphaInterrupts
-
-[system.cpu1.itb]
-type=AlphaTLB
-size=48
-
-[system.cpu1.tracer]
-type=ExeTracer
-
-[system.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.disk0.image
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
-read_only=true
-
-[system.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.disk2.image
-
-[system.disk2.image]
-type=CowDiskImage
-children=child
-child=system.disk2.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk2.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=true
-width=64
-default=system.tsunami.pciconfig.pio
-port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:8589934591
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=true
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[32]
-mem_side=system.membus.port[3]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[4]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[1]
-
-[system.simple_disk]
-type=SimpleDisk
-children=disk
-disk=system.simple_disk.disk
-system=system
-
-[system.simple_disk.disk]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
-read_only=true
-
-[system.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
-
-[system.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
-intrctrl=system.intrctrl
-system=system
-
-[system.tsunami.backdoor]
-type=AlphaBackdoor
-cpu=system.cpu0
-disk=system.simple_disk
-pio_addr=8804682956800
-pio_latency=1000
-platform=system.tsunami
-system=system
-terminal=system.terminal
-pio=system.iobus.port[25]
-
-[system.tsunami.cchip]
-type=TsunamiCChip
-pio_addr=8803072344064
-pio_latency=1000
-platform=system.tsunami
-system=system
-tsunami=system.tsunami
-pio=system.iobus.port[1]
-
-[system.tsunami.ethernet]
-type=NSGigE
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=52
-MinimumGrant=176
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clock=0
-config_latency=20000
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-hardware_address=00:90:00:00:00:01
-intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
-pio=system.iobus.port[29]
-
-[system.tsunami.fake_OROM]
-type=IsaFake
-fake_mem=false
-pio_addr=8796093677568
-pio_latency=1000
-pio_size=393216
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[9]
-
-[system.tsunami.fake_ata0]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848432
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[20]
-
-[system.tsunami.fake_ata1]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848304
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[21]
-
-[system.tsunami.fake_pnp_addr]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848569
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[10]
-
-[system.tsunami.fake_pnp_read0]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848451
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[12]
-
-[system.tsunami.fake_pnp_read1]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848515
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[13]
-
-[system.tsunami.fake_pnp_read2]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848579
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[14]
-
-[system.tsunami.fake_pnp_read3]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848643
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[15]
-
-[system.tsunami.fake_pnp_read4]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848707
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[16]
-
-[system.tsunami.fake_pnp_read5]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848771
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[17]
-
-[system.tsunami.fake_pnp_read6]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848835
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[18]
-
-[system.tsunami.fake_pnp_read7]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848899
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[19]
-
-[system.tsunami.fake_pnp_write]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615850617
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[11]
-
-[system.tsunami.fake_ppc]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848891
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[8]
-
-[system.tsunami.fake_sm_chip]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848816
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[3]
-
-[system.tsunami.fake_uart1]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848696
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[4]
-
-[system.tsunami.fake_uart2]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848936
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[5]
-
-[system.tsunami.fake_uart3]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848680
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[6]
-
-[system.tsunami.fake_uart4]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848944
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[7]
-
-[system.tsunami.fb]
-type=BadDevice
-devicename=FrameBuffer
-pio_addr=8804615848912
-pio_latency=1000
-platform=system.tsunami
-system=system
-pio=system.iobus.port[22]
-
-[system.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=0
-disks=system.disk0 system.disk2
-io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-system=system
-config=system.iobus.port[27]
-dma=system.iobus.port[28]
-pio=system.iobus.port[26]
-
-[system.tsunami.io]
-type=TsunamiIO
-frequency=976562500
-pio_addr=8804615847936
-pio_latency=1000
-platform=system.tsunami
-system=system
-time=Thu Jan 1 00:00:00 2009
-tsunami=system.tsunami
-year_is_bcd=false
-pio=system.iobus.port[23]
-
-[system.tsunami.pchip]
-type=TsunamiPChip
-pio_addr=8802535473152
-pio_latency=1000
-platform=system.tsunami
-system=system
-tsunami=system.tsunami
-pio=system.iobus.port[2]
-
-[system.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-pio_latency=1
-platform=system.tsunami
-size=16777216
-system=system
-pio=system.iobus.default
-
-[system.tsunami.uart]
-type=Uart8250
-pio_addr=8804615848952
-pio_latency=1000
-platform=system.tsunami
-system=system
-terminal=system.terminal
-pio=system.iobus.port[24]
-
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
deleted file mode 100755
index 0bcb6e870..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
+++ /dev/null
@@ -1,5 +0,0 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
deleted file mode 100755
index dbef4ddb7..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ /dev/null
@@ -1,13 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:22:39
-gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
-Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-info: kernel located at: /dist/m5/system/binaries/vmlinux
-info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 97861500
-Exiting @ tick 1870335522500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
deleted file mode 100644
index c3dae4684..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ /dev/null
@@ -1,891 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 1.870336 # Number of seconds simulated
-sim_ticks 1870335522500 # Number of ticks simulated
-final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3272042 # Simulator instruction rate (inst/s)
-host_tick_rate 96902915749 # Simulator tick rate (ticks/s)
-host_mem_usage 296264 # Number of bytes of host memory used
-host_seconds 19.30 # Real time elapsed on the host
-sim_insts 63154034 # Number of instructions simulated
-system.physmem.bytes_read 72297472 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 995008 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10452352 # Number of bytes written to this memory
-system.physmem.num_reads 1129648 # Number of read requests responded to by this memory
-system.physmem.num_writes 163318 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 38654814 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 531994 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 5588490 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 44243304 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 1051788 # number of replacements
-system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use
-system.l2c.total_refs 2341203 # Total number of references to valid blocks.
-system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks.
-system.l2c.avg_refs 2.151871 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 10019.673951 # Average occupied blocks per context
-system.l2c.occ_blocks::1 266.115685 # Average occupied blocks per context
-system.l2c.occ_blocks::2 23831.931773 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.152888 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.004061 # Average percentage of cache occupancy
-system.l2c.occ_percent::2 0.363646 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1620505 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 137130 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1757635 # number of ReadReq hits
-system.l2c.Writeback_hits::0 811846 # number of Writeback hits
-system.l2c.Writeback_hits::total 811846 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 134 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1 39 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 173 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0 15 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1 9 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 24 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0 164417 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1 14126 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 178543 # number of ReadExReq hits
-system.l2c.demand_hits::0 1784922 # number of demand (read+write) hits
-system.l2c.demand_hits::1 151256 # number of demand (read+write) hits
-system.l2c.demand_hits::2 0 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1936178 # number of demand (read+write) hits
-system.l2c.overall_hits::0 1784922 # number of overall hits
-system.l2c.overall_hits::1 151256 # number of overall hits
-system.l2c.overall_hits::2 0 # number of overall hits
-system.l2c.overall_hits::total 1936178 # number of overall hits
-system.l2c.ReadReq_misses::0 956917 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 4511 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 961428 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 2441 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 567 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3008 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0 65 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1 101 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0 117481 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1 9826 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 127307 # number of ReadExReq misses
-system.l2c.demand_misses::0 1074398 # number of demand (read+write) misses
-system.l2c.demand_misses::1 14337 # number of demand (read+write) misses
-system.l2c.demand_misses::2 0 # number of demand (read+write) misses
-system.l2c.demand_misses::total 1088735 # number of demand (read+write) misses
-system.l2c.overall_misses::0 1074398 # number of overall misses
-system.l2c.overall_misses::1 14337 # number of overall misses
-system.l2c.overall_misses::2 0 # number of overall misses
-system.l2c.overall_misses::total 1088735 # number of overall misses
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 2577422 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 141641 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2719063 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 811846 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 811846 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 2575 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 606 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0 80 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1 110 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 190 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 281898 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1 23952 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 305850 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 2859320 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 165593 # number of demand (read+write) accesses
-system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3024913 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 2859320 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 165593 # number of overall (read+write) accesses
-system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3024913 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.371269 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.031848 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.947961 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 0.935644 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0 0.812500 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1 0.918182 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.416750 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 0.410237 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.375753 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.086580 # miss rate for demand accesses
-system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
-system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.375753 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.086580 # miss rate for overall accesses
-system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
-system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 no_value # average overall miss latency
-system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::2 no_value # average overall miss latency
-system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 121798 # number of writebacks
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 no_value # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 no_value # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 41695 # number of replacements
-system.iocache.tagsinuse 0.435437 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1 0.435437 # Average occupied blocks per context
-system.iocache.occ_percent::1 0.027215 # Average percentage of cache occupancy
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.ReadReq_misses::1 175 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
-system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 41727 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 41727 # number of overall misses
-system.iocache.overall_misses::total 41727 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.ReadReq_accesses::1 175 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 41520 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
-system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs 395 # Number of DMA write transactions.
-system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.dtb.fetch_hits 0 # ITB hits
-system.cpu0.dtb.fetch_misses 0 # ITB misses
-system.cpu0.dtb.fetch_acv 0 # ITB acv
-system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 9154530 # DTB read hits
-system.cpu0.dtb.read_misses 7079 # DTB read misses
-system.cpu0.dtb.read_acv 152 # DTB read access violations
-system.cpu0.dtb.read_accesses 508987 # DTB read accesses
-system.cpu0.dtb.write_hits 5936899 # DTB write hits
-system.cpu0.dtb.write_misses 726 # DTB write misses
-system.cpu0.dtb.write_acv 99 # DTB write access violations
-system.cpu0.dtb.write_accesses 189050 # DTB write accesses
-system.cpu0.dtb.data_hits 15091429 # DTB hits
-system.cpu0.dtb.data_misses 7805 # DTB misses
-system.cpu0.dtb.data_acv 251 # DTB access violations
-system.cpu0.dtb.data_accesses 698037 # DTB accesses
-system.cpu0.itb.fetch_hits 3855556 # ITB hits
-system.cpu0.itb.fetch_misses 3485 # ITB misses
-system.cpu0.itb.fetch_acv 127 # ITB acv
-system.cpu0.itb.fetch_accesses 3859041 # ITB accesses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.read_acv 0 # DTB read access violations
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.write_acv 0 # DTB write access violations
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.data_hits 0 # DTB hits
-system.cpu0.itb.data_misses 0 # DTB misses
-system.cpu0.itb.data_acv 0 # DTB access violations
-system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.num_insts 57222076 # Number of instructions executed
-system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses
-system.cpu0.num_func_calls 1399585 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 53249924 # number of integer instructions
-system.cpu0.num_fp_insts 299810 # number of float instructions
-system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written
-system.cpu0.num_mem_refs 15135515 # number of memory refs
-system.cpu0.num_load_insts 9184477 # Number of load instructions
-system.cpu0.num_store_insts 5951038 # Number of store instructions
-system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles
-system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed
-system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed
-system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed
-system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed
-system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed
-system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed
-system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed
-system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed
-system.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed
-system.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed
-system.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed
-system.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed
-system.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed
-system.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed
-system.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed
-system.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed
-system.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed
-system.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed
-system.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed
-system.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed
-system.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed
-system.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed
-system.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed
-system.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed
-system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed
-system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 226 # number of syscalls executed
-system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed
-system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed
-system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed
-system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed
-system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 183291 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches
-system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1157
-system.cpu0.kern.mode_good::user 1158
-system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3763 # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 884404 # number of replacements
-system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use
-system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 511.244754 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.998525 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::0 56345132 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits
-system.cpu0.icache.demand_hits::0 56345132 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::0 56345132 # number of overall hits
-system.cpu0.icache.overall_hits::1 0 # number of overall hits
-system.cpu0.icache.overall_hits::total 56345132 # number of overall hits
-system.cpu0.icache.ReadReq_misses::0 885000 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses
-system.cpu0.icache.demand_misses::0 885000 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::0 885000 # number of overall misses
-system.cpu0.icache.overall_misses::1 0 # number of overall misses
-system.cpu0.icache.overall_misses::total 885000 # number of overall misses
-system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::0 57230132 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::0 57230132 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::0 57230132 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::0 0.015464 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::0 0.015464 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::0 0.015464 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks 95 # number of writebacks
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 1978962 # number of replacements
-system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0 504.827058 # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0 0.985990 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::0 7298106 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7298106 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::0 5462265 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 5462265 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::0 172138 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::0 186635 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 186635 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::0 12760371 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 12760371 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::0 12760371 # number of overall hits
-system.cpu0.dcache.overall_hits::1 0 # number of overall hits
-system.cpu0.dcache.overall_hits::total 12760371 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::0 1683563 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::0 285996 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 285996 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::0 16159 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 16159 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::0 703 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 703 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::0 1969559 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1969559 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::0 1969559 # number of overall misses
-system.cpu0.dcache.overall_misses::1 0 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1969559 # number of overall misses
-system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::0 8981669 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::0 5748261 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::0 188297 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::0 187338 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::0 14729930 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::0 14729930 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::0 0.187444 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::0 0.049753 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.085817 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003753 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::0 0.133711 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0 0.133711 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks 771740 # number of writebacks
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dtb.fetch_hits 0 # ITB hits
-system.cpu1.dtb.fetch_misses 0 # ITB misses
-system.cpu1.dtb.fetch_acv 0 # ITB acv
-system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1163439 # DTB read hits
-system.cpu1.dtb.read_misses 3277 # DTB read misses
-system.cpu1.dtb.read_acv 58 # DTB read access violations
-system.cpu1.dtb.read_accesses 220342 # DTB read accesses
-system.cpu1.dtb.write_hits 751446 # DTB write hits
-system.cpu1.dtb.write_misses 415 # DTB write misses
-system.cpu1.dtb.write_acv 58 # DTB write access violations
-system.cpu1.dtb.write_accesses 103280 # DTB write accesses
-system.cpu1.dtb.data_hits 1914885 # DTB hits
-system.cpu1.dtb.data_misses 3692 # DTB misses
-system.cpu1.dtb.data_acv 116 # DTB access violations
-system.cpu1.dtb.data_accesses 323622 # DTB accesses
-system.cpu1.itb.fetch_hits 1468399 # ITB hits
-system.cpu1.itb.fetch_misses 1539 # ITB misses
-system.cpu1.itb.fetch_acv 57 # ITB acv
-system.cpu1.itb.fetch_accesses 1469938 # ITB accesses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.read_acv 0 # DTB read access violations
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.write_acv 0 # DTB write access violations
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.data_hits 0 # DTB hits
-system.cpu1.itb.data_misses 0 # DTB misses
-system.cpu1.itb.data_acv 0 # DTB access violations
-system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.num_insts 5931958 # Number of instructions executed
-system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses
-system.cpu1.num_func_calls 182742 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 5550578 # number of integer instructions
-system.cpu1.num_fp_insts 28590 # number of float instructions
-system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written
-system.cpu1.num_mem_refs 1926244 # number of memory refs
-system.cpu1.num_load_insts 1170888 # Number of load instructions
-system.cpu1.num_store_insts 755356 # Number of store instructions
-system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles
-system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed
-system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed
-system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed
-system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed
-system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed
-system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed
-system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed
-system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed
-system.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed
-system.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed
-system.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed
-system.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed
-system.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed
-system.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed
-system.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed
-system.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed
-system.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 100 # number of syscalls executed
-system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed
-system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed
-system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed
-system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed
-system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed
-system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 32131 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 580 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 612
-system.cpu1.kern.mode_good::user 580
-system.cpu1.kern.mode_good::idle 32
-system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 1.608089 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 471 # number of times the context was actually changed
-system.cpu1.icache.replacements 103091 # number of replacements
-system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use
-system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0 427.126317 # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0 0.834231 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0 5832136 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits
-system.cpu1.icache.demand_hits::0 5832136 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::0 5832136 # number of overall hits
-system.cpu1.icache.overall_hits::1 0 # number of overall hits
-system.cpu1.icache.overall_hits::total 5832136 # number of overall hits
-system.cpu1.icache.ReadReq_misses::0 103630 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses
-system.cpu1.icache.demand_misses::0 103630 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0 103630 # number of overall misses
-system.cpu1.icache.overall_misses::1 0 # number of overall misses
-system.cpu1.icache.overall_misses::total 103630 # number of overall misses
-system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0 5935766 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::0 5935766 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::0 5935766 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0 0.017459 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0 0.017459 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::0 0.017459 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks 15 # number of writebacks
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 62338 # number of replacements
-system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0 391.951263 # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0 0.765530 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0 1109315 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0 707444 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 707444 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::0 15613 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 15613 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0 1816759 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 1816759 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0 1816759 # number of overall hits
-system.cpu1.dcache.overall_hits::1 0 # number of overall hits
-system.cpu1.dcache.overall_hits::total 1816759 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0 41650 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0 25861 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 25861 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0 1289 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0 732 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 732 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0 67511 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 67511 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0 67511 # number of overall misses
-system.cpu1.dcache.overall_misses::1 0 # number of overall misses
-system.cpu1.dcache.overall_misses::total 67511 # number of overall misses
-system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0 1150965 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::0 733305 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0 16345 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0 1884270 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0 1884270 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0 0.036187 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0 0.035266 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.078511 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044784 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0 0.035829 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0 0.035829 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 39996 # number of writebacks
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
deleted file mode 100644
index 6129834bd..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
+++ /dev/null
@@ -1,112 +0,0 @@
-M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
- Got Configuration 623
- memsize 8000000 pages 4000
- First free page after ROM 0xFFFFFC0000018000
- HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
- kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
- CPU Clock at 2000 MHz IntrClockFrequency=1024
- Booting with 2 processor(s)
- KSP: 0x20043FE8 PTBR 0x20
- KSP: 0x20043FE8 PTBR 0x20
- Console Callback at 0x0, fixup at 0x0, crb offset: 0x790
- Memory cluster 0 [0 - 392]
- Memory cluster 1 [392 - 15992]
- Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
- ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
- Bootstraping CPU 1 with sp=0xFFFFFC0000076000
- unix_boot_mem ends at FFFFFC0000078000
- k_argc = 0
- jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
- CallbackFixup 0 18000, t7=FFFFFC000070C000
- Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
- Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
- Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
- Major Options: SMP LEGACY_START VERBOSE_MCHECK
- Command line: root=/dev/hda1 console=ttyS0
- memcluster 0, usage 1, start 0, end 392
- memcluster 1, usage 0, start 392, end 16384
- freeing pages 1069:16384
- reserving pages 1069:1070
- SMP: 2 CPUs probed -- cpu_present_mask = 3
- Built 1 zonelists
- Kernel command line: root=/dev/hda1 console=ttyS0
- PID hash table entries: 1024 (order: 10, 32768 bytes)
- Using epoch = 1900
- Console: colour dummy device 80x25
- Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
- Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
- Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
- Mount-cache hash table entries: 512
- SMP starting up secondaries.
- Slave CPU 1 console command START
-SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
- Brought up 2 CPUs
- SMP: Total of 2 processors activated (8000.15 BogoMIPS).
- NET: Registered protocol family 16
- EISA bus registered
- pci: enabling save/restore of SRM state
- SCSI subsystem initialized
- srm_env: version 0.0.5 loaded successfully
- Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
- Initializing Cryptographic API
- rtc: Standard PC (1900) epoch (1900) detected
- Real Time Clock Driver v1.12
- Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
- ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
- io scheduler noop registered
- io scheduler anticipatory registered
- io scheduler deadline registered
- io scheduler cfq registered
- loop: loaded (max 8 devices)
- nbd: registered device at major 43
- ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
- PCI: Setting latency timer of device 0000:00:01.0 to 64
- eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
- eth0: enabling optical transceiver
- eth0: using 64 bit addressing.
- eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
- tun: Universal TUN/TAP device driver, 1.6
- tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
- Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
- ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
- PIIX4: IDE controller at PCI slot 0000:00:00.0
- PIIX4: chipset revision 0
- PIIX4: 100% native mode on irq 31
- PCI: Setting latency timer of device 0000:00:00.0 to 64
- ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
- ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
- hda: M5 IDE Disk, ATA DISK drive
- hdb: M5 IDE Disk, ATA DISK drive
- ide0 at 0x8410-0x8417,0x8422 on irq 31
- hda: max request size: 128KiB
- hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
- hda: cache flushes not supported
- hda: hda1
- hdb: max request size: 128KiB
- hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
- hdb: cache flushes not supported
- hdb: unknown partition table
- mice: PS/2 mouse device common for all mice
- NET: Registered protocol family 2
- IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
- TCP established hash table entries: 16384 (order: 5, 262144 bytes)
- TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
- TCP: Hash tables configured (established 16384 bind 16384)
- TCP reno registered
- ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
- ip_tables: (C) 2000-2002 Netfilter core team
- arp_tables: (C) 2002 David S. Miller
- TCP bic registered
- Initializing IPsec netlink socket
- NET: Registered protocol family 1
- NET: Registered protocol family 17
- NET: Registered protocol family 15
- Bridge firewalling registered
- 802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
- All bugs added by David S. Miller <davem@redhat.com>
- VFS: Mounted root (ext2 filesystem) readonly.
- Freeing unused kernel memory: 224k freed
- init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
-mounting filesystems...
-EXT2-fs warning: checktime reached, running e2fsck is recommended
- loading script...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
deleted file mode 100644
index b72ae72cb..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ /dev/null
@@ -1,864 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
-boot_cpu_frequency=500
-boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
-init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
-load_addr_mask=1099511627775
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
-physmem=system.physmem
-readfile=tests/halt.sh
-symbolfile=
-system_rev=1024
-system_type=34
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[2]
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=8796093022208:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu.dtb]
-type=AlphaTLB
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-
-[system.cpu.itb]
-type=AlphaTLB
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.disk0.image
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
-read_only=true
-
-[system.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.disk2.image
-
-[system.disk2.image]
-type=CowDiskImage
-children=child
-child=system.disk2.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk2.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=true
-width=64
-default=system.tsunami.pciconfig.pio
-port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:8589934591
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=true
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[32]
-mem_side=system.membus.port[3]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[4]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[1]
-
-[system.simple_disk]
-type=SimpleDisk
-children=disk
-disk=system.simple_disk.disk
-system=system
-
-[system.simple_disk.disk]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
-read_only=true
-
-[system.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
-intrctrl=system.intrctrl
-system=system
-
-[system.tsunami.backdoor]
-type=AlphaBackdoor
-cpu=system.cpu
-disk=system.simple_disk
-pio_addr=8804682956800
-pio_latency=1000
-platform=system.tsunami
-system=system
-terminal=system.terminal
-pio=system.iobus.port[25]
-
-[system.tsunami.cchip]
-type=TsunamiCChip
-pio_addr=8803072344064
-pio_latency=1000
-platform=system.tsunami
-system=system
-tsunami=system.tsunami
-pio=system.iobus.port[1]
-
-[system.tsunami.ethernet]
-type=NSGigE
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=52
-MinimumGrant=176
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clock=0
-config_latency=20000
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-hardware_address=00:90:00:00:00:01
-intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
-pio=system.iobus.port[29]
-
-[system.tsunami.fake_OROM]
-type=IsaFake
-fake_mem=false
-pio_addr=8796093677568
-pio_latency=1000
-pio_size=393216
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[9]
-
-[system.tsunami.fake_ata0]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848432
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[20]
-
-[system.tsunami.fake_ata1]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848304
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[21]
-
-[system.tsunami.fake_pnp_addr]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848569
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[10]
-
-[system.tsunami.fake_pnp_read0]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848451
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[12]
-
-[system.tsunami.fake_pnp_read1]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848515
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[13]
-
-[system.tsunami.fake_pnp_read2]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848579
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[14]
-
-[system.tsunami.fake_pnp_read3]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848643
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[15]
-
-[system.tsunami.fake_pnp_read4]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848707
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[16]
-
-[system.tsunami.fake_pnp_read5]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848771
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[17]
-
-[system.tsunami.fake_pnp_read6]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848835
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[18]
-
-[system.tsunami.fake_pnp_read7]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848899
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[19]
-
-[system.tsunami.fake_pnp_write]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615850617
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[11]
-
-[system.tsunami.fake_ppc]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848891
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[8]
-
-[system.tsunami.fake_sm_chip]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848816
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[3]
-
-[system.tsunami.fake_uart1]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848696
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[4]
-
-[system.tsunami.fake_uart2]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848936
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[5]
-
-[system.tsunami.fake_uart3]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848680
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[6]
-
-[system.tsunami.fake_uart4]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848944
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[7]
-
-[system.tsunami.fb]
-type=BadDevice
-devicename=FrameBuffer
-pio_addr=8804615848912
-pio_latency=1000
-platform=system.tsunami
-system=system
-pio=system.iobus.port[22]
-
-[system.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=0
-disks=system.disk0 system.disk2
-io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-system=system
-config=system.iobus.port[27]
-dma=system.iobus.port[28]
-pio=system.iobus.port[26]
-
-[system.tsunami.io]
-type=TsunamiIO
-frequency=976562500
-pio_addr=8804615847936
-pio_latency=1000
-platform=system.tsunami
-system=system
-time=Thu Jan 1 00:00:00 2009
-tsunami=system.tsunami
-year_is_bcd=false
-pio=system.iobus.port[23]
-
-[system.tsunami.pchip]
-type=TsunamiPChip
-pio_addr=8802535473152
-pio_latency=1000
-platform=system.tsunami
-system=system
-tsunami=system.tsunami
-pio=system.iobus.port[2]
-
-[system.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-pio_latency=1
-platform=system.tsunami
-size=16777216
-system=system
-pio=system.iobus.default
-
-[system.tsunami.uart]
-type=Uart8250
-pio_addr=8804615848952
-pio_latency=1000
-platform=system.tsunami
-system=system
-terminal=system.terminal
-pio=system.iobus.port[24]
-
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
deleted file mode 100755
index 0bcb6e870..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
+++ /dev/null
@@ -1,5 +0,0 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
deleted file mode 100755
index 9b658d14c..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ /dev/null
@@ -1,12 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:22:39
-gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
-Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-info: kernel located at: /dist/m5/system/binaries/vmlinux
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1829332258000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
deleted file mode 100644
index 7f4c99b34..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ /dev/null
@@ -1,548 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 1.829332 # Number of seconds simulated
-sim_ticks 1829332258000 # Number of ticks simulated
-final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3300922 # Simulator instruction rate (inst/s)
-host_tick_rate 100577077281 # Simulator tick rate (ticks/s)
-host_mem_usage 294216 # Number of bytes of host memory used
-host_seconds 18.19 # Real time elapsed on the host
-sim_insts 60038305 # Number of instructions simulated
-system.physmem.bytes_read 71650816 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 955904 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10156864 # Number of bytes written to this memory
-system.physmem.num_reads 1119544 # Number of read requests responded to by this memory
-system.physmem.num_writes 158701 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 39167743 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 522543 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 5552225 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 44719968 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 1045877 # number of replacements
-system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use
-system.l2c.total_refs 2291835 # Total number of references to valid blocks.
-system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks.
-system.l2c.avg_refs 2.126306 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 10193.605493 # Average occupied blocks per context
-system.l2c.occ_blocks::1 23613.410409 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.155542 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.360312 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1699395 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits
-system.l2c.Writeback_hits::0 825291 # number of Writeback hits
-system.l2c.Writeback_hits::total 825291 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 1 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 185383 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits
-system.l2c.demand_hits::0 1884778 # number of demand (read+write) hits
-system.l2c.demand_hits::1 0 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits
-system.l2c.overall_hits::0 1884778 # number of overall hits
-system.l2c.overall_hits::1 0 # number of overall hits
-system.l2c.overall_hits::total 1884778 # number of overall hits
-system.l2c.ReadReq_misses::0 959629 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 12 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0 118859 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses
-system.l2c.demand_misses::0 1078488 # number of demand (read+write) misses
-system.l2c.demand_misses::1 0 # number of demand (read+write) misses
-system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses
-system.l2c.overall_misses::0 1078488 # number of overall misses
-system.l2c.overall_misses::1 0 # number of overall misses
-system.l2c.overall_misses::total 1078488 # number of overall misses
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 2659024 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 825291 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 13 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 304242 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 2963266 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 2963266 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.360895 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.923077 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.390673 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.363952 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.363952 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 117189 # number of writebacks
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 41686 # number of replacements
-system.iocache.tagsinuse 1.225570 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1 1.225570 # Average occupied blocks per context
-system.iocache.occ_percent::1 0.076598 # Average percentage of cache occupancy
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.ReadReq_misses::1 174 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
-system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 41726 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 41726 # number of overall misses
-system.iocache.overall_misses::total 41726 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 41512 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
-system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs 395 # Number of DMA write transactions.
-system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9710427 # DTB read hits
-system.cpu.dtb.read_misses 10329 # DTB read misses
-system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_accesses 728856 # DTB read accesses
-system.cpu.dtb.write_hits 6352498 # DTB write hits
-system.cpu.dtb.write_misses 1142 # DTB write misses
-system.cpu.dtb.write_acv 157 # DTB write access violations
-system.cpu.dtb.write_accesses 291931 # DTB write accesses
-system.cpu.dtb.data_hits 16062925 # DTB hits
-system.cpu.dtb.data_misses 11471 # DTB misses
-system.cpu.dtb.data_acv 367 # DTB access violations
-system.cpu.dtb.data_accesses 1020787 # DTB accesses
-system.cpu.itb.fetch_hits 4974648 # ITB hits
-system.cpu.itb.fetch_misses 5006 # ITB misses
-system.cpu.itb.fetch_acv 184 # ITB acv
-system.cpu.itb.fetch_accesses 4979654 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 3658664408 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 60038305 # Number of instructions executed
-system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
-system.cpu.num_func_calls 1484182 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls
-system.cpu.num_int_insts 55913521 # number of integer instructions
-system.cpu.num_fp_insts 324460 # number of float instructions
-system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read
-system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
-system.cpu.num_mem_refs 16115709 # number of memory refs
-system.cpu.num_load_insts 9747513 # Number of load instructions
-system.cpu.num_store_insts 6368196 # Number of store instructions
-system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles
-system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles
-system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
-system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
-system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
-system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
-system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
-system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
-system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
-system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
-system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
-system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
-system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
-system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
-system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
-system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
-system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
-system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
-system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
-system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
-system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
-system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
-system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
-system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
-system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
-system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
-system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
-system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
-system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
-system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
-system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
-system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
-system.cpu.kern.syscall::total 326 # number of syscalls executed
-system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
-system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
-system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed
-system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
-system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
-system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
-system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
-system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
-system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
-system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
-system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192180 # number of callpals executed
-system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
-system.cpu.kern.mode_good::kernel 1909
-system.cpu.kern.mode_good::user 1738
-system.cpu.kern.mode_good::idle 171
-system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4178 # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 919594 # number of replacements
-system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use
-system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 511.215243 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.998467 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0 59129922 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits
-system.cpu.icache.demand_hits::0 59129922 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0 59129922 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 59129922 # number of overall hits
-system.cpu.icache.ReadReq_misses::0 920221 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses
-system.cpu.icache.demand_misses::0 920221 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0 920221 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 920221 # number of overall misses
-system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0 60050143 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0 60050143 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0 60050143 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0 0.015324 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0 0.015324 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0 0.015324 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 108 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2042700 # number of replacements
-system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 511.997802 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0 7807782 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0 5848212 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::0 183141 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0 199282 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0 13655994 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0 13655994 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 13655994 # number of overall hits
-system.cpu.dcache.ReadReq_misses::0 1721705 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0 304362 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0 17162 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::0 2026067 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0 2026067 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 2026067 # number of overall misses
-system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0 9529487 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0 200303 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0 15682061 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0 15682061 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.180671 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.049469 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085680 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.129196 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.129196 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 825183 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
deleted file mode 100644
index f17158b67..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
+++ /dev/null
@@ -1,107 +0,0 @@
-M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
- Got Configuration 623
- memsize 8000000 pages 4000
- First free page after ROM 0xFFFFFC0000018000
- HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
- kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
- CPU Clock at 2000 MHz IntrClockFrequency=1024
- Booting with 1 processor(s)
- KSP: 0x20043FE8 PTBR 0x20
- Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
- Memory cluster 0 [0 - 392]
- Memory cluster 1 [392 - 15992]
- Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
- ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
- unix_boot_mem ends at FFFFFC0000076000
- k_argc = 0
- jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
- CallbackFixup 0 18000, t7=FFFFFC000070C000
- Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
- Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
- Major Options: SMP LEGACY_START VERBOSE_MCHECK
- Command line: root=/dev/hda1 console=ttyS0
- memcluster 0, usage 1, start 0, end 392
- memcluster 1, usage 0, start 392, end 16384
- freeing pages 1069:16384
- reserving pages 1069:1070
- SMP: 1 CPUs probed -- cpu_present_mask = 1
- Built 1 zonelists
- Kernel command line: root=/dev/hda1 console=ttyS0
- PID hash table entries: 1024 (order: 10, 32768 bytes)
- Using epoch = 1900
- Console: colour dummy device 80x25
- Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
- Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
- Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
- Mount-cache hash table entries: 512
- SMP mode deactivated.
- Brought up 1 CPUs
- SMP: Total of 1 processors activated (4002.20 BogoMIPS).
- NET: Registered protocol family 16
- EISA bus registered
- pci: enabling save/restore of SRM state
- SCSI subsystem initialized
- srm_env: version 0.0.5 loaded successfully
- Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
- Initializing Cryptographic API
- rtc: Standard PC (1900) epoch (1900) detected
- Real Time Clock Driver v1.12
- Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
- ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
- io scheduler noop registered
- io scheduler anticipatory registered
- io scheduler deadline registered
- io scheduler cfq registered
- loop: loaded (max 8 devices)
- nbd: registered device at major 43
- ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
- PCI: Setting latency timer of device 0000:00:01.0 to 64
- eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
- eth0: enabling optical transceiver
- eth0: using 64 bit addressing.
- eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
- tun: Universal TUN/TAP device driver, 1.6
- tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
- Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
- ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
- PIIX4: IDE controller at PCI slot 0000:00:00.0
- PIIX4: chipset revision 0
- PIIX4: 100% native mode on irq 31
- PCI: Setting latency timer of device 0000:00:00.0 to 64
- ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
- ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
- hda: M5 IDE Disk, ATA DISK drive
- hdb: M5 IDE Disk, ATA DISK drive
- ide0 at 0x8410-0x8417,0x8422 on irq 31
- hda: max request size: 128KiB
- hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
- hda: cache flushes not supported
- hda: hda1
- hdb: max request size: 128KiB
- hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
- hdb: cache flushes not supported
- hdb: unknown partition table
- mice: PS/2 mouse device common for all mice
- NET: Registered protocol family 2
- IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
- TCP established hash table entries: 16384 (order: 5, 262144 bytes)
- TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
- TCP: Hash tables configured (established 16384 bind 16384)
- TCP reno registered
- ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
- ip_tables: (C) 2000-2002 Netfilter core team
- arp_tables: (C) 2002 David S. Miller
- TCP bic registered
- Initializing IPsec netlink socket
- NET: Registered protocol family 1
- NET: Registered protocol family 17
- NET: Registered protocol family 15
- Bridge firewalling registered
- 802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
- All bugs added by David S. Miller <davem@redhat.com>
- VFS: Mounted root (ext2 filesystem) readonly.
- Freeing unused kernel memory: 224k freed
- init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
-mounting filesystems...
-EXT2-fs warning: checktime reached, running e2fsck is recommended
- loading script...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
deleted file mode 100644
index 1a4bf8750..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ /dev/null
@@ -1,967 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxAlphaSystem
-children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
-boot_cpu_frequency=500
-boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
-init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
-load_addr_mask=1099511627775
-mem_mode=timing
-memories=system.physmem
-num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
-physmem=system.physmem
-readfile=tests/halt.sh
-symbolfile=
-system_rev=1024
-system_type=34
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[2]
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=8796093022208:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-system=system
-tracer=system.cpu0.tracer
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu0.dtb]
-type=AlphaTLB
-size=64
-
-[system.cpu0.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu0.interrupts]
-type=AlphaInterrupts
-
-[system.cpu0.itb]
-type=AlphaTLB
-size=48
-
-[system.cpu0.tracer]
-type=ExeTracer
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
-checker=Null
-clock=500
-cpu_id=1
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-system=system
-tracer=system.cpu1.tracer
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
-
-[system.cpu1.dtb]
-type=AlphaTLB
-size=64
-
-[system.cpu1.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
-
-[system.cpu1.interrupts]
-type=AlphaInterrupts
-
-[system.cpu1.itb]
-type=AlphaTLB
-size=48
-
-[system.cpu1.tracer]
-type=ExeTracer
-
-[system.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.disk0.image
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
-read_only=true
-
-[system.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.disk2.image
-
-[system.disk2.image]
-type=CowDiskImage
-children=child
-child=system.disk2.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk2.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=true
-width=64
-default=system.tsunami.pciconfig.pio
-port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:8589934591
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=true
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[32]
-mem_side=system.membus.port[3]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[4]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[1]
-
-[system.simple_disk]
-type=SimpleDisk
-children=disk
-disk=system.simple_disk.disk
-system=system
-
-[system.simple_disk.disk]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
-read_only=true
-
-[system.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
-
-[system.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
-intrctrl=system.intrctrl
-system=system
-
-[system.tsunami.backdoor]
-type=AlphaBackdoor
-cpu=system.cpu0
-disk=system.simple_disk
-pio_addr=8804682956800
-pio_latency=1000
-platform=system.tsunami
-system=system
-terminal=system.terminal
-pio=system.iobus.port[25]
-
-[system.tsunami.cchip]
-type=TsunamiCChip
-pio_addr=8803072344064
-pio_latency=1000
-platform=system.tsunami
-system=system
-tsunami=system.tsunami
-pio=system.iobus.port[1]
-
-[system.tsunami.ethernet]
-type=NSGigE
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=52
-MinimumGrant=176
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clock=0
-config_latency=20000
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-hardware_address=00:90:00:00:00:01
-intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
-pio=system.iobus.port[29]
-
-[system.tsunami.fake_OROM]
-type=IsaFake
-fake_mem=false
-pio_addr=8796093677568
-pio_latency=1000
-pio_size=393216
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[9]
-
-[system.tsunami.fake_ata0]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848432
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[20]
-
-[system.tsunami.fake_ata1]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848304
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[21]
-
-[system.tsunami.fake_pnp_addr]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848569
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[10]
-
-[system.tsunami.fake_pnp_read0]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848451
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[12]
-
-[system.tsunami.fake_pnp_read1]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848515
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[13]
-
-[system.tsunami.fake_pnp_read2]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848579
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[14]
-
-[system.tsunami.fake_pnp_read3]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848643
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[15]
-
-[system.tsunami.fake_pnp_read4]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848707
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[16]
-
-[system.tsunami.fake_pnp_read5]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848771
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[17]
-
-[system.tsunami.fake_pnp_read6]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848835
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[18]
-
-[system.tsunami.fake_pnp_read7]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848899
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[19]
-
-[system.tsunami.fake_pnp_write]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615850617
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[11]
-
-[system.tsunami.fake_ppc]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848891
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[8]
-
-[system.tsunami.fake_sm_chip]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848816
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[3]
-
-[system.tsunami.fake_uart1]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848696
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[4]
-
-[system.tsunami.fake_uart2]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848936
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[5]
-
-[system.tsunami.fake_uart3]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848680
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[6]
-
-[system.tsunami.fake_uart4]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848944
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[7]
-
-[system.tsunami.fb]
-type=BadDevice
-devicename=FrameBuffer
-pio_addr=8804615848912
-pio_latency=1000
-platform=system.tsunami
-system=system
-pio=system.iobus.port[22]
-
-[system.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=0
-disks=system.disk0 system.disk2
-io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-system=system
-config=system.iobus.port[27]
-dma=system.iobus.port[28]
-pio=system.iobus.port[26]
-
-[system.tsunami.io]
-type=TsunamiIO
-frequency=976562500
-pio_addr=8804615847936
-pio_latency=1000
-platform=system.tsunami
-system=system
-time=Thu Jan 1 00:00:00 2009
-tsunami=system.tsunami
-year_is_bcd=false
-pio=system.iobus.port[23]
-
-[system.tsunami.pchip]
-type=TsunamiPChip
-pio_addr=8802535473152
-pio_latency=1000
-platform=system.tsunami
-system=system
-tsunami=system.tsunami
-pio=system.iobus.port[2]
-
-[system.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-pio_latency=1
-platform=system.tsunami
-size=16777216
-system=system
-pio=system.iobus.default
-
-[system.tsunami.uart]
-type=Uart8250
-pio_addr=8804615848952
-pio_latency=1000
-platform=system.tsunami
-system=system
-terminal=system.terminal
-pio=system.iobus.port[24]
-
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
deleted file mode 100755
index 0bcb6e870..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
+++ /dev/null
@@ -1,5 +0,0 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
deleted file mode 100755
index 3af3fc1dd..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ /dev/null
@@ -1,13 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:23:09
-gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
-Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-info: kernel located at: /dist/m5/system/binaries/vmlinux
-info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 562628000
-Exiting @ tick 1958647095000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
deleted file mode 100644
index 628ea2e3e..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ /dev/null
@@ -1,1068 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 1.958647 # Number of seconds simulated
-sim_ticks 1958647095000 # Number of ticks simulated
-final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1643366 # Simulator instruction rate (inst/s)
-host_tick_rate 54228566310 # Simulator tick rate (ticks/s)
-host_mem_usage 293036 # Number of bytes of host memory used
-host_seconds 36.12 # Real time elapsed on the host
-sim_insts 59355643 # Number of instructions simulated
-system.physmem.bytes_read 30050624 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 971200 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10333120 # Number of bytes written to this memory
-system.physmem.num_reads 469541 # Number of read requests responded to by this memory
-system.physmem.num_writes 161455 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 15342541 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 495852 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 5275642 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 20618183 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 393576 # number of replacements
-system.l2c.tagsinuse 34487.800710 # Cycle average of tags in use
-system.l2c.total_refs 2371449 # Total number of references to valid blocks.
-system.l2c.sampled_refs 427769 # Sample count of references to valid blocks.
-system.l2c.avg_refs 5.543761 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 10882116000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 10867.929163 # Average occupied blocks per context
-system.l2c.occ_blocks::1 199.983935 # Average occupied blocks per context
-system.l2c.occ_blocks::2 23419.887612 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.165831 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.003052 # Average percentage of cache occupancy
-system.l2c.occ_percent::2 0.357359 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1659395 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 119191 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1778586 # number of ReadReq hits
-system.l2c.Writeback_hits::0 816294 # number of Writeback hits
-system.l2c.Writeback_hits::total 816294 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 172 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1 53 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 225 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0 18 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1 19 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 37 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0 170288 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1 12569 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 182857 # number of ReadExReq hits
-system.l2c.demand_hits::0 1829683 # number of demand (read+write) hits
-system.l2c.demand_hits::1 131760 # number of demand (read+write) hits
-system.l2c.demand_hits::2 0 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1961443 # number of demand (read+write) hits
-system.l2c.overall_hits::0 1829683 # number of overall hits
-system.l2c.overall_hits::1 131760 # number of overall hits
-system.l2c.overall_hits::2 0 # number of overall hits
-system.l2c.overall_hits::total 1961443 # number of overall hits
-system.l2c.ReadReq_misses::0 302827 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 1953 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 304780 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 2453 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 495 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2948 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0 15 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1 74 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 89 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0 117546 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1 6196 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 123742 # number of ReadExReq misses
-system.l2c.demand_misses::0 420373 # number of demand (read+write) misses
-system.l2c.demand_misses::1 8149 # number of demand (read+write) misses
-system.l2c.demand_misses::2 0 # number of demand (read+write) misses
-system.l2c.demand_misses::total 428522 # number of demand (read+write) misses
-system.l2c.overall_misses::0 420373 # number of overall misses
-system.l2c.overall_misses::1 8149 # number of overall misses
-system.l2c.overall_misses::2 0 # number of overall misses
-system.l2c.overall_misses::total 428522 # number of overall misses
-system.l2c.ReadReq_miss_latency 15853640000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency 3024000 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency 416000 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency 6434878000 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency 22288518000 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 22288518000 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 1962222 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 121144 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2083366 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 816294 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 816294 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 2625 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 548 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3173 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0 33 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1 93 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 126 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 287834 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1 18765 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 306599 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 2250056 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 139909 # number of demand (read+write) accesses
-system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2389965 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 2250056 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 139909 # number of overall (read+write) accesses
-system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2389965 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.154329 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.016121 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.934476 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 0.903285 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0 0.454545 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1 0.795699 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.408381 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 0.330189 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.186828 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.058245 # miss rate for demand accesses
-system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
-system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.186828 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.058245 # miss rate for overall accesses
-system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
-system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0 52352.135047 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 8117583.205325 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 1232.776192 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 6109.090909 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::0 27733.333333 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1 5621.621622 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 54743.487656 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 1038553.582957 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0 53020.812469 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 2735123.082587 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency
-system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 53020.812469 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 2735123.082587 # average overall miss latency
-system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency
-system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 119935 # number of writebacks
-system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 11 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses 304769 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses 2948 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses 89 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses 123742 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses 428511 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 428511 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency 12195855000 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency 117981000 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency 3560000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency 4949974000 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency 17145829000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 17145829000 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 802314500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency 1391411500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 2193726000 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.155318 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 2.515758 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0 1.123048 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 5.379562 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::0 2.696970 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1 0.956989 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0 0.429908 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 6.594298 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0 0.190445 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 3.062784 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0.190445 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 3.062784 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.717580 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40020.691995 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40002.375911 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency 40012.576107 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40012.576107 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 41694 # number of replacements
-system.iocache.tagsinuse 0.563721 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 41710 # Sample count of references to valid blocks.
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1751545158000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1 0.563721 # Average occupied blocks per context
-system.iocache.occ_percent::1 0.035233 # Average percentage of cache occupancy
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.ReadReq_misses::1 174 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
-system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 41726 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 41726 # number of overall misses
-system.iocache.overall_misses::total 41726 # number of overall misses
-system.iocache.ReadReq_miss_latency 20052998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency 5721783806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency 5741836804 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 5741836804 # number of overall miss cycles
-system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115247.114943 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137701.766606 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137608.129320 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137608.129320 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 6176.122765 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 41520 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses 41726 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 41726 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency 11004998 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency 3560928000 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency 3571932998 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 3571932998 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 63247.114943 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85698.113208 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 85604.491157 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 85604.491157 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
-system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs 395 # Number of DMA write transactions.
-system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.dtb.fetch_hits 0 # ITB hits
-system.cpu0.dtb.fetch_misses 0 # ITB misses
-system.cpu0.dtb.fetch_acv 0 # ITB acv
-system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 8633623 # DTB read hits
-system.cpu0.dtb.read_misses 7443 # DTB read misses
-system.cpu0.dtb.read_acv 210 # DTB read access violations
-system.cpu0.dtb.read_accesses 490673 # DTB read accesses
-system.cpu0.dtb.write_hits 6044743 # DTB write hits
-system.cpu0.dtb.write_misses 813 # DTB write misses
-system.cpu0.dtb.write_acv 134 # DTB write access violations
-system.cpu0.dtb.write_accesses 187452 # DTB write accesses
-system.cpu0.dtb.data_hits 14678366 # DTB hits
-system.cpu0.dtb.data_misses 8256 # DTB misses
-system.cpu0.dtb.data_acv 344 # DTB access violations
-system.cpu0.dtb.data_accesses 678125 # DTB accesses
-system.cpu0.itb.fetch_hits 3853057 # ITB hits
-system.cpu0.itb.fetch_misses 3871 # ITB misses
-system.cpu0.itb.fetch_acv 184 # ITB acv
-system.cpu0.itb.fetch_accesses 3856928 # ITB accesses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.read_acv 0 # DTB read access violations
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.write_acv 0 # DTB write access violations
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.data_hits 0 # DTB hits
-system.cpu0.itb.data_misses 0 # DTB misses
-system.cpu0.itb.data_acv 0 # DTB access violations
-system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 3916023774 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.num_insts 54072652 # Number of instructions executed
-system.cpu0.num_int_alu_accesses 50043234 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses
-system.cpu0.num_func_calls 1426863 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 6237040 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 50043234 # number of integer instructions
-system.cpu0.num_fp_insts 293967 # number of float instructions
-system.cpu0.num_int_register_reads 68528072 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 37080372 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written
-system.cpu0.num_mem_refs 14724357 # number of memory refs
-system.cpu0.num_load_insts 8664914 # Number of load instructions
-system.cpu0.num_store_insts 6059443 # Number of store instructions
-system.cpu0.num_idle_cycles 3680034047.555842 # Number of idle cycles
-system.cpu0.num_busy_cycles 235989726.444158 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.060263 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.939737 # Percentage of idle cycles
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6380 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 202972 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 72739 40.62% 40.62% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 104211 58.20% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 179062 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 71372 49.27% 49.27% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 71366 49.27% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 144850 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1899667899000 97.02% 97.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 79058000 0.00% 97.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 565985500 0.03% 97.05% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 4729500 0.00% 97.05% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 57694185000 2.95% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1958011857000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.981207 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.684822 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
-system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
-system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
-system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
-system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
-system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
-system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
-system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
-system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
-system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
-system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
-system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
-system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
-system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
-system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
-system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
-system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
-system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
-system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
-system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
-system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
-system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
-system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
-system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
-system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 222 # number of syscalls executed
-system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3894 2.07% 2.12% # number of callpals executed
-system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 172198 91.50% 93.64% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed
-system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed
-system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed
-system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 188203 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 7302 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches
-system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1283
-system.cpu0.kern.mode_good::user 1283
-system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3895 # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 915147 # number of replacements
-system.cpu0.icache.tagsinuse 508.800486 # Cycle average of tags in use
-system.cpu0.icache.total_refs 53165471 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 915659 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 58.062522 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 36696092000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 508.800486 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.993751 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::0 53165471 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 53165471 # number of ReadReq hits
-system.cpu0.icache.demand_hits::0 53165471 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 53165471 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::0 53165471 # number of overall hits
-system.cpu0.icache.overall_hits::1 0 # number of overall hits
-system.cpu0.icache.overall_hits::total 53165471 # number of overall hits
-system.cpu0.icache.ReadReq_misses::0 915781 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 915781 # number of ReadReq misses
-system.cpu0.icache.demand_misses::0 915781 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 915781 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::0 915781 # number of overall misses
-system.cpu0.icache.overall_misses::1 0 # number of overall misses
-system.cpu0.icache.overall_misses::total 915781 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency 13429132500 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency 13429132500 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency 13429132500 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::0 54081252 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 54081252 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::0 54081252 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 54081252 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::0 54081252 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::0 0.016933 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::0 0.016933 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::0 0.016933 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::0 14664.130944 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::0 14664.130944 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::0 14664.130944 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks 55 # number of writebacks
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses 915781 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses 915781 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses 915781 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 10681093500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency 10681093500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency 10681093500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.016933 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::0 0.016933 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::0 0.016933 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11663.370937 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11663.370937 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11663.370937 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 1338438 # number of replacements
-system.cpu0.dcache.tagsinuse 502.524901 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 13348404 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 1338837 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 9.970149 # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0 503.524900 # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0 0.983447 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::0 7421006 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7421006 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::0 5560133 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 5560133 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::0 176505 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 176505 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::0 191674 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 191674 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::0 12981139 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 12981139 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::0 12981139 # number of overall hits
-system.cpu0.dcache.overall_hits::1 0 # number of overall hits
-system.cpu0.dcache.overall_hits::total 12981139 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::0 1036101 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1036101 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::0 291536 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 291536 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::0 16544 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 16544 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::0 410 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 410 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::0 1327637 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1327637 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::0 1327637 # number of overall misses
-system.cpu0.dcache.overall_misses::1 0 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1327637 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency 26570279500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency 9109954000 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency 234949000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency 2973000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency 35680233500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency 35680233500 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::0 8457107 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8457107 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::0 5851669 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 5851669 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::0 193049 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 193049 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::0 192084 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 192084 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::0 14308776 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 14308776 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::0 14308776 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::0 0.122512 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::0 0.049821 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.085698 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::0 0.002134 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::0 0.092785 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0 0.092785 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 25644.487844 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 31248.127161 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14201.462766 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 7251.219512 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::0 26874.991809 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0 26874.991809 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks 786441 # number of writebacks
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses 1036101 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses 291536 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 16544 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses 410 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses 1327637 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses 1327637 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 23461938500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency 8235346000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 185317000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1743000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency 31697284500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency 31697284500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 884470000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1242107000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency 2126577000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122512 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049821 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.085698 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.002134 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::0 0.092785 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0 0.092785 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22644.451168 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 28248.127161 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11201.462766 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 4251.219512 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 23874.963186 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 23874.963186 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dtb.fetch_hits 0 # ITB hits
-system.cpu1.dtb.fetch_misses 0 # ITB misses
-system.cpu1.dtb.fetch_acv 0 # ITB acv
-system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1050117 # DTB read hits
-system.cpu1.dtb.read_misses 2992 # DTB read misses
-system.cpu1.dtb.read_acv 0 # DTB read access violations
-system.cpu1.dtb.read_accesses 239363 # DTB read accesses
-system.cpu1.dtb.write_hits 651208 # DTB write hits
-system.cpu1.dtb.write_misses 341 # DTB write misses
-system.cpu1.dtb.write_acv 29 # DTB write access violations
-system.cpu1.dtb.write_accesses 105247 # DTB write accesses
-system.cpu1.dtb.data_hits 1701325 # DTB hits
-system.cpu1.dtb.data_misses 3333 # DTB misses
-system.cpu1.dtb.data_acv 29 # DTB access violations
-system.cpu1.dtb.data_accesses 344610 # DTB accesses
-system.cpu1.itb.fetch_hits 1493438 # ITB hits
-system.cpu1.itb.fetch_misses 1216 # ITB misses
-system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 1494654 # ITB accesses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.read_acv 0 # DTB read access violations
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.write_acv 0 # DTB write access violations
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.data_hits 0 # DTB hits
-system.cpu1.itb.data_misses 0 # DTB misses
-system.cpu1.itb.data_acv 0 # DTB access violations
-system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3917294190 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.num_insts 5282991 # Number of instructions executed
-system.cpu1.num_int_alu_accesses 4948310 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses
-system.cpu1.num_func_calls 158031 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 510974 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 4948310 # number of integer instructions
-system.cpu1.num_fp_insts 34031 # number of float instructions
-system.cpu1.num_int_register_reads 6886066 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 3732878 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written
-system.cpu1.num_mem_refs 1710778 # number of memory refs
-system.cpu1.num_load_insts 1056124 # Number of load instructions
-system.cpu1.num_store_insts 654654 # Number of store instructions
-system.cpu1.num_idle_cycles 3898237020.998010 # Number of idle cycles
-system.cpu1.num_busy_cycles 19057169.001990 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.004865 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.995135 # Percentage of idle cycles
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2318 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 36191 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 9289 32.15% 32.15% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1969 6.81% 38.96% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 88 0.30% 39.26% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 17551 60.74% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 28897 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 9279 45.20% 45.20% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1969 9.59% 54.80% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 88 0.43% 55.22% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 9191 44.78% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 20527 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1917878582000 97.92% 97.92% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 507844000 0.03% 97.94% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 54239000 0.00% 97.95% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 40205672000 2.05% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1958646337000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.998923 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.523674 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
-system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
-system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
-system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
-system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
-system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
-system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
-system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
-system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
-system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
-system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
-system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
-system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 104 # number of syscalls executed
-system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 337 1.14% 1.17% # number of callpals executed
-system.cpu1.kern.callpal::tbi 3 0.01% 1.18% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.02% 1.20% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 24309 82.25% 83.46% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2170 7.34% 90.80% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 90.80% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 90.82% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.01% 90.83% # number of callpals executed
-system.cpu1.kern.callpal::rti 2530 8.56% 99.39% # number of callpals executed
-system.cpu1.kern.callpal::callsys 136 0.46% 99.85% # number of callpals executed
-system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 29554 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 804 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2064 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 477
-system.cpu1.kern.mode_good::user 464
-system.cpu1.kern.mode_good::idle 13
-system.cpu1.kern.mode_switch_good::kernel 0.593284 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.006298 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 1.599582 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 3571416000 0.18% 0.18% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1745054000 0.09% 0.27% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1953329865000 99.73% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 338 # number of times the context was actually changed
-system.cpu1.icache.replacements 86457 # number of replacements
-system.cpu1.icache.tagsinuse 419.807616 # Cycle average of tags in use
-system.cpu1.icache.total_refs 5199349 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 86969 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 59.783935 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1942711132000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0 419.807616 # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0 0.819937 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0 5199349 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 5199349 # number of ReadReq hits
-system.cpu1.icache.demand_hits::0 5199349 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 5199349 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::0 5199349 # number of overall hits
-system.cpu1.icache.overall_hits::1 0 # number of overall hits
-system.cpu1.icache.overall_hits::total 5199349 # number of overall hits
-system.cpu1.icache.ReadReq_misses::0 87005 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 87005 # number of ReadReq misses
-system.cpu1.icache.demand_misses::0 87005 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 87005 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0 87005 # number of overall misses
-system.cpu1.icache.overall_misses::1 0 # number of overall misses
-system.cpu1.icache.overall_misses::total 87005 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency 1260607500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency 1260607500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency 1260607500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0 5286354 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 5286354 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::0 5286354 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 5286354 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::0 5286354 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0 0.016458 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0 0.016458 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::0 0.016458 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14488.908683 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::0 14488.908683 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0 14488.908683 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks 14 # number of writebacks
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses 87005 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses 87005 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses 87005 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency 999558500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency 999558500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency 999558500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.016458 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::0 0.016458 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0 0.016458 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11488.517901 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11488.517901 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11488.517901 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 52960 # number of replacements
-system.cpu1.dcache.tagsinuse 389.521271 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 1644934 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 53472 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 30.762530 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 1942411783000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0 389.521271 # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0 0.760784 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0 1003161 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 1003161 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0 616899 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 616899 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0 11784 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 11784 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::0 11526 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 11526 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0 1620060 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 1620060 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0 1620060 # number of overall hits
-system.cpu1.dcache.overall_hits::1 0 # number of overall hits
-system.cpu1.dcache.overall_hits::total 1620060 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0 37113 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 37113 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0 20421 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 20421 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0 982 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 982 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0 505 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 505 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0 57534 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 57534 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0 57534 # number of overall misses
-system.cpu1.dcache.overall_misses::1 0 # number of overall misses
-system.cpu1.dcache.overall_misses::total 57534 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency 533263000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency 556796000 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency 13079000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency 6416000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency 1090059000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency 1090059000 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0 1040274 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 1040274 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::0 637320 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 637320 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0 12766 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0 12031 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 12031 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0 1677594 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 1677594 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0 1677594 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0 0.035676 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0 0.032042 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.076923 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.041975 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0 0.034296 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0 0.034296 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 14368.630938 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 27265.853778 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12704.950495 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::0 18946.344770 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 18946.344770 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 29784 # number of writebacks
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses 37113 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses 20421 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses 982 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses 505 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses 57534 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses 57534 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 421922000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency 495533000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10133000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency 4901000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency 917455000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency 917455000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 11413500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 298050500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency 309464000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035676 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.032042 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.076923 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.041975 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::0 0.034296 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0 0.034296 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11368.577048 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 24265.853778 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10318.737271 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9704.950495 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 15946.310008 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 15946.310008 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
deleted file mode 100644
index aa80e0b5e..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
+++ /dev/null
@@ -1,113 +0,0 @@
-M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
- Got Configuration 623
- memsize 8000000 pages 4000
- First free page after ROM 0xFFFFFC0000018000
- HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
- kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
- CPU Clock at 2000 MHz IntrClockFrequency=1024
- Booting with 2 processor(s)
- KSP: 0x20043FE8 PTBR 0x20
- KSP: 0x20043FE8 PTBR 0x20
- Console Callback at 0x0, fixup at 0x0, crb offset: 0x790
- Memory cluster 0 [0 - 392]
- Memory cluster 1 [392 - 15992]
- Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
- ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
- Bootstraping CPU 1 with sp=0xFFFFFC0000076000
- unix_boot_mem ends at FFFFFC0000078000
- k_argc = 0
- jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
- Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
- CallbackFixup 0 18000, t7=FFFFFC000070C000
- Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
- Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
- Major Options: SMP LEGACY_START VERBOSE_MCHECK
- Command line: root=/dev/hda1 console=ttyS0
- memcluster 0, usage 1, start 0, end 392
- memcluster 1, usage 0, start 392, end 16384
- freeing pages 1069:16384
- reserving pages 1069:1070
- 4096K Bcache detected; load hit latency 40 cycles, load miss latency 123 cycles
- SMP: 2 CPUs probed -- cpu_present_mask = 3
- Built 1 zonelists
- Kernel command line: root=/dev/hda1 console=ttyS0
- PID hash table entries: 1024 (order: 10, 32768 bytes)
- Using epoch = 1900
- Console: colour dummy device 80x25
- Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
- Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
- Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
- Mount-cache hash table entries: 512
- SMP starting up secondaries.
- Slave CPU 1 console command START
-SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
- Brought up 2 CPUs
- SMP: Total of 2 processors activated (8000.15 BogoMIPS).
- NET: Registered protocol family 16
- EISA bus registered
- pci: enabling save/restore of SRM state
- SCSI subsystem initialized
- srm_env: version 0.0.5 loaded successfully
- Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
- Initializing Cryptographic API
- rtc: Standard PC (1900) epoch (1900) detected
- Real Time Clock Driver v1.12
- Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
- ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
- io scheduler noop registered
- io scheduler anticipatory registered
- io scheduler deadline registered
- io scheduler cfq registered
- loop: loaded (max 8 devices)
- nbd: registered device at major 43
- ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
- PCI: Setting latency timer of device 0000:00:01.0 to 64
- eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
- eth0: enabling optical transceiver
- eth0: using 64 bit addressing.
- eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
- tun: Universal TUN/TAP device driver, 1.6
- tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
- Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
- ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
- PIIX4: IDE controller at PCI slot 0000:00:00.0
- PIIX4: chipset revision 0
- PIIX4: 100% native mode on irq 31
- PCI: Setting latency timer of device 0000:00:00.0 to 64
- ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
- ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
- hda: M5 IDE Disk, ATA DISK drive
- hdb: M5 IDE Disk, ATA DISK drive
- ide0 at 0x8410-0x8417,0x8422 on irq 31
- hda: max request size: 128KiB
- hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
- hda: cache flushes not supported
- hda: hda1
- hdb: max request size: 128KiB
- hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
- hdb: cache flushes not supported
- hdb: unknown partition table
- mice: PS/2 mouse device common for all mice
- NET: Registered protocol family 2
- IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
- TCP established hash table entries: 16384 (order: 5, 262144 bytes)
- TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
- TCP: Hash tables configured (established 16384 bind 16384)
- TCP reno registered
- ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
- ip_tables: (C) 2000-2002 Netfilter core team
- arp_tables: (C) 2002 David S. Miller
- TCP bic registered
- Initializing IPsec netlink socket
- NET: Registered protocol family 1
- NET: Registered protocol family 17
- NET: Registered protocol family 15
- Bridge firewalling registered
- 802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
- All bugs added by David S. Miller <davem@redhat.com>
- VFS: Mounted root (ext2 filesystem) readonly.
- Freeing unused kernel memory: 224k freed
- init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
-mounting filesystems...
-EXT2-fs warning: checktime reached, running e2fsck is recommended
- loading script...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
deleted file mode 100644
index 54195aa23..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ /dev/null
@@ -1,861 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
-boot_cpu_frequency=500
-boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
-init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
-load_addr_mask=1099511627775
-mem_mode=timing
-memories=system.physmem
-num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
-physmem=system.physmem
-readfile=tests/halt.sh
-symbolfile=
-system_rev=1024
-system_type=34
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[2]
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=8796093022208:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-system=system
-tracer=system.cpu.tracer
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu.dtb]
-type=AlphaTLB
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-
-[system.cpu.itb]
-type=AlphaTLB
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.disk0.image
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
-read_only=true
-
-[system.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.disk2.image
-
-[system.disk2.image]
-type=CowDiskImage
-children=child
-child=system.disk2.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk2.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=true
-width=64
-default=system.tsunami.pciconfig.pio
-port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:8589934591
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=true
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[32]
-mem_side=system.membus.port[3]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[4]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[1]
-
-[system.simple_disk]
-type=SimpleDisk
-children=disk
-disk=system.simple_disk.disk
-system=system
-
-[system.simple_disk.disk]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
-read_only=true
-
-[system.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
-intrctrl=system.intrctrl
-system=system
-
-[system.tsunami.backdoor]
-type=AlphaBackdoor
-cpu=system.cpu
-disk=system.simple_disk
-pio_addr=8804682956800
-pio_latency=1000
-platform=system.tsunami
-system=system
-terminal=system.terminal
-pio=system.iobus.port[25]
-
-[system.tsunami.cchip]
-type=TsunamiCChip
-pio_addr=8803072344064
-pio_latency=1000
-platform=system.tsunami
-system=system
-tsunami=system.tsunami
-pio=system.iobus.port[1]
-
-[system.tsunami.ethernet]
-type=NSGigE
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=52
-MinimumGrant=176
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clock=0
-config_latency=20000
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-hardware_address=00:90:00:00:00:01
-intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
-pio=system.iobus.port[29]
-
-[system.tsunami.fake_OROM]
-type=IsaFake
-fake_mem=false
-pio_addr=8796093677568
-pio_latency=1000
-pio_size=393216
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[9]
-
-[system.tsunami.fake_ata0]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848432
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[20]
-
-[system.tsunami.fake_ata1]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848304
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[21]
-
-[system.tsunami.fake_pnp_addr]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848569
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[10]
-
-[system.tsunami.fake_pnp_read0]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848451
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[12]
-
-[system.tsunami.fake_pnp_read1]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848515
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[13]
-
-[system.tsunami.fake_pnp_read2]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848579
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[14]
-
-[system.tsunami.fake_pnp_read3]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848643
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[15]
-
-[system.tsunami.fake_pnp_read4]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848707
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[16]
-
-[system.tsunami.fake_pnp_read5]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848771
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[17]
-
-[system.tsunami.fake_pnp_read6]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848835
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[18]
-
-[system.tsunami.fake_pnp_read7]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848899
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[19]
-
-[system.tsunami.fake_pnp_write]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615850617
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[11]
-
-[system.tsunami.fake_ppc]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848891
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[8]
-
-[system.tsunami.fake_sm_chip]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848816
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[3]
-
-[system.tsunami.fake_uart1]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848696
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[4]
-
-[system.tsunami.fake_uart2]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848936
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[5]
-
-[system.tsunami.fake_uart3]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848680
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[6]
-
-[system.tsunami.fake_uart4]
-type=IsaFake
-fake_mem=false
-pio_addr=8804615848944
-pio_latency=1000
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[7]
-
-[system.tsunami.fb]
-type=BadDevice
-devicename=FrameBuffer
-pio_addr=8804615848912
-pio_latency=1000
-platform=system.tsunami
-system=system
-pio=system.iobus.port[22]
-
-[system.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=0
-disks=system.disk0 system.disk2
-io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-system=system
-config=system.iobus.port[27]
-dma=system.iobus.port[28]
-pio=system.iobus.port[26]
-
-[system.tsunami.io]
-type=TsunamiIO
-frequency=976562500
-pio_addr=8804615847936
-pio_latency=1000
-platform=system.tsunami
-system=system
-time=Thu Jan 1 00:00:00 2009
-tsunami=system.tsunami
-year_is_bcd=false
-pio=system.iobus.port[23]
-
-[system.tsunami.pchip]
-type=TsunamiPChip
-pio_addr=8802535473152
-pio_latency=1000
-platform=system.tsunami
-system=system
-tsunami=system.tsunami
-pio=system.iobus.port[2]
-
-[system.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-pio_latency=1
-platform=system.tsunami
-size=16777216
-system=system
-pio=system.iobus.default
-
-[system.tsunami.uart]
-type=Uart8250
-pio_addr=8804615848952
-pio_latency=1000
-platform=system.tsunami
-system=system
-terminal=system.terminal
-pio=system.iobus.port[24]
-
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
deleted file mode 100755
index 0bcb6e870..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
+++ /dev/null
@@ -1,5 +0,0 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
deleted file mode 100755
index 826f2c28b..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ /dev/null
@@ -1,12 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:22:43
-gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
-Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-info: kernel located at: /dist/m5/system/binaries/vmlinux
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1915548867000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
deleted file mode 100644
index ac9598c08..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ /dev/null
@@ -1,646 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 1.915549 # Number of seconds simulated
-sim_ticks 1915548867000 # Number of ticks simulated
-final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1659827 # Simulator instruction rate (inst/s)
-host_tick_rate 56637748152 # Simulator tick rate (ticks/s)
-host_mem_usage 290988 # Number of bytes of host memory used
-host_seconds 33.82 # Real time elapsed on the host
-sim_insts 56137087 # Number of instructions simulated
-system.physmem.bytes_read 29663360 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10122368 # Number of bytes written to this memory
-system.physmem.num_reads 463490 # Number of read requests responded to by this memory
-system.physmem.num_writes 158162 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 15485567 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 492308 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 5284317 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 20769884 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 389289 # number of replacements
-system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use
-system.l2c.total_refs 2311163 # Total number of references to valid blocks.
-system.l2c.sampled_refs 421794 # Sample count of references to valid blocks.
-system.l2c.avg_refs 5.479364 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 11241.373247 # Average occupied blocks per context
-system.l2c.occ_blocks::1 23110.665097 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.171530 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.352641 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1710461 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits
-system.l2c.Writeback_hits::0 826671 # number of Writeback hits
-system.l2c.Writeback_hits::total 826671 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 6 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 185878 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits
-system.l2c.demand_hits::0 1896339 # number of demand (read+write) hits
-system.l2c.demand_hits::1 0 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits
-system.l2c.overall_hits::0 1896339 # number of overall hits
-system.l2c.overall_hits::1 0 # number of overall hits
-system.l2c.overall_hits::total 1896339 # number of overall hits
-system.l2c.ReadReq_misses::0 304138 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 7 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0 118294 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 118294 # number of ReadExReq misses
-system.l2c.demand_misses::0 422432 # number of demand (read+write) misses
-system.l2c.demand_misses::1 0 # number of demand (read+write) misses
-system.l2c.demand_misses::total 422432 # number of demand (read+write) misses
-system.l2c.overall_misses::0 422432 # number of overall misses
-system.l2c.overall_misses::1 0 # number of overall misses
-system.l2c.overall_misses::total 422432 # number of overall misses
-system.l2c.ReadReq_miss_latency 15820206500 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency 248000 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency 6151753000 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency 21971959500 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 21971959500 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 2014599 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2014599 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 826671 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 826671 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 13 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 304172 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 2318771 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2318771 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 2318771 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.150967 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.538462 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.388905 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.182179 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.182179 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0 52016.540189 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 35428.571429 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52003.930884 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0 52013.009194 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
-system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 52013.009194 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
-system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 116650 # number of writebacks
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses 304138 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses 7 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses 118294 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses 422432 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 422432 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency 12170545000 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency 320000 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency 4732225000 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency 16902770000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 16902770000 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency 1083819500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 1856492500 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.150967 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.538462 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0 0.388905 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0 0.182179 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0.182179 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.522105 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 45714.285714 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40003.930884 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency 40012.996175 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40012.996175 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 41685 # number of replacements
-system.iocache.tagsinuse 1.340325 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1 1.340325 # Average occupied blocks per context
-system.iocache.occ_percent::1 0.083770 # Average percentage of cache occupancy
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.ReadReq_misses::1 173 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
-system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 41725 # number of overall misses
-system.iocache.overall_misses::total 41725 # number of overall misses
-system.iocache.ReadReq_miss_latency 19940998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency 5722300806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency 5742241804 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 5742241804 # number of overall miss cycles
-system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115265.884393 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137714.208847 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137621.133709 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137621.133709 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 41512 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency 10944998 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency 3561447990 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency 3572392988 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 3572392988 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 63265.884393 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85710.627407 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 85617.567118 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 85617.567118 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
-system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs 395 # Number of DMA write transactions.
-system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9057511 # DTB read hits
-system.cpu.dtb.read_misses 10312 # DTB read misses
-system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_accesses 728817 # DTB read accesses
-system.cpu.dtb.write_hits 6352446 # DTB write hits
-system.cpu.dtb.write_misses 1140 # DTB write misses
-system.cpu.dtb.write_acv 157 # DTB write access violations
-system.cpu.dtb.write_accesses 291929 # DTB write accesses
-system.cpu.dtb.data_hits 15409957 # DTB hits
-system.cpu.dtb.data_misses 11452 # DTB misses
-system.cpu.dtb.data_acv 367 # DTB access violations
-system.cpu.dtb.data_accesses 1020746 # DTB accesses
-system.cpu.itb.fetch_hits 4973520 # ITB hits
-system.cpu.itb.fetch_misses 4997 # ITB misses
-system.cpu.itb.fetch_acv 184 # ITB acv
-system.cpu.itb.fetch_accesses 4978517 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 3831097734 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 56137087 # Number of instructions executed
-system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses
-system.cpu.num_func_calls 1482242 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls
-system.cpu.num_int_insts 52011214 # number of integer instructions
-system.cpu.num_fp_insts 324192 # number of float instructions
-system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read
-system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written
-system.cpu.num_mem_refs 15462519 # number of memory refs
-system.cpu.num_load_insts 9094324 # Number of load instructions
-system.cpu.num_store_insts 6368195 # Number of store instructions
-system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles
-system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles
-system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.936531 # Percentage of idle cycles
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211932 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74887 40.89% 40.89% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 106197 57.98% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 183146 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73520 49.31% 49.31% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22 1931 1.30% 50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73520 49.31% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 149102 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1857816228500 96.99% 96.99% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 79988500 0.00% 96.99% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 554693000 0.03% 97.02% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 57097199000 2.98% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1915548109000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
-system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
-system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
-system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
-system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
-system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
-system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
-system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
-system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
-system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
-system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
-system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
-system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
-system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
-system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
-system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
-system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
-system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
-system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
-system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
-system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
-system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
-system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
-system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
-system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
-system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
-system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
-system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
-system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
-system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
-system.cpu.kern.syscall::total 326 # number of syscalls executed
-system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx 4173 2.16% 2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
-system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175927 91.22% 93.41% # number of callpals executed
-system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
-system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
-system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
-system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
-system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192868 # number of callpals executed
-system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches
-system.cpu.kern.mode_good::kernel 1906
-system.cpu.kern.mode_good::user 1738
-system.cpu.kern.mode_good::idle 168
-system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 1.403193 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4174 # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 927683 # number of replacements
-system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use
-system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 508.721464 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.993597 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0 55220553 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits
-system.cpu.icache.demand_hits::0 55220553 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0 55220553 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 55220553 # number of overall hits
-system.cpu.icache.ReadReq_misses::0 928354 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses
-system.cpu.icache.demand_misses::0 928354 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 928354 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0 928354 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 928354 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 13616370500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 13616370500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 13616370500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0 56148907 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 56148907 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0 56148907 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 56148907 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0 56148907 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0 0.016534 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0 0.016534 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0 0.016534 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14667.218001 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14667.218001 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14667.218001 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 85 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 928354 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 928354 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 928354 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 10830625500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 10830625500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 10830625500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016534 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0 0.016534 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0 0.016534 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11666.482290 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11666.482290 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11666.482290 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1390115 # number of replacements
-system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14038335 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 10.094968 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 511.984023 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999969 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0 7807536 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7807536 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0 5848554 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 5848554 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::0 183025 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0 199203 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 199203 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0 13656090 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13656090 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0 13656090 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 13656090 # number of overall hits
-system.cpu.dcache.ReadReq_misses::0 1069110 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1069110 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0 304335 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0 17201 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 17201 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::0 1373445 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1373445 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0 1373445 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 1373445 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 27121920500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 9228484000 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency 245980000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency 36350404500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 36350404500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0 8876646 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 8876646 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0 6152889 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6152889 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0 200226 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 200226 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0 199203 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 199203 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0 15029535 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15029535 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0 15029535 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.120441 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.049462 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085908 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.091383 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.091383 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 25368.690313 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 30323.439631 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14300.331376 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 26466.589124 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 26466.589124 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 826586 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 1069110 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 304335 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses 17201 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 1373445 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 1373445 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 23914545000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 8315479000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 194377000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 32230024000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 32230024000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1199607500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 2062370500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120441 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.049462 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.085908 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0 0.091383 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0.091383 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22368.647754 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27323.439631 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11300.331376 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23466.555996 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23466.555996 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
deleted file mode 100644
index ff644ed3f..000000000
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
+++ /dev/null
@@ -1,108 +0,0 @@
-M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
- Got Configuration 623
- memsize 8000000 pages 4000
- First free page after ROM 0xFFFFFC0000018000
- HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
- kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
- CPU Clock at 2000 MHz IntrClockFrequency=1024
- Booting with 1 processor(s)
- KSP: 0x20043FE8 PTBR 0x20
- Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
- Memory cluster 0 [0 - 392]
- Memory cluster 1 [392 - 15992]
- Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
- ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
- unix_boot_mem ends at FFFFFC0000076000
- k_argc = 0
- jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
- CallbackFixup 0 18000, t7=FFFFFC000070C000
- Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
- Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
- Major Options: SMP LEGACY_START VERBOSE_MCHECK
- Command line: root=/dev/hda1 console=ttyS0
- memcluster 0, usage 1, start 0, end 392
- memcluster 1, usage 0, start 392, end 16384
- freeing pages 1069:16384
- reserving pages 1069:1070
- 4096K Bcache detected; load hit latency 40 cycles, load miss latency 124 cycles
- SMP: 1 CPUs probed -- cpu_present_mask = 1
- Built 1 zonelists
- Kernel command line: root=/dev/hda1 console=ttyS0
- PID hash table entries: 1024 (order: 10, 32768 bytes)
- Using epoch = 1900
- Console: colour dummy device 80x25
- Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
- Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
- Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
- Mount-cache hash table entries: 512
- SMP mode deactivated.
- Brought up 1 CPUs
- SMP: Total of 1 processors activated (4002.20 BogoMIPS).
- NET: Registered protocol family 16
- EISA bus registered
- pci: enabling save/restore of SRM state
- SCSI subsystem initialized
- srm_env: version 0.0.5 loaded successfully
- Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
- Initializing Cryptographic API
- rtc: Standard PC (1900) epoch (1900) detected
- Real Time Clock Driver v1.12
- Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
- ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
- io scheduler noop registered
- io scheduler anticipatory registered
- io scheduler deadline registered
- io scheduler cfq registered
- loop: loaded (max 8 devices)
- nbd: registered device at major 43
- ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
- PCI: Setting latency timer of device 0000:00:01.0 to 64
- eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
- eth0: enabling optical transceiver
- eth0: using 64 bit addressing.
- eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
- tun: Universal TUN/TAP device driver, 1.6
- tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
- Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
- ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
- PIIX4: IDE controller at PCI slot 0000:00:00.0
- PIIX4: chipset revision 0
- PIIX4: 100% native mode on irq 31
- PCI: Setting latency timer of device 0000:00:00.0 to 64
- ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
- ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
- hda: M5 IDE Disk, ATA DISK drive
- hdb: M5 IDE Disk, ATA DISK drive
- ide0 at 0x8410-0x8417,0x8422 on irq 31
- hda: max request size: 128KiB
- hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
- hda: cache flushes not supported
- hda: hda1
- hdb: max request size: 128KiB
- hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
- hdb: cache flushes not supported
- hdb: unknown partition table
- mice: PS/2 mouse device common for all mice
- NET: Registered protocol family 2
- IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
- TCP established hash table entries: 16384 (order: 5, 262144 bytes)
- TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
- TCP: Hash tables configured (established 16384 bind 16384)
- TCP reno registered
- ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
- ip_tables: (C) 2000-2002 Netfilter core team
- arp_tables: (C) 2002 David S. Miller
- TCP bic registered
- Initializing IPsec netlink socket
- NET: Registered protocol family 1
- NET: Registered protocol family 17
- NET: Registered protocol family 15
- Bridge firewalling registered
- 802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
- All bugs added by David S. Miller <davem@redhat.com>
- VFS: Mounted root (ext2 filesystem) readonly.
- Freeing unused kernel memory: 224k freed
- init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
-mounting filesystems...
-EXT2-fs warning: checktime reached, running e2fsck is recommended
- loading script...
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
deleted file mode 100644
index 84e5e8c3f..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ /dev/null
@@ -1,846 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_cpu_frequency=500
-boot_loader=/dist/m5/system/binaries/boot.arm
-boot_loader_mem=system.nvmem
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-flags_addr=268435504
-gic_cpu_addr=520093952
-init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-load_addr_mask=268435455
-machine_type=RealView_PBX
-mem_mode=atomic
-memories=system.physmem system.nvmem
-midr_regval=890224640
-num_work_ids=16
-physmem=system.physmem
-readfile=tests/halt.sh
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[7]
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=268435456:520093695 1073741824:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-arm-ael.img
-read_only=true
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
-sys=system
-port=system.toL2Bus.port[4]
-
-[system.cpu0.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
-sys=system
-port=system.toL2Bus.port[3]
-
-[system.cpu0.tracer]
-type=ExeTracer
-
-[system.cpu1]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
-checker=Null
-clock=500
-cpu_id=1
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu1.tracer
-width=1
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[6]
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
-sys=system
-port=system.toL2Bus.port[8]
-
-[system.cpu1.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[5]
-
-[system.cpu1.interrupts]
-type=ArmInterrupts
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
-sys=system
-port=system.toL2Bus.port[7]
-
-[system.cpu1.tracer]
-type=ExeTracer
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:268435455
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=false
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[28]
-mem_side=system.membus.port[8]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[9]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.realview
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.nvmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=2147483648:2214592511
-zero=true
-port=system.membus.port[1]
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=true
-port=system.membus.port[2]
-
-[system.realview]
-type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
-intrctrl=system.intrctrl
-pci_cfg_base=0
-system=system
-
-[system.realview.a9scu]
-type=A9SCU
-pio_addr=520093696
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.membus.port[5]
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268451840
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[24]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=402653184
-BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
-BAR1LegacyIO=true
-BAR1Size=1
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=2
-disks=system.cf0
-io_shift=1
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=2
-pci_dev=7
-pci_func=0
-pio_latency=1000
-platform=system.realview
-system=system
-config=system.iobus.port[10]
-dma=system.iobus.port[11]
-pio=system.iobus.port[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clock=41667
-gic=system.realview.gic
-int_num=55
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pio_addr=268566528
-pio_latency=10000
-platform=system.realview
-system=system
-vnc=system.vncserver
-dma=system.iobus.port[6]
-pio=system.iobus.port[5]
-
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268632064
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[12]
-
-[system.realview.flash_fake]
-type=IsaFake
-fake_mem=true
-pio_addr=1073741824
-pio_latency=1000
-pio_size=536870912
-platform=system.realview
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[27]
-
-[system.realview.gic]
-type=Gic
-cpu_addr=520093952
-cpu_pio_delay=10000
-dist_addr=520097792
-dist_pio_delay=10000
-int_latency=10000
-it_lines=128
-platform=system.realview
-system=system
-pio=system.membus.port[3]
-
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[19]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[20]
-
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[21]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-gic=system.realview.gic
-int_delay=1000000
-int_num=52
-is_mouse=false
-pio_addr=268460032
-pio_latency=1000
-platform=system.realview
-system=system
-vnc=system.vncserver
-pio=system.iobus.port[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-gic=system.realview.gic
-int_delay=1000000
-int_num=53
-is_mouse=true
-pio_addr=268464128
-pio_latency=1000
-platform=system.realview
-system=system
-vnc=system.vncserver
-pio=system.iobus.port[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-fake_mem=false
-pio_addr=520101888
-pio_latency=1000
-pio_size=4095
-platform=system.realview
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.port[4]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clock=1000
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-pio_addr=520095232
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.membus.port[6]
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268455936
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[25]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-idreg=0
-pio_addr=268435456
-pio_latency=1000
-platform=system.realview
-proc_id0=201326592
-proc_id1=201327138
-system=system
-pio=system.iobus.port[2]
-
-[system.realview.rtc_fake]
-type=AmbaFake
-amba_id=266289
-ignore_access=false
-pio_addr=268529664
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[26]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[23]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[16]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=true
-pio_addr=268439552
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[17]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268488704
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[22]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clock0=1000000
-clock1=1000000
-gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clock0=1000000
-clock1=1000000
-gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[4]
-
-[system.realview.uart]
-type=Pl011
-end_on_eot=false
-gic=system.realview.gic
-int_delay=100000
-int_num=44
-pio_addr=268472320
-pio_latency=1000
-platform=system.realview
-system=system
-terminal=system.terminal
-pio=system.iobus.port[1]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268476416
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268480512
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268484608
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[15]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268500992
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[18]
-
-[system.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.vncserver]
-type=VncServer
-frame_capture=false
-number=0
-port=5900
-
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
deleted file mode 100755
index 04178bb32..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
+++ /dev/null
@@ -1,18 +0,0 @@
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
deleted file mode 100755
index 417579719..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ /dev/null
@@ -1,12 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:21:22
-gem5 started Jan 23 2012 04:25:02
-gem5 executing on zizzer
-command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2411694099500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
deleted file mode 100644
index 2ca0aa5cb..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ /dev/null
@@ -1,719 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.411694 # Number of seconds simulated
-sim_ticks 2411694099500 # Number of ticks simulated
-final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2039542 # Simulator instruction rate (inst/s)
-host_tick_rate 61821688958 # Simulator tick rate (ticks/s)
-host_mem_usage 378872 # Number of bytes of host memory used
-host_seconds 39.01 # Real time elapsed on the host
-sim_insts 79563488 # Number of instructions simulated
-system.nvmem.bytes_read 68 # Number of bytes read from this memory
-system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
-system.nvmem.bytes_written 0 # Number of bytes written to this memory
-system.nvmem.num_reads 17 # Number of read requests responded to by this memory
-system.nvmem.num_writes 0 # Number of write requests responded to by this memory
-system.nvmem.num_other 0 # Number of other requests responded to by this memory
-system.nvmem.bw_read 28 # Total read bandwidth from this memory (bytes/s)
-system.nvmem.bw_inst_read 28 # Instruction read bandwidth from this memory (bytes/s)
-system.nvmem.bw_total 28 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read 123270308 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 1011392 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10185232 # Number of bytes written to this memory
-system.physmem.num_reads 14146769 # Number of read requests responded to by this memory
-system.physmem.num_writes 869038 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 51113575 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 419370 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 4223269 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 55336844 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 127720 # number of replacements
-system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use
-system.l2c.total_refs 1498989 # Total number of references to valid blocks.
-system.l2c.sampled_refs 156132 # Sample count of references to valid blocks.
-system.l2c.avg_refs 9.600780 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 4404.089299 # Average occupied blocks per context
-system.l2c.occ_blocks::1 6217.918720 # Average occupied blocks per context
-system.l2c.occ_blocks::2 14925.912843 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.067201 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.094878 # Average percentage of cache occupancy
-system.l2c.occ_percent::2 0.227751 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 706190 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 499815 # number of ReadReq hits
-system.l2c.ReadReq_hits::2 12920 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits
-system.l2c.Writeback_hits::0 580461 # number of Writeback hits
-system.l2c.Writeback_hits::total 580461 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 776 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1 523 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0 147 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1 202 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 349 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0 64831 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1 37797 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 102628 # number of ReadExReq hits
-system.l2c.demand_hits::0 771021 # number of demand (read+write) hits
-system.l2c.demand_hits::1 537612 # number of demand (read+write) hits
-system.l2c.demand_hits::2 12920 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits
-system.l2c.overall_hits::0 771021 # number of overall hits
-system.l2c.overall_hits::1 537612 # number of overall hits
-system.l2c.overall_hits::2 12920 # number of overall hits
-system.l2c.overall_hits::total 1321553 # number of overall hits
-system.l2c.ReadReq_misses::0 19675 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 15224 # number of ReadReq misses
-system.l2c.ReadReq_misses::2 52 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 34951 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 6349 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 3492 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 9841 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0 791 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1 531 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1322 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0 99048 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1 48785 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 147833 # number of ReadExReq misses
-system.l2c.demand_misses::0 118723 # number of demand (read+write) misses
-system.l2c.demand_misses::1 64009 # number of demand (read+write) misses
-system.l2c.demand_misses::2 52 # number of demand (read+write) misses
-system.l2c.demand_misses::total 182784 # number of demand (read+write) misses
-system.l2c.overall_misses::0 118723 # number of overall misses
-system.l2c.overall_misses::1 64009 # number of overall misses
-system.l2c.overall_misses::2 52 # number of overall misses
-system.l2c.overall_misses::total 182784 # number of overall misses
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 725865 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 515039 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2 12972 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 580461 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 7125 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 4015 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0 938 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1 733 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1671 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 163879 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1 86582 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 250461 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 889744 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 601621 # number of demand (read+write) accesses
-system.l2c.demand_accesses::2 12972 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 889744 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 601621 # number of overall (read+write) accesses
-system.l2c.overall_accesses::2 12972 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.027106 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.029559 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2 0.004009 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.060673 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.891088 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 0.869738 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0 0.843284 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1 0.724420 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.604397 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 0.563454 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.133435 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.106394 # miss rate for demand accesses
-system.l2c.demand_miss_rate::2 0.004009 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.243838 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.133435 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.106394 # miss rate for overall accesses
-system.l2c.overall_miss_rate::2 0.004009 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.243838 # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 111818 # number of writebacks
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 9339288 # DTB read hits
-system.cpu0.dtb.read_misses 5153 # DTB read misses
-system.cpu0.dtb.write_hits 6907876 # DTB write hits
-system.cpu0.dtb.write_misses 1048 # DTB write misses
-system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 9344441 # DTB read accesses
-system.cpu0.dtb.write_accesses 6908924 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 16247164 # DTB hits
-system.cpu0.dtb.misses 6201 # DTB misses
-system.cpu0.dtb.accesses 16253365 # DTB accesses
-system.cpu0.itb.inst_hits 34822552 # ITB inst hits
-system.cpu0.itb.inst_misses 2978 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses
-system.cpu0.itb.hits 34822552 # DTB hits
-system.cpu0.itb.misses 2978 # DTB misses
-system.cpu0.itb.accesses 34825530 # DTB accesses
-system.cpu0.numCycles 4823340800 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.num_insts 44975797 # Number of instructions executed
-system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses
-system.cpu0.num_func_calls 1311755 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4494669 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 39858123 # number of integer instructions
-system.cpu0.num_fp_insts 4945 # number of float instructions
-system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 42204131 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written
-system.cpu0.num_mem_refs 17030946 # number of memory refs
-system.cpu0.num_load_insts 9786549 # Number of load instructions
-system.cpu0.num_store_insts 7244397 # Number of store instructions
-system.cpu0.num_idle_cycles 4777543068.852608 # Number of idle cycles
-system.cpu0.num_busy_cycles 45797731.147393 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed
-system.cpu0.icache.replacements 504460 # number of replacements
-system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use
-system.cpu0.icache.total_refs 34319155 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 67.962491 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 511.627588 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.999273 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::0 34319155 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 34319155 # number of ReadReq hits
-system.cpu0.icache.demand_hits::0 34319155 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 34319155 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::0 34319155 # number of overall hits
-system.cpu0.icache.overall_hits::1 0 # number of overall hits
-system.cpu0.icache.overall_hits::total 34319155 # number of overall hits
-system.cpu0.icache.ReadReq_misses::0 504973 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses
-system.cpu0.icache.demand_misses::0 504973 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::0 504973 # number of overall misses
-system.cpu0.icache.overall_misses::1 0 # number of overall misses
-system.cpu0.icache.overall_misses::total 504973 # number of overall misses
-system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::0 34824128 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 34824128 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::0 34824128 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 34824128 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::0 34824128 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 34824128 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::0 0.014501 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::0 0.014501 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::0 0.014501 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks 24728 # number of writebacks
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 380107 # number of replacements
-system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 14708286 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 38.643068 # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0 479.716402 # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0 0.936946 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::0 7803296 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7803296 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::0 6534059 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 6534059 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::0 172314 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::0 174866 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::0 14337355 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 14337355 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::0 14337355 # number of overall hits
-system.cpu0.dcache.overall_hits::1 0 # number of overall hits
-system.cpu0.dcache.overall_hits::total 14337355 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::0 237350 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::0 183580 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 183580 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::0 9878 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 9878 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::0 7293 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 7293 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::0 420930 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::0 420930 # number of overall misses
-system.cpu0.dcache.overall_misses::1 0 # number of overall misses
-system.cpu0.dcache.overall_misses::total 420930 # number of overall misses
-system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::0 8040646 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8040646 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::0 6717639 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 6717639 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::0 182192 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::0 182159 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::0 14758285 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 14758285 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::0 14758285 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 14758285 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::0 0.029519 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::0 0.027328 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.054218 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::0 0.040036 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::0 0.028522 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0 0.028522 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks 339627 # number of writebacks
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 6258230 # DTB read hits
-system.cpu1.dtb.read_misses 2159 # DTB read misses
-system.cpu1.dtb.write_hits 4713962 # DTB write hits
-system.cpu1.dtb.write_misses 1181 # DTB write misses
-system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1498 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 6260389 # DTB read accesses
-system.cpu1.dtb.write_accesses 4715143 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 10972192 # DTB hits
-system.cpu1.dtb.misses 3340 # DTB misses
-system.cpu1.dtb.accesses 10975532 # DTB accesses
-system.cpu1.itb.inst_hits 27739434 # ITB inst hits
-system.cpu1.itb.inst_misses 1388 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1342 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 27740822 # ITB inst accesses
-system.cpu1.itb.hits 27739434 # DTB hits
-system.cpu1.itb.misses 1388 # DTB misses
-system.cpu1.itb.accesses 27740822 # DTB accesses
-system.cpu1.numCycles 4822838236 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.num_insts 34587691 # Number of instructions executed
-system.cpu1.num_int_alu_accesses 30998246 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses
-system.cpu1.num_func_calls 758024 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3375080 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 30998246 # number of integer instructions
-system.cpu1.num_fp_insts 5772 # number of float instructions
-system.cpu1.num_int_register_reads 156835040 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 33469179 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written
-system.cpu1.num_mem_refs 11415835 # number of memory refs
-system.cpu1.num_load_insts 6478994 # Number of load instructions
-system.cpu1.num_store_insts 4936841 # Number of store instructions
-system.cpu1.num_idle_cycles 4787960178.177661 # Number of idle cycles
-system.cpu1.num_busy_cycles 34878057.822339 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.007232 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.992768 # Percentage of idle cycles
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 33011 # number of quiesce instructions executed
-system.cpu1.icache.replacements 374406 # number of replacements
-system.cpu1.icache.tagsinuse 498.143079 # Cycle average of tags in use
-system.cpu1.icache.total_refs 27365572 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 374918 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 72.990819 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 69956143000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0 498.143079 # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0 0.972936 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0 27365572 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 27365572 # number of ReadReq hits
-system.cpu1.icache.demand_hits::0 27365572 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 27365572 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::0 27365572 # number of overall hits
-system.cpu1.icache.overall_hits::1 0 # number of overall hits
-system.cpu1.icache.overall_hits::total 27365572 # number of overall hits
-system.cpu1.icache.ReadReq_misses::0 374920 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 374920 # number of ReadReq misses
-system.cpu1.icache.demand_misses::0 374920 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 374920 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0 374920 # number of overall misses
-system.cpu1.icache.overall_misses::1 0 # number of overall misses
-system.cpu1.icache.overall_misses::total 374920 # number of overall misses
-system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0 27740492 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 27740492 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::0 27740492 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 27740492 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::0 27740492 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 27740492 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0 0.013515 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0 0.013515 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::0 0.013515 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks 13905 # number of writebacks
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 247434 # number of replacements
-system.cpu1.dcache.tagsinuse 444.903488 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 9876826 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 247805 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 39.857251 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 69253206000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0 444.903488 # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0 0.868952 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0 5955973 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 5955973 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0 3777038 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 3777038 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0 59593 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::0 60090 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0 9733011 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 9733011 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0 9733011 # number of overall hits
-system.cpu1.dcache.overall_hits::1 0 # number of overall hits
-system.cpu1.dcache.overall_hits::total 9733011 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0 165799 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 165799 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0 111467 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0 10725 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0 10198 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0 277266 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 277266 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0 277266 # number of overall misses
-system.cpu1.dcache.overall_misses::1 0 # number of overall misses
-system.cpu1.dcache.overall_misses::total 277266 # number of overall misses
-system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0 6121772 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 6121772 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::0 3888505 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 3888505 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0 70318 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0 70288 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0 10010277 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 10010277 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0 10010277 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 10010277 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0 0.027083 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0 0.028666 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.152521 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.145089 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0 0.027698 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0 0.027698 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 202201 # number of writebacks
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 0 # number of replacements
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.avg_refs no_value # Average number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 0 # number of demand (read+write) misses
-system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 0 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
deleted file mode 100644
index 10632c381..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
+++ /dev/null
@@ -1 +0,0 @@
-build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
deleted file mode 100644
index ac162c148..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
deleted file mode 100644
index 5b5bd9164..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ /dev/null
@@ -1,719 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_cpu_frequency=500
-boot_loader=/dist/m5/system/binaries/boot.arm
-boot_loader_mem=system.nvmem
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-flags_addr=268435504
-gic_cpu_addr=520093952
-init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-load_addr_mask=268435455
-machine_type=RealView_PBX
-mem_mode=atomic
-memories=system.nvmem system.physmem
-midr_regval=890224640
-num_work_ids=16
-physmem=system.physmem
-readfile=tests/halt.sh
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[7]
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=268435456:520093695 1073741824:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-arm-ael.img
-read_only=true
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
-sys=system
-port=system.toL2Bus.port[4]
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
-sys=system
-port=system.toL2Bus.port[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:268435455
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=false
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[28]
-mem_side=system.membus.port[8]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[9]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.realview
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.nvmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=2147483648:2214592511
-zero=true
-port=system.membus.port[1]
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=true
-port=system.membus.port[2]
-
-[system.realview]
-type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
-intrctrl=system.intrctrl
-pci_cfg_base=0
-system=system
-
-[system.realview.a9scu]
-type=A9SCU
-pio_addr=520093696
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.membus.port[5]
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268451840
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[24]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=402653184
-BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
-BAR1LegacyIO=true
-BAR1Size=1
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=2
-disks=system.cf0
-io_shift=1
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=2
-pci_dev=7
-pci_func=0
-pio_latency=1000
-platform=system.realview
-system=system
-config=system.iobus.port[10]
-dma=system.iobus.port[11]
-pio=system.iobus.port[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clock=41667
-gic=system.realview.gic
-int_num=55
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pio_addr=268566528
-pio_latency=10000
-platform=system.realview
-system=system
-vnc=system.vncserver
-dma=system.iobus.port[6]
-pio=system.iobus.port[5]
-
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268632064
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[12]
-
-[system.realview.flash_fake]
-type=IsaFake
-fake_mem=true
-pio_addr=1073741824
-pio_latency=1000
-pio_size=536870912
-platform=system.realview
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[27]
-
-[system.realview.gic]
-type=Gic
-cpu_addr=520093952
-cpu_pio_delay=10000
-dist_addr=520097792
-dist_pio_delay=10000
-int_latency=10000
-it_lines=128
-platform=system.realview
-system=system
-pio=system.membus.port[3]
-
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[19]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[20]
-
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[21]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-gic=system.realview.gic
-int_delay=1000000
-int_num=52
-is_mouse=false
-pio_addr=268460032
-pio_latency=1000
-platform=system.realview
-system=system
-vnc=system.vncserver
-pio=system.iobus.port[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-gic=system.realview.gic
-int_delay=1000000
-int_num=53
-is_mouse=true
-pio_addr=268464128
-pio_latency=1000
-platform=system.realview
-system=system
-vnc=system.vncserver
-pio=system.iobus.port[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-fake_mem=false
-pio_addr=520101888
-pio_latency=1000
-pio_size=4095
-platform=system.realview
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.port[4]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clock=1000
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-pio_addr=520095232
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.membus.port[6]
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268455936
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[25]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-idreg=0
-pio_addr=268435456
-pio_latency=1000
-platform=system.realview
-proc_id0=201326592
-proc_id1=201327138
-system=system
-pio=system.iobus.port[2]
-
-[system.realview.rtc_fake]
-type=AmbaFake
-amba_id=266289
-ignore_access=false
-pio_addr=268529664
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[26]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[23]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[16]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=true
-pio_addr=268439552
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[17]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268488704
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[22]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clock0=1000000
-clock1=1000000
-gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clock0=1000000
-clock1=1000000
-gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[4]
-
-[system.realview.uart]
-type=Pl011
-end_on_eot=false
-gic=system.realview.gic
-int_delay=100000
-int_num=44
-pio_addr=268472320
-pio_latency=1000
-platform=system.realview
-system=system
-terminal=system.terminal
-pio=system.iobus.port[1]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268476416
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268480512
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268484608
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[15]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268500992
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[18]
-
-[system.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.vncserver]
-type=VncServer
-frame_capture=false
-number=0
-port=5900
-
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
deleted file mode 100755
index 9a28ceb37..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
+++ /dev/null
@@ -1,17 +0,0 @@
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
deleted file mode 100755
index e355498ce..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ /dev/null
@@ -1,12 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:21:22
-gem5 started Jan 23 2012 04:24:55
-gem5 executing on zizzer
-command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2332316587000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
deleted file mode 100644
index e3050fa31..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ /dev/null
@@ -1,441 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.332317 # Number of seconds simulated
-sim_ticks 2332316587000 # Number of ticks simulated
-final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2072038 # Simulator instruction rate (inst/s)
-host_tick_rate 63144661085 # Simulator tick rate (ticks/s)
-host_mem_usage 379208 # Number of bytes of host memory used
-host_seconds 36.94 # Real time elapsed on the host
-sim_insts 76532931 # Number of instructions simulated
-system.nvmem.bytes_read 20 # Number of bytes read from this memory
-system.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory
-system.nvmem.bytes_written 0 # Number of bytes written to this memory
-system.nvmem.num_reads 5 # Number of read requests responded to by this memory
-system.nvmem.num_writes 0 # Number of write requests responded to by this memory
-system.nvmem.num_other 0 # Number of other requests responded to by this memory
-system.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s)
-system.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s)
-system.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read 122663536 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 941280 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 9577800 # Number of bytes written to this memory
-system.physmem.num_reads 14137126 # Number of read requests responded to by this memory
-system.physmem.num_writes 856485 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 52593004 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 403582 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 116822 # number of replacements
-system.l2c.tagsinuse 24240.388378 # Cycle average of tags in use
-system.l2c.total_refs 1520830 # Total number of references to valid blocks.
-system.l2c.sampled_refs 146847 # Sample count of references to valid blocks.
-system.l2c.avg_refs 10.356562 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 10591.091336 # Average occupied blocks per context
-system.l2c.occ_blocks::1 13649.297042 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.161607 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.208272 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1188216 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 10669 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits
-system.l2c.Writeback_hits::0 604613 # number of Writeback hits
-system.l2c.Writeback_hits::total 604613 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 105791 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 105791 # number of ReadExReq hits
-system.l2c.demand_hits::0 1294007 # number of demand (read+write) hits
-system.l2c.demand_hits::1 10669 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1304676 # number of demand (read+write) hits
-system.l2c.overall_hits::0 1294007 # number of overall hits
-system.l2c.overall_hits::1 10669 # number of overall hits
-system.l2c.overall_hits::total 1304676 # number of overall hits
-system.l2c.ReadReq_misses::0 31716 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 27 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 2911 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0 141169 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 141169 # number of ReadExReq misses
-system.l2c.demand_misses::0 172885 # number of demand (read+write) misses
-system.l2c.demand_misses::1 27 # number of demand (read+write) misses
-system.l2c.demand_misses::total 172912 # number of demand (read+write) misses
-system.l2c.overall_misses::0 172885 # number of overall misses
-system.l2c.overall_misses::1 27 # number of overall misses
-system.l2c.overall_misses::total 172912 # number of overall misses
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 1219932 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 10696 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1230628 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 604613 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 2937 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 246960 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 1466892 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 10696 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 1466892 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 10696 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.025998 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.002524 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.028522 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.991147 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.571627 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.117858 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.002524 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.120382 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.117858 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.002524 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.120382 # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 102531 # number of writebacks
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 14940566 # DTB read hits
-system.cpu.dtb.read_misses 7288 # DTB read misses
-system.cpu.dtb.write_hits 11198205 # DTB write hits
-system.cpu.dtb.write_misses 2199 # DTB write misses
-system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 14947854 # DTB read accesses
-system.cpu.dtb.write_accesses 11200404 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 26138771 # DTB hits
-system.cpu.dtb.misses 9487 # DTB misses
-system.cpu.dtb.accesses 26148258 # DTB accesses
-system.cpu.itb.inst_hits 60273889 # ITB inst hits
-system.cpu.itb.inst_misses 4471 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 60278360 # ITB inst accesses
-system.cpu.itb.hits 60273889 # DTB hits
-system.cpu.itb.misses 4471 # DTB misses
-system.cpu.itb.accesses 60278360 # DTB accesses
-system.cpu.numCycles 4664556206 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 76532931 # Number of instructions executed
-system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
-system.cpu.num_func_calls 1971944 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7572657 # number of instructions that are conditional controls
-system.cpu.num_int_insts 68161177 # number of integer instructions
-system.cpu.num_fp_insts 10269 # number of float instructions
-system.cpu.num_int_register_reads 345365607 # number of times the integer registers were read
-system.cpu.num_int_register_writes 72877692 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
-system.cpu.num_mem_refs 27310784 # number of memory refs
-system.cpu.num_load_insts 15607074 # Number of load instructions
-system.cpu.num_store_insts 11703710 # Number of store instructions
-system.cpu.num_idle_cycles 4586920150.977920 # Number of idle cycles
-system.cpu.num_busy_cycles 77636055.022080 # Number of busy cycles
-system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.983356 # Percentage of idle cycles
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed
-system.cpu.icache.replacements 847054 # number of replacements
-system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use
-system.cpu.icache.total_refs 59429083 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 70.117351 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 5705452000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 511.678552 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.999372 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0 59429083 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 59429083 # number of ReadReq hits
-system.cpu.icache.demand_hits::0 59429083 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 59429083 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0 59429083 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 59429083 # number of overall hits
-system.cpu.icache.ReadReq_misses::0 847566 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses
-system.cpu.icache.demand_misses::0 847566 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0 847566 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 847566 # number of overall misses
-system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0 60276649 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 60276649 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0 60276649 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 60276649 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0 60276649 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 60276649 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0 0.014061 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0 0.014061 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0 0.014061 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 44721 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 622134 # number of replacements
-system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use
-system.cpu.dcache.total_refs 23580069 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 37.870747 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 511.997030 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999994 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0 13150366 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0 9943631 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::0 235999 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0 247136 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0 23093997 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0 23093997 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 23093997 # number of overall hits
-system.cpu.dcache.ReadReq_misses::0 364548 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0 249897 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0 11138 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::0 614445 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0 614445 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 614445 # number of overall misses
-system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0 13514914 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0 10193528 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0 247137 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0 247136 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0 23708442 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0 23708442 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.026974 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.024515 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.045068 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.025917 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.025917 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 559892 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 0 # number of replacements
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.avg_refs no_value # Average number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 0 # number of demand (read+write) misses
-system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 0 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
deleted file mode 100644
index 586cb6b73..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
+++ /dev/null
@@ -1 +0,0 @@
-build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
deleted file mode 100644
index eabb40181..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
deleted file mode 100644
index 82d6c82a5..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ /dev/null
@@ -1,840 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_cpu_frequency=500
-boot_loader=/dist/m5/system/binaries/boot.arm
-boot_loader_mem=system.nvmem
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-flags_addr=268435504
-gic_cpu_addr=520093952
-init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-load_addr_mask=268435455
-machine_type=RealView_PBX
-mem_mode=timing
-memories=system.physmem system.nvmem
-midr_regval=890224640
-num_work_ids=16
-physmem=system.physmem
-readfile=tests/halt.sh
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[7]
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=268435456:520093695 1073741824:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-arm-ael.img
-read_only=true
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-system=system
-tracer=system.cpu0.tracer
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
-sys=system
-port=system.toL2Bus.port[4]
-
-[system.cpu0.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
-sys=system
-port=system.toL2Bus.port[3]
-
-[system.cpu0.tracer]
-type=ExeTracer
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
-checker=Null
-clock=500
-cpu_id=1
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-system=system
-tracer=system.cpu1.tracer
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[6]
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
-sys=system
-port=system.toL2Bus.port[8]
-
-[system.cpu1.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[5]
-
-[system.cpu1.interrupts]
-type=ArmInterrupts
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
-sys=system
-port=system.toL2Bus.port[7]
-
-[system.cpu1.tracer]
-type=ExeTracer
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:268435455
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=false
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[28]
-mem_side=system.membus.port[8]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[9]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.realview
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.nvmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=2147483648:2214592511
-zero=true
-port=system.membus.port[1]
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=true
-port=system.membus.port[2]
-
-[system.realview]
-type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
-intrctrl=system.intrctrl
-pci_cfg_base=0
-system=system
-
-[system.realview.a9scu]
-type=A9SCU
-pio_addr=520093696
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.membus.port[5]
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268451840
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[24]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=402653184
-BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
-BAR1LegacyIO=true
-BAR1Size=1
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=2
-disks=system.cf0
-io_shift=1
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=2
-pci_dev=7
-pci_func=0
-pio_latency=1000
-platform=system.realview
-system=system
-config=system.iobus.port[10]
-dma=system.iobus.port[11]
-pio=system.iobus.port[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clock=41667
-gic=system.realview.gic
-int_num=55
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pio_addr=268566528
-pio_latency=10000
-platform=system.realview
-system=system
-vnc=system.vncserver
-dma=system.iobus.port[6]
-pio=system.iobus.port[5]
-
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268632064
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[12]
-
-[system.realview.flash_fake]
-type=IsaFake
-fake_mem=true
-pio_addr=1073741824
-pio_latency=1000
-pio_size=536870912
-platform=system.realview
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[27]
-
-[system.realview.gic]
-type=Gic
-cpu_addr=520093952
-cpu_pio_delay=10000
-dist_addr=520097792
-dist_pio_delay=10000
-int_latency=10000
-it_lines=128
-platform=system.realview
-system=system
-pio=system.membus.port[3]
-
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[19]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[20]
-
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[21]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-gic=system.realview.gic
-int_delay=1000000
-int_num=52
-is_mouse=false
-pio_addr=268460032
-pio_latency=1000
-platform=system.realview
-system=system
-vnc=system.vncserver
-pio=system.iobus.port[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-gic=system.realview.gic
-int_delay=1000000
-int_num=53
-is_mouse=true
-pio_addr=268464128
-pio_latency=1000
-platform=system.realview
-system=system
-vnc=system.vncserver
-pio=system.iobus.port[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-fake_mem=false
-pio_addr=520101888
-pio_latency=1000
-pio_size=4095
-platform=system.realview
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.port[4]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clock=1000
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-pio_addr=520095232
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.membus.port[6]
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268455936
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[25]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-idreg=0
-pio_addr=268435456
-pio_latency=1000
-platform=system.realview
-proc_id0=201326592
-proc_id1=201327138
-system=system
-pio=system.iobus.port[2]
-
-[system.realview.rtc_fake]
-type=AmbaFake
-amba_id=266289
-ignore_access=false
-pio_addr=268529664
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[26]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[23]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[16]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=true
-pio_addr=268439552
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[17]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268488704
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[22]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clock0=1000000
-clock1=1000000
-gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clock0=1000000
-clock1=1000000
-gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[4]
-
-[system.realview.uart]
-type=Pl011
-end_on_eot=false
-gic=system.realview.gic
-int_delay=100000
-int_num=44
-pio_addr=268472320
-pio_latency=1000
-platform=system.realview
-system=system
-terminal=system.terminal
-pio=system.iobus.port[1]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268476416
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268480512
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268484608
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[15]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268500992
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[18]
-
-[system.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.vncserver]
-type=VncServer
-frame_capture=false
-number=0
-port=5900
-
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
deleted file mode 100755
index 04178bb32..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
+++ /dev/null
@@ -1,18 +0,0 @@
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
deleted file mode 100755
index 2f40c0e53..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ /dev/null
@@ -1,12 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:21:22
-gem5 started Jan 23 2012 04:25:02
-gem5 executing on zizzer
-command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2669611225000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
deleted file mode 100644
index 6f6f084e3..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ /dev/null
@@ -1,888 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.669611 # Number of seconds simulated
-sim_ticks 2669611225000 # Number of ticks simulated
-final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 842154 # Simulator instruction rate (inst/s)
-host_tick_rate 28671225175 # Simulator tick rate (ticks/s)
-host_mem_usage 380676 # Number of bytes of host memory used
-host_seconds 93.11 # Real time elapsed on the host
-sim_insts 78413959 # Number of instructions simulated
-system.nvmem.bytes_read 68 # Number of bytes read from this memory
-system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
-system.nvmem.bytes_written 0 # Number of bytes written to this memory
-system.nvmem.num_reads 17 # Number of read requests responded to by this memory
-system.nvmem.num_writes 0 # Number of write requests responded to by this memory
-system.nvmem.num_other 0 # Number of other requests responded to by this memory
-system.nvmem.bw_read 25 # Total read bandwidth from this memory (bytes/s)
-system.nvmem.bw_inst_read 25 # Instruction read bandwidth from this memory (bytes/s)
-system.nvmem.bw_total 25 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read 134334820 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 1003520 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10194256 # Number of bytes written to this memory
-system.physmem.num_reads 15523876 # Number of read requests responded to by this memory
-system.physmem.num_writes 869239 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 50319994 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 375905 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 3818629 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 54138623 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 127749 # number of replacements
-system.l2c.tagsinuse 26172.513439 # Cycle average of tags in use
-system.l2c.total_refs 1540412 # Total number of references to valid blocks.
-system.l2c.sampled_refs 157158 # Sample count of references to valid blocks.
-system.l2c.avg_refs 9.801677 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 6351.465954 # Average occupied blocks per context
-system.l2c.occ_blocks::1 4614.904109 # Average occupied blocks per context
-system.l2c.occ_blocks::2 15206.143377 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.096916 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.070418 # Average percentage of cache occupancy
-system.l2c.occ_percent::2 0.232027 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 562859 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 656143 # number of ReadReq hits
-system.l2c.ReadReq_hits::2 11798 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1230800 # number of ReadReq hits
-system.l2c.Writeback_hits::0 589400 # number of Writeback hits
-system.l2c.Writeback_hits::total 589400 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 1143 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1 692 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1835 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0 168 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1 186 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 354 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0 42506 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1 58554 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 101060 # number of ReadExReq hits
-system.l2c.demand_hits::0 605365 # number of demand (read+write) hits
-system.l2c.demand_hits::1 714697 # number of demand (read+write) hits
-system.l2c.demand_hits::2 11798 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1331860 # number of demand (read+write) hits
-system.l2c.overall_hits::0 605365 # number of overall hits
-system.l2c.overall_hits::1 714697 # number of overall hits
-system.l2c.overall_hits::2 11798 # number of overall hits
-system.l2c.overall_hits::total 1331860 # number of overall hits
-system.l2c.ReadReq_misses::0 18655 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 16034 # number of ReadReq misses
-system.l2c.ReadReq_misses::2 50 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 34739 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 3515 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 5223 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 8738 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0 546 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1 614 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1160 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0 97324 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1 51524 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 148848 # number of ReadExReq misses
-system.l2c.demand_misses::0 115979 # number of demand (read+write) misses
-system.l2c.demand_misses::1 67558 # number of demand (read+write) misses
-system.l2c.demand_misses::2 50 # number of demand (read+write) misses
-system.l2c.demand_misses::total 183587 # number of demand (read+write) misses
-system.l2c.overall_misses::0 115979 # number of overall misses
-system.l2c.overall_misses::1 67558 # number of overall misses
-system.l2c.overall_misses::2 50 # number of overall misses
-system.l2c.overall_misses::total 183587 # number of overall misses
-system.l2c.ReadReq_miss_latency 1812504500 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency 56471000 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency 6300000 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency 7751543000 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency 9564047500 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 9564047500 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 581514 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 672177 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2 11848 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1265539 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 589400 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 4658 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 5915 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 10573 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0 714 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1 800 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1514 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 139830 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1 110078 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 721344 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 782255 # number of demand (read+write) accesses
-system.l2c.demand_accesses::2 11848 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1515447 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 721344 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 782255 # number of overall (read+write) accesses
-system.l2c.overall_accesses::2 11848 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1515447 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.032080 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.023854 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2 0.004220 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.060154 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.754616 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 0.883009 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0 0.764706 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1 0.767500 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.696017 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 0.468068 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.160782 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.086363 # miss rate for demand accesses
-system.l2c.demand_miss_rate::2 0.004220 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.251365 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.160782 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.086363 # miss rate for overall accesses
-system.l2c.overall_miss_rate::2 0.004220 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.251365 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0 97159.179845 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 113041.318448 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2 36250090 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 36460290.498293 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 16065.718350 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 10811.985449 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::0 11538.461538 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1 10260.586319 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 79646.777773 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 150445.287633 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0 82463.614103 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 141567.949022 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 191280950 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 191504981.563124 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 82463.614103 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 141567.949022 # average overall miss latency
-system.l2c.overall_avg_miss_latency::2 191280950 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 191504981.563124 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 111955 # number of writebacks
-system.l2c.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits 9 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 9 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses 34730 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses 8738 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses 1160 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses 148848 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses 183578 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 183578 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency 1395310000 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency 350593500 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency 46546000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency 5965367000 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency 7360677000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 7360677000 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 131926671000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency 31372379500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 163299050500 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.059723 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 0.051668 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2 2.931296 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 3.042688 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0 1.875912 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 1.477261 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.624650 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.450000 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0 1.064493 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 1.352205 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0 0.254494 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0.234678 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 15.494429 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 15.983602 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0.254494 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0.234678 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 15.494429 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 15.983602 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40175.928592 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40122.854200 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40125.862069 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40076.903956 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7857580 # DTB read hits
-system.cpu0.dtb.read_misses 1898 # DTB read misses
-system.cpu0.dtb.write_hits 6224259 # DTB write hits
-system.cpu0.dtb.write_misses 1143 # DTB write misses
-system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1404 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 79 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 191 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7859478 # DTB read accesses
-system.cpu0.dtb.write_accesses 6225402 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14081839 # DTB hits
-system.cpu0.dtb.misses 3041 # DTB misses
-system.cpu0.dtb.accesses 14084880 # DTB accesses
-system.cpu0.itb.inst_hits 35747911 # ITB inst hits
-system.cpu0.itb.inst_misses 1204 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1262 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 35749115 # ITB inst accesses
-system.cpu0.itb.hits 35747911 # DTB hits
-system.cpu0.itb.misses 1204 # DTB misses
-system.cpu0.itb.accesses 35749115 # DTB accesses
-system.cpu0.numCycles 5337805216 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.num_insts 43969024 # Number of instructions executed
-system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses
-system.cpu0.num_func_calls 977479 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4512711 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 39881498 # number of integer instructions
-system.cpu0.num_fp_insts 4107 # number of float instructions
-system.cpu0.num_int_register_reads 225043856 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 43158045 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3851 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written
-system.cpu0.num_mem_refs 14677999 # number of memory refs
-system.cpu0.num_load_insts 8148547 # Number of load instructions
-system.cpu0.num_store_insts 6529452 # Number of store instructions
-system.cpu0.num_idle_cycles 5107410781.564784 # Number of idle cycles
-system.cpu0.num_busy_cycles 230394434.435216 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.043163 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.956837 # Percentage of idle cycles
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 38525 # number of quiesce instructions executed
-system.cpu0.icache.replacements 380069 # number of replacements
-system.cpu0.icache.tagsinuse 510.849663 # Cycle average of tags in use
-system.cpu0.icache.total_refs 35367311 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 380581 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 92.929786 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 510.849663 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.997753 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::0 35367311 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 35367311 # number of ReadReq hits
-system.cpu0.icache.demand_hits::0 35367311 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 35367311 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::0 35367311 # number of overall hits
-system.cpu0.icache.overall_hits::1 0 # number of overall hits
-system.cpu0.icache.overall_hits::total 35367311 # number of overall hits
-system.cpu0.icache.ReadReq_misses::0 380583 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 380583 # number of ReadReq misses
-system.cpu0.icache.demand_misses::0 380583 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 380583 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::0 380583 # number of overall misses
-system.cpu0.icache.overall_misses::1 0 # number of overall misses
-system.cpu0.icache.overall_misses::total 380583 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency 5651439000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency 5651439000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency 5651439000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::0 35747894 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::0 35747894 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 35747894 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::0 35747894 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 35747894 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::0 0.010646 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::0 0.010646 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::0 0.010646 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::0 14849.425749 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::0 14849.425749 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::0 14849.425749 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks 12960 # number of writebacks
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses 380583 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses 380583 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses 380583 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 4509188500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency 4509188500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency 4509188500 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency 351814000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency 351814000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.010646 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::0 0.010646 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::0 0.010646 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11848.108034 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 334596 # number of replacements
-system.cpu0.dcache.tagsinuse 450.118381 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 12875674 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0 450.118381 # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0 0.879137 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::0 7428609 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7428609 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::0 5172633 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 5172633 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::0 126778 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 126778 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::0 127996 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 127996 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::0 12601242 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 12601242 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::0 12601242 # number of overall hits
-system.cpu0.dcache.overall_hits::1 0 # number of overall hits
-system.cpu0.dcache.overall_hits::total 12601242 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::0 217330 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 217330 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::0 155538 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 155538 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::0 9456 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 9456 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::0 8189 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 8189 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::0 372868 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 372868 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::0 372868 # number of overall misses
-system.cpu0.dcache.overall_misses::1 0 # number of overall misses
-system.cpu0.dcache.overall_misses::total 372868 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency 3330686000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency 6317758500 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency 100249000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency 70240000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency 9648444500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency 9648444500 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::0 7645939 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 7645939 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::0 5328171 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 5328171 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::0 136234 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 136234 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::0 136185 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 136185 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::0 12974110 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 12974110 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::0 12974110 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 12974110 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::0 0.028424 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::0 0.029192 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.069410 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::0 0.060131 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::0 0.028739 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0 0.028739 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 15325.477385 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 40618.745901 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 10601.628596 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 8577.359873 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::0 25876.300728 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0 25876.300728 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks 294891 # number of writebacks
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses 217330 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses 155538 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 9456 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses 8184 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses 372868 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses 372868 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 2678673500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency 5851029000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 71881000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency 45691000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency 8529702500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency 8529702500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 9171180500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 40129379500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency 49300560000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028424 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.029192 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.069410 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.060095 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::0 0.028739 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0 0.028739 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12325.373855 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37618.003318 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 7601.628596 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 5582.966764 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 7762496 # DTB read hits
-system.cpu1.dtb.read_misses 5432 # DTB read misses
-system.cpu1.dtb.write_hits 5411648 # DTB write hits
-system.cpu1.dtb.write_misses 1096 # DTB write misses
-system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2346 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 166 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 261 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 7767928 # DTB read accesses
-system.cpu1.dtb.write_accesses 5412744 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 13174144 # DTB hits
-system.cpu1.dtb.misses 6528 # DTB misses
-system.cpu1.dtb.accesses 13180672 # DTB accesses
-system.cpu1.itb.inst_hits 26848280 # ITB inst hits
-system.cpu1.itb.inst_misses 3154 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1544 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 26851434 # ITB inst accesses
-system.cpu1.itb.hits 26848280 # DTB hits
-system.cpu1.itb.misses 3154 # DTB misses
-system.cpu1.itb.accesses 26851434 # DTB accesses
-system.cpu1.numCycles 5339222450 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.num_insts 34444935 # Number of instructions executed
-system.cpu1.num_int_alu_accesses 31033253 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses
-system.cpu1.num_func_calls 1093852 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3362553 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 31033253 # number of integer instructions
-system.cpu1.num_fp_insts 5714 # number of float instructions
-system.cpu1.num_int_register_reads 181157193 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 32585304 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3770 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written
-system.cpu1.num_mem_refs 13796843 # number of memory refs
-system.cpu1.num_load_insts 8139019 # Number of load instructions
-system.cpu1.num_store_insts 5657824 # Number of store instructions
-system.cpu1.num_idle_cycles 4950307250.068146 # Number of idle cycles
-system.cpu1.num_busy_cycles 388915199.931854 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.072841 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.927159 # Percentage of idle cycles
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 53838 # number of quiesce instructions executed
-system.cpu1.icache.replacements 508221 # number of replacements
-system.cpu1.icache.tagsinuse 497.375159 # Cycle average of tags in use
-system.cpu1.icache.total_refs 26339543 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 51.774788 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0 497.375159 # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0 0.971436 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0 26339543 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 26339543 # number of ReadReq hits
-system.cpu1.icache.demand_hits::0 26339543 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 26339543 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::0 26339543 # number of overall hits
-system.cpu1.icache.overall_hits::1 0 # number of overall hits
-system.cpu1.icache.overall_hits::total 26339543 # number of overall hits
-system.cpu1.icache.ReadReq_misses::0 508733 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses
-system.cpu1.icache.demand_misses::0 508733 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0 508733 # number of overall misses
-system.cpu1.icache.overall_misses::1 0 # number of overall misses
-system.cpu1.icache.overall_misses::total 508733 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency 7436442000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency 7436442000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency 7436442000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0 26848276 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 26848276 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::0 26848276 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 26848276 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::0 26848276 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 26848276 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0 0.018948 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0 0.018948 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::0 0.018948 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.573462 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::0 14617.573462 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0 14617.573462 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks 27998 # number of writebacks
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses 508733 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses 508733 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses 508733 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency 5908060000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency 5908060000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency 5908060000 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency 5250000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency 5250000 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.018948 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::0 0.018948 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0 0.018948 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11613.282409 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 295754 # number of replacements
-system.cpu1.dcache.tagsinuse 467.166427 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 11737107 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 39.616787 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0 467.166427 # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0 0.912434 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0 6345290 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 6345290 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0 5152610 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 5152610 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0 104795 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::0 106403 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0 11497900 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 11497900 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0 11497900 # number of overall hits
-system.cpu1.dcache.overall_hits::1 0 # number of overall hits
-system.cpu1.dcache.overall_hits::total 11497900 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0 188245 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0 137493 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 137493 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0 11557 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 11557 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0 9906 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 9906 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0 325738 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0 325738 # number of overall misses
-system.cpu1.dcache.overall_misses::1 0 # number of overall misses
-system.cpu1.dcache.overall_misses::total 325738 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency 2729023500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency 4123985000 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency 131721000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency 82493000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency 6853008500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency 6853008500 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0 6533535 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 6533535 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::0 5290103 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 5290103 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0 116352 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0 116309 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0 11823638 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 11823638 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0 11823638 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 11823638 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0 0.028812 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0 0.025991 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.099328 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.085170 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0 0.027550 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0 0.027550 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 14497.189832 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 29994.145156 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11397.508004 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8327.579245 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::0 21038.406634 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 21038.406634 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 253551 # number of writebacks
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses 188245 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses 137493 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses 11557 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses 9900 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses 325738 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses 325738 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 2164153000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency 3711466500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97050000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency 52793000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency 5875619500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency 5875619500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 137931975000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 470526000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency 138402501000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.028812 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.025991 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.099328 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.085118 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::0 0.027550 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0 0.027550 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11496.470026 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26993.857869 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8397.508004 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5332.626263 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 0 # number of replacements
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.avg_refs no_value # Average number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 0 # number of demand (read+write) misses
-system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 0 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_uncacheable_latency 1342252853622 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency 1342252853622 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
deleted file mode 100644
index 9e24c3e8a..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
+++ /dev/null
@@ -1 +0,0 @@
-build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
deleted file mode 100644
index 7e7f32a27..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
deleted file mode 100644
index b4466ea53..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ /dev/null
@@ -1,716 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_cpu_frequency=500
-boot_loader=/dist/m5/system/binaries/boot.arm
-boot_loader_mem=system.nvmem
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-flags_addr=268435504
-gic_cpu_addr=520093952
-init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-load_addr_mask=268435455
-machine_type=RealView_PBX
-mem_mode=timing
-memories=system.nvmem system.physmem
-midr_regval=890224640
-num_work_ids=16
-physmem=system.physmem
-readfile=tests/halt.sh
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[7]
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=268435456:520093695 1073741824:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-arm-ael.img
-read_only=true
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-system=system
-tracer=system.cpu.tracer
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
-sys=system
-port=system.toL2Bus.port[4]
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
-sys=system
-port=system.toL2Bus.port[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:268435455
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=false
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[28]
-mem_side=system.membus.port[8]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[9]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.realview
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.nvmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=2147483648:2214592511
-zero=true
-port=system.membus.port[1]
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=true
-port=system.membus.port[2]
-
-[system.realview]
-type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
-intrctrl=system.intrctrl
-pci_cfg_base=0
-system=system
-
-[system.realview.a9scu]
-type=A9SCU
-pio_addr=520093696
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.membus.port[5]
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268451840
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[24]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=402653184
-BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
-BAR1LegacyIO=true
-BAR1Size=1
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=2
-disks=system.cf0
-io_shift=1
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=2
-pci_dev=7
-pci_func=0
-pio_latency=1000
-platform=system.realview
-system=system
-config=system.iobus.port[10]
-dma=system.iobus.port[11]
-pio=system.iobus.port[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clock=41667
-gic=system.realview.gic
-int_num=55
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pio_addr=268566528
-pio_latency=10000
-platform=system.realview
-system=system
-vnc=system.vncserver
-dma=system.iobus.port[6]
-pio=system.iobus.port[5]
-
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268632064
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[12]
-
-[system.realview.flash_fake]
-type=IsaFake
-fake_mem=true
-pio_addr=1073741824
-pio_latency=1000
-pio_size=536870912
-platform=system.realview
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[27]
-
-[system.realview.gic]
-type=Gic
-cpu_addr=520093952
-cpu_pio_delay=10000
-dist_addr=520097792
-dist_pio_delay=10000
-int_latency=10000
-it_lines=128
-platform=system.realview
-system=system
-pio=system.membus.port[3]
-
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[19]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[20]
-
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[21]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-gic=system.realview.gic
-int_delay=1000000
-int_num=52
-is_mouse=false
-pio_addr=268460032
-pio_latency=1000
-platform=system.realview
-system=system
-vnc=system.vncserver
-pio=system.iobus.port[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-gic=system.realview.gic
-int_delay=1000000
-int_num=53
-is_mouse=true
-pio_addr=268464128
-pio_latency=1000
-platform=system.realview
-system=system
-vnc=system.vncserver
-pio=system.iobus.port[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-fake_mem=false
-pio_addr=520101888
-pio_latency=1000
-pio_size=4095
-platform=system.realview
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.port[4]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clock=1000
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-pio_addr=520095232
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.membus.port[6]
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268455936
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[25]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-idreg=0
-pio_addr=268435456
-pio_latency=1000
-platform=system.realview
-proc_id0=201326592
-proc_id1=201327138
-system=system
-pio=system.iobus.port[2]
-
-[system.realview.rtc_fake]
-type=AmbaFake
-amba_id=266289
-ignore_access=false
-pio_addr=268529664
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[26]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[23]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[16]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=true
-pio_addr=268439552
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[17]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268488704
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[22]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clock0=1000000
-clock1=1000000
-gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clock0=1000000
-clock1=1000000
-gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[4]
-
-[system.realview.uart]
-type=Pl011
-end_on_eot=false
-gic=system.realview.gic
-int_delay=100000
-int_num=44
-pio_addr=268472320
-pio_latency=1000
-platform=system.realview
-system=system
-terminal=system.terminal
-pio=system.iobus.port[1]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268476416
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268480512
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268484608
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[15]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
-pio_addr=268500992
-pio_latency=1000
-platform=system.realview
-system=system
-pio=system.iobus.port[18]
-
-[system.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.vncserver]
-type=VncServer
-frame_capture=false
-number=0
-port=5900
-
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
deleted file mode 100755
index 9a28ceb37..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
+++ /dev/null
@@ -1,17 +0,0 @@
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
deleted file mode 100755
index 661533caf..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ /dev/null
@@ -1,12 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:21:22
-gem5 started Jan 23 2012 04:25:02
-gem5 executing on zizzer
-command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2591441692000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
deleted file mode 100644
index 543720998..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ /dev/null
@@ -1,523 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.591442 # Number of seconds simulated
-sim_ticks 2591441692000 # Number of ticks simulated
-final_tick 2591441692000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 852555 # Simulator instruction rate (inst/s)
-host_tick_rate 29271571690 # Simulator tick rate (ticks/s)
-host_mem_usage 379496 # Number of bytes of host memory used
-host_seconds 88.53 # Real time elapsed on the host
-sim_insts 75477515 # Number of instructions simulated
-system.nvmem.bytes_read 20 # Number of bytes read from this memory
-system.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory
-system.nvmem.bytes_written 0 # Number of bytes written to this memory
-system.nvmem.num_reads 5 # Number of read requests responded to by this memory
-system.nvmem.num_writes 0 # Number of write requests responded to by this memory
-system.nvmem.num_other 0 # Number of other requests responded to by this memory
-system.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s)
-system.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s)
-system.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read 133655408 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 949920 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 9634312 # Number of bytes written to this memory
-system.physmem.num_reads 15513098 # Number of read requests responded to by this memory
-system.physmem.num_writes 857428 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 51575696 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 366560 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 3717742 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 55293438 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 117809 # number of replacements
-system.l2c.tagsinuse 24928.376904 # Cycle average of tags in use
-system.l2c.total_refs 1535240 # Total number of references to valid blocks.
-system.l2c.sampled_refs 146709 # Sample count of references to valid blocks.
-system.l2c.avg_refs 10.464525 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 10331.534348 # Average occupied blocks per context
-system.l2c.occ_blocks::1 14596.842556 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.157647 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.222730 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1198360 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 12495 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1210855 # number of ReadReq hits
-system.l2c.Writeback_hits::0 610049 # number of Writeback hits
-system.l2c.Writeback_hits::total 610049 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 106473 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 106473 # number of ReadExReq hits
-system.l2c.demand_hits::0 1304833 # number of demand (read+write) hits
-system.l2c.demand_hits::1 12495 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1317328 # number of demand (read+write) hits
-system.l2c.overall_hits::0 1304833 # number of overall hits
-system.l2c.overall_hits::1 12495 # number of overall hits
-system.l2c.overall_hits::total 1317328 # number of overall hits
-system.l2c.ReadReq_misses::0 31685 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 37 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 31722 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 2875 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0 140928 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 140928 # number of ReadExReq misses
-system.l2c.demand_misses::0 172613 # number of demand (read+write) misses
-system.l2c.demand_misses::1 37 # number of demand (read+write) misses
-system.l2c.demand_misses::total 172650 # number of demand (read+write) misses
-system.l2c.overall_misses::0 172613 # number of overall misses
-system.l2c.overall_misses::1 37 # number of overall misses
-system.l2c.overall_misses::total 172650 # number of overall misses
-system.l2c.ReadReq_miss_latency 1654516000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency 1040000 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency 7338006500 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency 8992522500 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 8992522500 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 1230045 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 12532 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1242577 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 610049 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 610049 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 2901 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 247401 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 247401 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 1477446 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 12532 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1489978 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 1477446 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 12532 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1489978 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.025759 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.002952 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.028712 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.991038 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.569634 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.116832 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.002952 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.119784 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.116832 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.002952 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.119784 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0 52217.642418 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 44716648.648649 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 44768866.291066 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 361.739130 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52069.187812 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0 52096.438275 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 243041148.648649 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 243093245.086924 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 52096.438275 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 243041148.648649 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 243093245.086924 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 103410 # number of writebacks
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses 31722 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses 2875 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses 140928 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses 172650 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 172650 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency 1273844000 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency 115156000 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency 5646870000 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency 6920714000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 6920714000 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 131817513000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency 31206766500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 163024279500 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.025789 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 2.531280 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 2.557069 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.991038 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0 0.569634 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0 0.116857 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 13.776732 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 13.893589 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0.116857 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 13.776732 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 13.893589 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40156.484459 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40054.260870 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40069.184264 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 14970647 # DTB read hits
-system.cpu.dtb.read_misses 7343 # DTB read misses
-system.cpu.dtb.write_hits 11215605 # DTB write hits
-system.cpu.dtb.write_misses 2208 # DTB write misses
-system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 183 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 14977990 # DTB read accesses
-system.cpu.dtb.write_accesses 11217813 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 26186252 # DTB hits
-system.cpu.dtb.misses 9551 # DTB misses
-system.cpu.dtb.accesses 26195803 # DTB accesses
-system.cpu.itb.inst_hits 60357722 # ITB inst hits
-system.cpu.itb.inst_misses 4471 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 60362193 # ITB inst accesses
-system.cpu.itb.hits 60357722 # DTB hits
-system.cpu.itb.misses 4471 # DTB misses
-system.cpu.itb.accesses 60362193 # DTB accesses
-system.cpu.numCycles 5182883384 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 75477515 # Number of instructions executed
-system.cpu.num_int_alu_accesses 68255270 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
-system.cpu.num_func_calls 1975579 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7580611 # number of instructions that are conditional controls
-system.cpu.num_int_insts 68255270 # number of integer instructions
-system.cpu.num_fp_insts 10269 # number of float instructions
-system.cpu.num_int_register_reads 390835391 # number of times the integer registers were read
-system.cpu.num_int_register_writes 72984158 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
-system.cpu.num_mem_refs 27351734 # number of memory refs
-system.cpu.num_load_insts 15632521 # Number of load instructions
-system.cpu.num_store_insts 11719213 # Number of store instructions
-system.cpu.num_idle_cycles 4574345772.482235 # Number of idle cycles
-system.cpu.num_busy_cycles 608537611.517765 # Number of busy cycles
-system.cpu.not_idle_fraction 0.117413 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.882587 # Percentage of idle cycles
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 82953 # number of quiesce instructions executed
-system.cpu.icache.replacements 852971 # number of replacements
-system.cpu.icache.tagsinuse 510.943281 # Cycle average of tags in use
-system.cpu.icache.total_refs 59504239 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 853483 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 69.719302 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 18512998000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 510.943281 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.997936 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0 59504239 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 59504239 # number of ReadReq hits
-system.cpu.icache.demand_hits::0 59504239 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 59504239 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0 59504239 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 59504239 # number of overall hits
-system.cpu.icache.ReadReq_misses::0 853483 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 853483 # number of ReadReq misses
-system.cpu.icache.demand_misses::0 853483 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 853483 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0 853483 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 853483 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 12547128000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 12547128000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 12547128000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0 60357722 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 60357722 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0 60357722 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 60357722 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0 60357722 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 60357722 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0 0.014140 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0 0.014140 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0 0.014140 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14701.087192 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14701.087192 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14701.087192 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 45661 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 853483 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 853483 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 853483 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 9984295500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 9984295500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 9984295500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency 350913000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 350913000 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.014140 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0 0.014140 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0 0.014140 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11698.294518 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 626903 # number of replacements
-system.cpu.dcache.tagsinuse 511.875592 # Cycle average of tags in use
-system.cpu.dcache.total_refs 23615096 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 627415 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 37.638718 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 511.875592 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999757 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0 13170367 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13170367 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0 9958094 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 9958094 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::0 236142 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 236142 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0 247592 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 247592 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0 23128461 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 23128461 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0 23128461 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 23128461 # number of overall hits
-system.cpu.dcache.ReadReq_misses::0 368563 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 368563 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0 250302 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 250302 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0 11451 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 11451 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::0 618865 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 618865 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0 618865 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 618865 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 5846897000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 9551170500 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency 186076500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency 15398067500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 15398067500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0 13538930 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13538930 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0 10208396 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10208396 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0 247593 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0 247592 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0 23747326 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 23747326 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0 23747326 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 23747326 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.027222 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.024519 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.046249 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.026060 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.026060 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15864.036813 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 38158.586428 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16249.803511 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 24881.141283 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 24881.141283 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 564388 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 368563 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 250302 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses 11451 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 618865 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 618865 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4741074500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 8800219500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 151723500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 13541294000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 13541294000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 146946835000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 40367455500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 187314290500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.027222 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024519 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.046249 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0 0.026060 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0.026060 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12863.674596 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35158.406645 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13249.803511 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 0 # number of replacements
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.avg_refs no_value # Average number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 0 # number of demand (read+write) misses
-system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 0 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_uncacheable_latency 1341941439938 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency 1341941439938 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
deleted file mode 100644
index 8953751c2..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
+++ /dev/null
@@ -1 +0,0 @@
-build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
deleted file mode 100644
index 33e436852..000000000
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
deleted file mode 100644
index 91a089b4b..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ /dev/null
@@ -1,1210 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_cpu_frequency=500
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-e820_table=system.e820_table
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-load_addr_mask=18446744073709551615
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-readfile=tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[3]
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[1]
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.dtb_walker_cache.cpu_side
-
-[system.cpu.dtb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dtb.walker.port
-mem_side=system.toL2Bus.port[4]
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu.interrupts]
-type=X86LocalApic
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.itb_walker_cache.cpu_side
-
-[system.cpu.itb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.itb.walker.port
-mem_side=system.toL2Bus.port[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1
-entries=system.e820_table.entries0 system.e820_table.entries1
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-range_type=2
-size=1048576
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=1048576
-range_type=1
-size=133169152
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-id=1
-version=17
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPBus
-bus_id=0
-bus_type=ISA
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=1
-bus_type=PCI
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=16
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=2
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=1
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=3
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=4
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=5
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=6
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=7
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=8
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=9
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=10
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=11
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=12
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=13
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=14
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=0
-parent_bus=1
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=true
-width=64
-default=system.pc.pciconfig.pio
-port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:134217727
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=true
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[21]
-mem_side=system.membus.port[4]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[5]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854779128
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[15]
-
-[system.pc.com_1]
-type=Uart8250
-children=terminal
-pio_addr=9223372036854776824
-pio_latency=1000
-platform=system.pc
-system=system
-terminal=system.pc.com_1.terminal
-pio=system.iobus.port[16]
-
-[system.pc.com_1.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.com_1.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.fake_com_2]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776568
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[17]
-
-[system.pc.fake_com_3]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776808
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[18]
-
-[system.pc.fake_com_4]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776552
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[19]
-
-[system.pc.fake_floppy]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776818
-pio_latency=1000
-pio_size=2
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[20]
-
-[system.pc.i_dont_exist]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854775936
-pio_latency=1000
-pio_size=1
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[14]
-
-[system.pc.pciconfig]
-type=PciConfigAll
-bus=0
-pio_latency=1
-platform=system.pc
-size=16777216
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pio_latency=1000
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-children=int_pin
-int_pin=system.pc.south_bridge.cmos.int_pin
-pio_addr=9223372036854775920
-pio_latency=1000
-platform=system.pc
-system=system
-time=Sun Jan 1 00:00:00 2012
-pio=system.iobus.port[2]
-
-[system.pc.south_bridge.cmos.int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.dma1]
-type=I8237
-pio_addr=9223372036854775808
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[3]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=1000
-platform=system.pc
-system=system
-config=system.iobus.port[5]
-dma=system.iobus.port[6]
-pio=system.iobus.port[4]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.pic1.output
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=0
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.pic2.output
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=2
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.cmos.int_pin
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-number=0
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=0
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.keyboard.keyboard_int_pin
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=1
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.keyboard.mouse_int_pin
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=12
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=1
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.iobus.port[13]
-pio=system.iobus.port[12]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-children=keyboard_int_pin mouse_int_pin
-command_port=9223372036854775908
-data_port=9223372036854775904
-keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
-mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
-pio_addr=0
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[7]
-
-[system.pc.south_bridge.keyboard.keyboard_int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.keyboard.mouse_int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pic1]
-type=I8259
-children=output
-mode=I8259Master
-output=system.pc.south_bridge.pic1.output
-pio_addr=9223372036854775840
-pio_latency=1000
-platform=system.pc
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.port[8]
-
-[system.pc.south_bridge.pic1.output]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pic2]
-type=I8259
-children=output
-mode=I8259Slave
-output=system.pc.south_bridge.pic2.output
-pio_addr=9223372036854775968
-pio_latency=1000
-platform=system.pc
-slave=Null
-system=system
-pio=system.iobus.port[9]
-
-[system.pc.south_bridge.pic2.output]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pit]
-type=I8254
-children=int_pin
-int_pin=system.pc.south_bridge.pit.int_pin
-pio_addr=9223372036854775872
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[10]
-
-[system.pc.south_bridge.pit.int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[11]
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
-
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
deleted file mode 100755
index fd09f1faf..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
+++ /dev/null
@@ -1,9 +0,0 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Reading current count from inactive timer.
-warn: Sockets disabled, not accepting gdb connections
-warn: Don't know what interrupt to clear for console.
-warn: instruction 'fxsave' unimplemented
-warn: Tried to clear PCI interrupt 14
-warn: Unknown mouse command 0xe1.
-warn: instruction 'wbinvd' unimplemented
-hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
deleted file mode 100755
index 23cf47db2..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ /dev/null
@@ -1,13 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:12:17
-gem5 started Jan 23 2012 04:24:46
-gem5 executing on zizzer
-command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-atomic
-warning: add_child('terminal'): child 'terminal' already has parent
-Global frequency set at 1000000000000 ticks per second
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5112043255000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
deleted file mode 100644
index 324bf8929..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ /dev/null
@@ -1,553 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 5.112043 # Number of seconds simulated
-sim_ticks 5112043255000 # Number of ticks simulated
-final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2850135 # Simulator instruction rate (inst/s)
-host_tick_rate 35611898535 # Simulator tick rate (ticks/s)
-host_mem_usage 353172 # Number of bytes of host memory used
-host_seconds 143.55 # Real time elapsed on the host
-sim_insts 409133277 # Number of instructions simulated
-system.physmem.bytes_read 15568704 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 12232896 # Number of bytes written to this memory
-system.physmem.num_reads 243261 # Number of read requests responded to by this memory
-system.physmem.num_writes 191139 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 3045495 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 190283 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 2392956 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 5438452 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 164044 # number of replacements
-system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use
-system.l2c.total_refs 3332458 # Total number of references to valid blocks.
-system.l2c.sampled_refs 196390 # Sample count of references to valid blocks.
-system.l2c.avg_refs 16.968573 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 9701.563280 # Average occupied blocks per context
-system.l2c.occ_blocks::1 27141.380805 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.148034 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.414145 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 2042917 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 9538 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits
-system.l2c.Writeback_hits::0 1529403 # number of Writeback hits
-system.l2c.Writeback_hits::total 1529403 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 31 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 168948 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits
-system.l2c.demand_hits::0 2211865 # number of demand (read+write) hits
-system.l2c.demand_hits::1 9538 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits
-system.l2c.overall_hits::0 2211865 # number of overall hits
-system.l2c.overall_hits::1 9538 # number of overall hits
-system.l2c.overall_hits::total 2221403 # number of overall hits
-system.l2c.ReadReq_misses::0 55972 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 27 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 1792 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0 144639 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses
-system.l2c.demand_misses::0 200611 # number of demand (read+write) misses
-system.l2c.demand_misses::1 27 # number of demand (read+write) misses
-system.l2c.demand_misses::total 200638 # number of demand (read+write) misses
-system.l2c.overall_misses::0 200611 # number of overall misses
-system.l2c.overall_misses::1 27 # number of overall misses
-system.l2c.overall_misses::total 200638 # number of overall misses
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 2098889 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 9565 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 1529403 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 1823 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 313587 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 2412476 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 9565 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 2412476 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 9565 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.026667 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.002823 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.982995 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.461240 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.083156 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.002823 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.085978 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.083156 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.002823 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.085978 # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 144472 # number of writebacks
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 47570 # number of replacements
-system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1 0.042409 # Average occupied blocks per context
-system.iocache.occ_percent::1 0.002651 # Average percentage of cache occupancy
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.ReadReq_misses::1 905 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
-system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 47625 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 47625 # number of overall misses
-system.iocache.overall_misses::total 47625 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 46667 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 10224086531 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 409133277 # Number of instructions executed
-system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls
-system.cpu.num_int_insts 374297244 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 801267455 # number of times the integer registers were read
-system.cpu.num_int_register_writes 401624559 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 35626519 # number of memory refs
-system.cpu.num_load_insts 27217784 # Number of load instructions
-system.cpu.num_store_insts 8408735 # Number of store instructions
-system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles
-system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles
-system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.icache.replacements 790795 # number of replacements
-system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
-system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 510.627676 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.997320 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0 243365777 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits
-system.cpu.icache.demand_hits::0 243365777 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0 243365777 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 243365777 # number of overall hits
-system.cpu.icache.ReadReq_misses::0 791314 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses
-system.cpu.icache.demand_misses::0 791314 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0 791314 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 791314 # number of overall misses
-system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0 244157091 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0 244157091 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0 244157091 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0 0.003241 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0 0.003241 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
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-system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses
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-system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses
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-system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses
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-system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
deleted file mode 100644
index ab8215fe1..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
+++ /dev/null
@@ -1,133 +0,0 @@
-Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
-Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-BIOS-provided physical RAM map:
- BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
- BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
-end_pfn_map = 32768
-kernel direct mapping tables up to 8000000 @ 100000-102000
-DMI 2.5 present.
-Zone PFN ranges:
- DMA 256 -> 4096
- DMA32 4096 -> 1048576
- Normal 1048576 -> 1048576
-early_node_map[1] active PFN ranges
- 0: 256 -> 32768
-Intel MultiProcessor Specification v1.4
-MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
-Processor #0 (Bootup-CPU)
-I/O APIC #1 at 0xFEC00000.
-Setting APIC routing to flat
-Processors: 1
-Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
-Built 1 zonelists. Total pages: 30458
-Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-Initializing CPU#0
-PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 1999.998 MHz processor.
-Console: colour dummy device 80x25
-console handover: boot [earlyser0] -> real [ttyS0]
-Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
-Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
-Checking aperture...
-Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)
-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
-Mount-cache hash table entries: 256
-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
-CPU: L2 Cache: 1024K (64 bytes/line)
-CPU: Fake M5 x86_64 CPU stepping 01
-ACPI: Core revision 20070126
-ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
-ACPI: Unable to load the System Description Tables
-Using local APIC timer interrupts.
-result 7812490
-Detected 7.812 MHz APIC timer.
-NET: Registered protocol family 16
-PCI: Using configuration type 1
-ACPI: Interpreter disabled.
-Linux Plug and Play Support v0.97 (c) Adam Belay
-pnp: PnP ACPI: disabled
-SCSI subsystem initialized
-usbcore: registered new interface driver usbfs
-usbcore: registered new interface driver hub
-usbcore: registered new device driver usb
-PCI: Probing PCI hardware
-PCI-GART: No AMD northbridge found.
-NET: Registered protocol family 2
-Time: tsc clocksource has been installed.
-IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
-TCP established hash table entries: 4096 (order: 4, 65536 bytes)
-TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
-TCP: Hash tables configured (established 4096 bind 4096)
-TCP reno registered
-Total HugeTLB memory allocated, 0
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
-io scheduler noop registered
-io scheduler deadline registered
-io scheduler cfq registered (default)
-Real Time Clock Driver v1.12ac
-Linux agpgart interface v0.102 (c) Dave Jones
-Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
-serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
-floppy0: no floppy controllers found
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
-loop: module loaded
-Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
-Copyright (c) 1999-2006 Intel Corporation.
-e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
-e100: Copyright(c) 1999-2006 Intel Corporation
-forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
-tun: Universal TUN/TAP device driver, 1.6
-tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
-netconsole: not configured, aborting
-Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
-ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
-PIIX4: IDE controller at PCI slot 0000:00:04.0
-PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
-PIIX4: chipset revision 0
-PIIX4: not 100% native mode: will probe irqs later
- ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
- ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
-hda: M5 IDE Disk, ATA DISK drive
-hdb: M5 IDE Disk, ATA DISK drive
-ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
-hda: max request size: 128KiB
-hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
- hda: hda1
-hdb: max request size: 128KiB
-hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
- hdb: unknown partition table
-megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
-megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
-megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
-Fusion MPT base driver 3.04.04
-Copyright (c) 1999-2007 LSI Logic Corporation
-Fusion MPT SPI Host driver 3.04.04
-Fusion MPT SAS Host driver 3.04.04
-ieee1394: raw1394: /dev/raw1394 device initialized
-USB Universal Host Controller Interface driver v3.0
-usbcore: registered new interface driver usblp
-drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
-Initializing USB Mass Storage driver...
-usbcore: registered new interface driver usb-storage
-USB Mass Storage support registered.
-PNP: No PS/2 controller found. Probing ports directly.
-serio: i8042 KBD port at 0x60,0x64 irq 1
-serio: i8042 AUX port at 0x60,0x64 irq 12
-mice: PS/2 mouse device common for all mice
-input: AT Translated Set 2 keyboard as /class/input/input0
-device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
-input: PS/2 Generic Mouse as /class/input/input1
-usbcore: registered new interface driver usbhid
-drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
-oprofile: using timer interrupt.
-TCP cubic registered
-NET: Registered protocol family 1
-NET: Registered protocol family 10
-IPv6 over IPv4 tunneling driver
-NET: Registered protocol family 17
-EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
-VFS: Mounted root (ext2 filesystem).
-Freeing unused kernel memory: 232k freed
- INIT: version 2.86 booting
-mounting filesystems...
-loading script...
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
deleted file mode 100644
index e3a339662..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ /dev/null
@@ -1,1207 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_cpu_frequency=500
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-e820_table=system.e820_table
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-load_addr_mask=18446744073709551615
-mem_mode=timing
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-readfile=tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[3]
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[1]
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-system=system
-tracer=system.cpu.tracer
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.dtb_walker_cache.cpu_side
-
-[system.cpu.dtb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dtb.walker.port
-mem_side=system.toL2Bus.port[4]
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu.interrupts]
-type=X86LocalApic
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.itb_walker_cache.cpu_side
-
-[system.cpu.itb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.itb.walker.port
-mem_side=system.toL2Bus.port[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1
-entries=system.e820_table.entries0 system.e820_table.entries1
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-range_type=2
-size=1048576
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=1048576
-range_type=1
-size=133169152
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-id=1
-version=17
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPBus
-bus_id=0
-bus_type=ISA
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=1
-bus_type=PCI
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=16
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=2
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=1
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=3
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=4
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=5
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=6
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=7
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=8
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=9
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=10
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=11
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=12
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=13
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=14
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=0
-parent_bus=1
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=true
-width=64
-default=system.pc.pciconfig.pio
-port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:134217727
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=false
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[21]
-mem_side=system.membus.port[4]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[5]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854779128
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[15]
-
-[system.pc.com_1]
-type=Uart8250
-children=terminal
-pio_addr=9223372036854776824
-pio_latency=1000
-platform=system.pc
-system=system
-terminal=system.pc.com_1.terminal
-pio=system.iobus.port[16]
-
-[system.pc.com_1.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.com_1.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.fake_com_2]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776568
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[17]
-
-[system.pc.fake_com_3]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776808
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[18]
-
-[system.pc.fake_com_4]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776552
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[19]
-
-[system.pc.fake_floppy]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776818
-pio_latency=1000
-pio_size=2
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[20]
-
-[system.pc.i_dont_exist]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854775936
-pio_latency=1000
-pio_size=1
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[14]
-
-[system.pc.pciconfig]
-type=PciConfigAll
-bus=0
-pio_latency=1
-platform=system.pc
-size=16777216
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pio_latency=1000
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-children=int_pin
-int_pin=system.pc.south_bridge.cmos.int_pin
-pio_addr=9223372036854775920
-pio_latency=1000
-platform=system.pc
-system=system
-time=Sun Jan 1 00:00:00 2012
-pio=system.iobus.port[2]
-
-[system.pc.south_bridge.cmos.int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.dma1]
-type=I8237
-pio_addr=9223372036854775808
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[3]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=1000
-platform=system.pc
-system=system
-config=system.iobus.port[5]
-dma=system.iobus.port[6]
-pio=system.iobus.port[4]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.pic1.output
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=0
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.pic2.output
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=2
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.cmos.int_pin
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-number=0
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=0
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.keyboard.keyboard_int_pin
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=1
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.keyboard.mouse_int_pin
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=12
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=1
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.iobus.port[13]
-pio=system.iobus.port[12]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-children=keyboard_int_pin mouse_int_pin
-command_port=9223372036854775908
-data_port=9223372036854775904
-keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
-mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
-pio_addr=0
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[7]
-
-[system.pc.south_bridge.keyboard.keyboard_int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.keyboard.mouse_int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pic1]
-type=I8259
-children=output
-mode=I8259Master
-output=system.pc.south_bridge.pic1.output
-pio_addr=9223372036854775840
-pio_latency=1000
-platform=system.pc
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.port[8]
-
-[system.pc.south_bridge.pic1.output]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pic2]
-type=I8259
-children=output
-mode=I8259Slave
-output=system.pc.south_bridge.pic2.output
-pio_addr=9223372036854775968
-pio_latency=1000
-platform=system.pc
-slave=Null
-system=system
-pio=system.iobus.port[9]
-
-[system.pc.south_bridge.pic2.output]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pit]
-type=I8254
-children=int_pin
-int_pin=system.pc.south_bridge.pit.int_pin
-pio_addr=9223372036854775872
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[10]
-
-[system.pc.south_bridge.pit.int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[11]
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
-
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
deleted file mode 100755
index fd09f1faf..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
+++ /dev/null
@@ -1,9 +0,0 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Reading current count from inactive timer.
-warn: Sockets disabled, not accepting gdb connections
-warn: Don't know what interrupt to clear for console.
-warn: instruction 'fxsave' unimplemented
-warn: Tried to clear PCI interrupt 14
-warn: Unknown mouse command 0xe1.
-warn: instruction 'wbinvd' unimplemented
-hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
deleted file mode 100755
index 5dde537a2..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ /dev/null
@@ -1,13 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:12:17
-gem5 started Jan 23 2012 04:24:49
-gem5 executing on zizzer
-command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-timing
-warning: add_child('terminal'): child 'terminal' already has parent
-Global frequency set at 1000000000000 ticks per second
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5195470393000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
deleted file mode 100644
index c4a248e5e..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ /dev/null
@@ -1,661 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 5.195470 # Number of seconds simulated
-sim_ticks 5195470393000 # Number of ticks simulated
-final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1681123 # Simulator instruction rate (inst/s)
-host_tick_rate 32940960656 # Simulator tick rate (ticks/s)
-host_mem_usage 349824 # Number of bytes of host memory used
-host_seconds 157.72 # Real time elapsed on the host
-sim_insts 265147881 # Number of instructions simulated
-system.physmem.bytes_read 13764096 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 974400 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10427072 # Number of bytes written to this memory
-system.physmem.num_reads 215064 # Number of read requests responded to by this memory
-system.physmem.num_writes 162923 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 2649249 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 187548 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 2006954 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 4656204 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 136133 # number of replacements
-system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use
-system.l2c.total_refs 3363370 # Total number of references to valid blocks.
-system.l2c.sampled_refs 168244 # Sample count of references to valid blocks.
-system.l2c.avg_refs 19.991025 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 7910.895776 # Average occupied blocks per context
-system.l2c.occ_blocks::1 23478.999694 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.120711 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.358261 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 2047882 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 9561 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits
-system.l2c.Writeback_hits::0 1534567 # number of Writeback hits
-system.l2c.Writeback_hits::total 1534567 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 320 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 192958 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits
-system.l2c.demand_hits::0 2240840 # number of demand (read+write) hits
-system.l2c.demand_hits::1 9561 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits
-system.l2c.overall_hits::0 2240840 # number of overall hits
-system.l2c.overall_hits::1 9561 # number of overall hits
-system.l2c.overall_hits::total 2250401 # number of overall hits
-system.l2c.ReadReq_misses::0 50807 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 23 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 1369 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0 120168 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses
-system.l2c.demand_misses::0 170975 # number of demand (read+write) misses
-system.l2c.demand_misses::1 23 # number of demand (read+write) misses
-system.l2c.demand_misses::total 170998 # number of demand (read+write) misses
-system.l2c.overall_misses::0 170975 # number of overall misses
-system.l2c.overall_misses::1 23 # number of overall misses
-system.l2c.overall_misses::total 170998 # number of overall misses
-system.l2c.ReadReq_miss_latency 2656122500 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency 33778000 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency 6249324500 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency 8905447000 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 8905447000 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 2098689 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 9584 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 1534567 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 1689 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 313126 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 313126 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 2411815 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 9584 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 2411815 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 9584 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.024209 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.002400 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.026609 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.810539 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.383769 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.070891 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.002400 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.073290 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.070891 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.002400 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.073290 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0 52278.672230 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 115483586.956522 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 115535865.628752 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 24673.484295 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52004.897310 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0 52086.252376 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 387193347.826087 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 387245434.078463 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 52086.252376 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 387193347.826087 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 387245434.078463 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 116255 # number of writebacks
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses 50830 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses 1369 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses 120168 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses 170998 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 170998 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency 2046144000 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency 55109000 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency 4807305000 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency 6853449000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 6853449000 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 56051785000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency 1218050000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 57269835000 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.024220 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 5.303631 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 5.327851 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.810539 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0 0.383769 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0 0.070900 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 17.842028 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 17.912929 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0.070900 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 17.842028 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 17.912929 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40254.652764 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40254.930606 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40004.868185 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 47510 # number of replacements
-system.iocache.tagsinuse 0.120586 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47526 # Sample count of references to valid blocks.
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1 0.120586 # Average occupied blocks per context
-system.iocache.occ_percent::1 0.007537 # Average percentage of cache occupancy
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.ReadReq_misses::1 844 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 844 # number of ReadReq misses
-system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 47564 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47564 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 47564 # number of overall misses
-system.iocache.overall_misses::total 47564 # number of overall misses
-system.iocache.ReadReq_miss_latency 106575932 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency 6391379160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency 6497955092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 6497955092 # number of overall miss cycles
-system.iocache.ReadReq_accesses::1 844 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 47564 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 47564 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 126274.800948 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 136801.779966 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 136614.983853 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 136614.983853 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 46668 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses 844 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses 47564 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 47564 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency 62666978 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency 3961676998 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency 4024343976 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 4024343976 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 74249.973934 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 84796.168622 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 84609.031536 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 84609.031536 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 10390940786 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 265147881 # Number of instructions executed
-system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls
-system.cpu.num_int_insts 249556386 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 543487907 # number of times the integer registers were read
-system.cpu.num_int_register_writes 266037487 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 23169904 # number of memory refs
-system.cpu.num_load_insts 14812525 # Number of load instructions
-system.cpu.num_store_insts 8357379 # Number of store instructions
-system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles
-system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles
-system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.941953 # Percentage of idle cycles
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.icache.replacements 788139 # number of replacements
-system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use
-system.cpu.icache.total_refs 158433932 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 510.361283 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.996799 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0 158433932 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 158433932 # number of ReadReq hits
-system.cpu.icache.demand_hits::0 158433932 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 158433932 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0 158433932 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 158433932 # number of overall hits
-system.cpu.icache.ReadReq_misses::0 788658 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses
-system.cpu.icache.demand_misses::0 788658 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 788658 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0 788658 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 788658 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 11681762500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 11681762500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 11681762500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0 159222590 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0 159222590 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0 159222590 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0 0.004953 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0 0.004953 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0 0.004953 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14812.203135 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14812.203135 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14812.203135 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
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-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 805 # number of writebacks
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-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 788658 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 788658 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 788658 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 9314744000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 9314744000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 9314744000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.004953 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0 0.004953 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0 0.004953 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11810.878733 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11810.878733 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11810.878733 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements 3754 # number of replacements
-system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs 7549 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::1 3.070606 # Average occupied blocks per context
-system.cpu.itb_walker_cache.occ_percent::1 0.191913 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::1 7619 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total 7619 # number of ReadReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
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-system.cpu.itb_walker_cache.demand_hits::1 7621 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total 7621 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::1 7621 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::1 4602 # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses
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-system.cpu.itb_walker_cache.demand_misses::1 4602 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total 4602 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::1 4602 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency 50817000 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency 50817000 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency 50817000 # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::1 12221 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
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-system.cpu.itb_walker_cache.demand_accesses::1 12223 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses
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-system.cpu.itb_walker_cache.overall_accesses::1 12223 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.376565 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::1 0.376503 # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::1 0.376503 # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 11042.372881 # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::1 11042.372881 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::1 11042.372881 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency
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-system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
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-system.cpu.itb_walker_cache.writebacks 826 # number of writebacks
-system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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-system.cpu.itb_walker_cache.ReadReq_mshr_misses 4602 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses 4602 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses 4602 # number of overall MSHR misses
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-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 37011000 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency 37011000 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency 37011000 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.376565 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.376503 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.376503 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 8042.372881 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements 7704 # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs 13051 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::1 5.052403 # Average occupied blocks per context
-system.cpu.dtb_walker_cache.occ_percent::1 0.315775 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::1 13051 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits
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-system.cpu.dtb_walker_cache.demand_hits::1 13051 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1 13051 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::1 8896 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses
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-system.cpu.dtb_walker_cache.demand_misses::1 8896 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1 8896 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency 103895500 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency 103895500 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency 103895500 # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::1 21947 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses)
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-system.cpu.dtb_walker_cache.demand_accesses::1 21947 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses
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-system.cpu.dtb_walker_cache.overall_accesses::1 21947 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.405340 # miss rate for ReadReq accesses
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-system.cpu.dtb_walker_cache.demand_miss_rate::1 0.405340 # miss rate for demand accesses
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-system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1 0.405340 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 11678.900629 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 11678.900629 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 11678.900629 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency
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-system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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-system.cpu.dtb_walker_cache.writebacks 2985 # number of writebacks
-system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses 8896 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses 8896 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses 8896 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 77207000 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency 77207000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency 77207000 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.405340 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.405340 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.405340 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 8678.844424 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 8678.844424 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 8678.844424 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1623424 # number of replacements
-system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use
-system.cpu.dcache.total_refs 20011404 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 511.997312 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999995 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0 11977182 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0 8032009 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits
-system.cpu.dcache.demand_hits::0 20009191 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0 20009191 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 20009191 # number of overall hits
-system.cpu.dcache.ReadReq_misses::0 1310824 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0 315344 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses
-system.cpu.dcache.demand_misses::0 1626168 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1626168 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0 1626168 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 1626168 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 19851809000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 9514837000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 29366646000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 29366646000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0 13288006 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0 8347353 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0 21635359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 21635359 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0 21635359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.098647 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.037778 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.075163 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.075163 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15144.526649 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 30172.881044 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 18058.802043 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 18058.802043 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 1529951 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 1310824 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 315344 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 1626168 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 1626168 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 15919294500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 8568794500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 24488089000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 24488089000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 75925324500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1379728500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 77305053000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098647 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.037778 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0 0.075163 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0.075163 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12144.494227 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27172.847747 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
deleted file mode 100644
index a1c03790e..000000000
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
+++ /dev/null
@@ -1,133 +0,0 @@
-Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
-Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-BIOS-provided physical RAM map:
- BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
- BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
-end_pfn_map = 32768
-kernel direct mapping tables up to 8000000 @ 100000-102000
-DMI 2.5 present.
-Zone PFN ranges:
- DMA 256 -> 4096
- DMA32 4096 -> 1048576
- Normal 1048576 -> 1048576
-early_node_map[1] active PFN ranges
- 0: 256 -> 32768
-Intel MultiProcessor Specification v1.4
-MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
-Processor #0 (Bootup-CPU)
-I/O APIC #1 at 0xFEC00000.
-Setting APIC routing to flat
-Processors: 1
-Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
-Built 1 zonelists. Total pages: 30458
-Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-Initializing CPU#0
-PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 1999.998 MHz processor.
-Console: colour dummy device 80x25
-console handover: boot [earlyser0] -> real [ttyS0]
-Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
-Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
-Checking aperture...
-Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)
-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
-Mount-cache hash table entries: 256
-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
-CPU: L2 Cache: 1024K (64 bytes/line)
-CPU: Fake M5 x86_64 CPU stepping 01
-ACPI: Core revision 20070126
-ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
-ACPI: Unable to load the System Description Tables
-Using local APIC timer interrupts.
-result 7812489
-Detected 7.812 MHz APIC timer.
-NET: Registered protocol family 16
-PCI: Using configuration type 1
-ACPI: Interpreter disabled.
-Linux Plug and Play Support v0.97 (c) Adam Belay
-pnp: PnP ACPI: disabled
-SCSI subsystem initialized
-usbcore: registered new interface driver usbfs
-usbcore: registered new interface driver hub
-usbcore: registered new device driver usb
-PCI: Probing PCI hardware
-PCI-GART: No AMD northbridge found.
-Time: tsc clocksource has been installed.
-NET: Registered protocol family 2
-IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
-TCP established hash table entries: 4096 (order: 4, 65536 bytes)
-TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
-TCP: Hash tables configured (established 4096 bind 4096)
-TCP reno registered
-Total HugeTLB memory allocated, 0
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
-io scheduler noop registered
-io scheduler deadline registered
-io scheduler cfq registered (default)
-Real Time Clock Driver v1.12ac
-Linux agpgart interface v0.102 (c) Dave Jones
-Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
-serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
-floppy0: no floppy controllers found
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
-loop: module loaded
-Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
-Copyright (c) 1999-2006 Intel Corporation.
-e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
-e100: Copyright(c) 1999-2006 Intel Corporation
-forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
-tun: Universal TUN/TAP device driver, 1.6
-tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
-netconsole: not configured, aborting
-Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
-ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
-PIIX4: IDE controller at PCI slot 0000:00:04.0
-PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
-PIIX4: chipset revision 0
-PIIX4: not 100% native mode: will probe irqs later
- ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
- ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
-hda: M5 IDE Disk, ATA DISK drive
-hdb: M5 IDE Disk, ATA DISK drive
-ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
-hda: max request size: 128KiB
-hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
- hda: hda1
-hdb: max request size: 128KiB
-hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
- hdb: unknown partition table
-megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
-megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
-megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
-Fusion MPT base driver 3.04.04
-Copyright (c) 1999-2007 LSI Logic Corporation
-Fusion MPT SPI Host driver 3.04.04
-Fusion MPT SAS Host driver 3.04.04
-ieee1394: raw1394: /dev/raw1394 device initialized
-USB Universal Host Controller Interface driver v3.0
-usbcore: registered new interface driver usblp
-drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
-Initializing USB Mass Storage driver...
-usbcore: registered new interface driver usb-storage
-USB Mass Storage support registered.
-PNP: No PS/2 controller found. Probing ports directly.
-serio: i8042 KBD port at 0x60,0x64 irq 1
-serio: i8042 AUX port at 0x60,0x64 irq 12
-mice: PS/2 mouse device common for all mice
-input: AT Translated Set 2 keyboard as /class/input/input0
-device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
-input: PS/2 Generic Mouse as /class/input/input1
-usbcore: registered new interface driver usbhid
-drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
-oprofile: using timer interrupt.
-TCP cubic registered
-NET: Registered protocol family 1
-NET: Registered protocol family 10
-IPv6 over IPv4 tunneling driver
-NET: Registered protocol family 17
-EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
-VFS: Mounted root (ext2 filesystem).
-Freeing unused kernel memory: 232k freed
- INIT: version 2.86 booting
-mounting filesystems...
-loading script...