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authorAli Saidi <Ali.Saidi@ARM.com>2011-08-19 15:08:09 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-08-19 15:08:09 -0500
commitba265abbfd70060cc61a3b4a53b4b1cfcb7a96fe (patch)
tree5cf148fb600af2da5440a442d10170666ae8bbc9 /tests/quick/10.linux-boot/ref
parentc9d5985b8221459e4737c637910dc08513b05660 (diff)
downloadgem5-ba265abbfd70060cc61a3b4a53b4b1cfcb7a96fe.tar.xz
ARM: Add some MP regressions and clean up the disk images and kernels a bit
Diffstat (limited to 'tests/quick/10.linux-boot/ref')
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini846
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr18
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout12
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt699
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status1
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminalbin0 -> 6037 bytes
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini94
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr30
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout21
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt756
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status2
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminalbin3941 -> 5878 bytes
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini840
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr18
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout12
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt868
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status1
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminalbin0 -> 6036 bytes
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini94
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr30
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout21
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt922
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status2
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminalbin3941 -> 5878 bytes
24 files changed, 4325 insertions, 962 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
new file mode 100644
index 000000000..9933a8e22
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -0,0 +1,846 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
+boot_cpu_frequency=500
+boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader_mem=system.nvmem
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+flags_addr=268435504
+gic_cpu_addr=520093952
+init_param=0
+kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+load_addr_mask=268435455
+machine_type=RealView_PBX
+mem_mode=atomic
+memories=system.nvmem system.physmem
+midr_regval=890224640
+physmem=system.physmem
+readfile=tests/halt.sh
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+
+[system.bridge]
+type=Bridge
+delay=50000
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:268435455
+nack_delay=4000
+req_size_a=16
+req_size_b=16
+resp_size_a=16
+resp_size_b=16
+write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+read_only=true
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dtb icache interrupts itb tracer
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[4]
+
+[system.cpu0.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[3]
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu1]
+type=AtomicSimpleCPU
+children=dcache dtb icache interrupts itb tracer
+checker=Null
+clock=500
+cpu_id=1
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu1.tracer
+width=1
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.dcache_port
+mem_side=system.toL2Bus.port[6]
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[8]
+
+[system.cpu1.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.toL2Bus.port[5]
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[7]
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:268435455
+assoc=8
+block_size=64
+forward_snoops=false
+hash_delay=1
+is_top_level=false
+latency=50000
+max_miss_count=0
+mshrs=20
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[25]
+mem_side=system.membus.port[7]
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=2
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[8]
+
+[system.membus]
+type=Bus
+children=badaddr_responder
+block_size=64
+bus_id=1
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+default=system.membus.badaddr_responder.pio
+port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+fake_mem=false
+pio_addr=0
+pio_latency=1000
+pio_size=8
+platform=system.realview
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.nvmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.port[1]
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=true
+port=system.membus.port[2]
+
+[system.realview]
+type=RealView
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+intrctrl=system.intrctrl
+pci_cfg_base=0
+system=system
+
+[system.realview.a9scu]
+type=A9SCU
+pio_addr=520093696
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[5]
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268451840
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[21]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=402653184
+BAR0LegacyIO=true
+BAR0Size=16
+BAR1=402653440
+BAR1LegacyIO=true
+BAR1Size=1
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+config_latency=20000
+ctrl_offset=2
+disks=system.cf0
+io_shift=1
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=2
+pci_dev=7
+pci_func=0
+pio_latency=1000
+platform=system.realview
+system=system
+config=system.iobus.port[26]
+dma=system.iobus.port[27]
+pio=system.iobus.port[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clock=41667
+gic=system.realview.gic
+int_num=55
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pio_addr=268566528
+pio_latency=10000
+platform=system.realview
+system=system
+vnc=system.vncserver
+dma=system.iobus.port[28]
+pio=system.iobus.port[5]
+
+[system.realview.dmac_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268632064
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[9]
+
+[system.realview.flash_fake]
+type=IsaFake
+fake_mem=true
+pio_addr=1073741824
+pio_latency=1000
+pio_size=536870912
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[24]
+
+[system.realview.gic]
+type=Gic
+cpu_addr=520093952
+cpu_pio_delay=10000
+dist_addr=520097792
+dist_pio_delay=10000
+int_latency=10000
+it_lines=128
+platform=system.realview
+system=system
+pio=system.membus.port[3]
+
+[system.realview.gpio0_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268513280
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[16]
+
+[system.realview.gpio1_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268517376
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[17]
+
+[system.realview.gpio2_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268521472
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[18]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=1000000
+int_num=52
+is_mouse=false
+pio_addr=268460032
+pio_latency=1000
+platform=system.realview
+system=system
+vnc=system.vncserver
+pio=system.iobus.port[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=1000000
+int_num=53
+is_mouse=true
+pio_addr=268464128
+pio_latency=1000
+platform=system.realview
+system=system
+vnc=system.vncserver
+pio=system.iobus.port[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+fake_mem=false
+pio_addr=520101888
+pio_latency=1000
+pio_size=4095
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.port[4]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[6]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268455936
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[22]
+
+[system.realview.realview_io]
+type=RealViewCtrl
+idreg=0
+pio_addr=268435456
+pio_latency=1000
+platform=system.realview
+proc_id0=201326592
+proc_id1=201327138
+system=system
+pio=system.iobus.port[2]
+
+[system.realview.rtc_fake]
+type=AmbaFake
+amba_id=266289
+ignore_access=false
+pio_addr=268529664
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[23]
+
+[system.realview.sci_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268492800
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[20]
+
+[system.realview.smc_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=269357056
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[13]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=true
+pio_addr=268439552
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[14]
+
+[system.realview.ssp_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268488704
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[19]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=36
+int_num1=36
+pio_addr=268505088
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[3]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=37
+int_num1=37
+pio_addr=268509184
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[4]
+
+[system.realview.uart]
+type=Pl011
+end_on_eot=false
+gic=system.realview.gic
+int_delay=100000
+int_num=44
+pio_addr=268472320
+pio_latency=1000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.port[1]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268476416
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[10]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268480512
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[11]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268484608
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[12]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268500992
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[15]
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+number=0
+port=5900
+
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
new file mode 100755
index 000000000..04178bb32
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
@@ -0,0 +1,18 @@
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr bpiallis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr dccimvac' unimplemented
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
+warn: instruction 'mcr bpiallis' unimplemented
+warn: LCD dual screen mode not supported
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
new file mode 100755
index 000000000..38da5afa6
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
@@ -0,0 +1,12 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Aug 18 2011 16:54:46
+gem5 started Aug 18 2011 17:16:56
+gem5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 2411694099500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
new file mode 100644
index 000000000..7f6e2a888
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -0,0 +1,699 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 2.411694 # Number of seconds simulated
+sim_ticks 2411694099500 # Number of ticks simulated
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1186264 # Simulator instruction rate (inst/s)
+host_tick_rate 35957520604 # Simulator tick rate (ticks/s)
+host_mem_usage 417168 # Number of bytes of host memory used
+host_seconds 67.07 # Real time elapsed on the host
+sim_insts 79563488 # Number of instructions simulated
+system.l2c.replacements 127720 # number of replacements
+system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use
+system.l2c.total_refs 1498989 # Total number of references to valid blocks.
+system.l2c.sampled_refs 156132 # Sample count of references to valid blocks.
+system.l2c.avg_refs 9.600780 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0 4404.089299 # Average occupied blocks per context
+system.l2c.occ_blocks::1 6217.918720 # Average occupied blocks per context
+system.l2c.occ_blocks::2 14925.912843 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.067201 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.094878 # Average percentage of cache occupancy
+system.l2c.occ_percent::2 0.227751 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0 706190 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 499815 # number of ReadReq hits
+system.l2c.ReadReq_hits::2 12920 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits
+system.l2c.Writeback_hits::0 580461 # number of Writeback hits
+system.l2c.Writeback_hits::total 580461 # number of Writeback hits
+system.l2c.UpgradeReq_hits::0 776 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1 523 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::0 147 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::1 202 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 349 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::0 64831 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1 37797 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 102628 # number of ReadExReq hits
+system.l2c.demand_hits::0 771021 # number of demand (read+write) hits
+system.l2c.demand_hits::1 537612 # number of demand (read+write) hits
+system.l2c.demand_hits::2 12920 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits
+system.l2c.overall_hits::0 771021 # number of overall hits
+system.l2c.overall_hits::1 537612 # number of overall hits
+system.l2c.overall_hits::2 12920 # number of overall hits
+system.l2c.overall_hits::total 1321553 # number of overall hits
+system.l2c.ReadReq_misses::0 19675 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 15224 # number of ReadReq misses
+system.l2c.ReadReq_misses::2 52 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 34951 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0 6349 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1 3492 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 9841 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::0 791 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1 531 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1322 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::0 99048 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1 48785 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 147833 # number of ReadExReq misses
+system.l2c.demand_misses::0 118723 # number of demand (read+write) misses
+system.l2c.demand_misses::1 64009 # number of demand (read+write) misses
+system.l2c.demand_misses::2 52 # number of demand (read+write) misses
+system.l2c.demand_misses::total 182784 # number of demand (read+write) misses
+system.l2c.overall_misses::0 118723 # number of overall misses
+system.l2c.overall_misses::1 64009 # number of overall misses
+system.l2c.overall_misses::2 52 # number of overall misses
+system.l2c.overall_misses::total 182784 # number of overall misses
+system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency 0 # number of overall miss cycles
+system.l2c.ReadReq_accesses::0 725865 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 515039 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::2 12972 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0 580461 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0 7125 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1 4015 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0 938 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1 733 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1671 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0 163879 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1 86582 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 250461 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0 889744 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 601621 # number of demand (read+write) accesses
+system.l2c.demand_accesses::2 12972 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses
+system.l2c.overall_accesses::0 889744 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 601621 # number of overall (read+write) accesses
+system.l2c.overall_accesses::2 12972 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0 0.027106 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.029559 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2 0.004009 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.060673 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0 0.891088 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1 0.869738 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::0 0.843284 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1 0.724420 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0 0.604397 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1 0.563454 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0 0.133435 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.106394 # miss rate for demand accesses
+system.l2c.demand_miss_rate::2 0.004009 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.243838 # miss rate for demand accesses
+system.l2c.overall_miss_rate::0 0.133435 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.106394 # miss rate for overall accesses
+system.l2c.overall_miss_rate::2 0.004009 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.243838 # miss rate for overall accesses
+system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks 111818 # number of writebacks
+system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
+system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
+system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 9339288 # DTB read hits
+system.cpu0.dtb.read_misses 5153 # DTB read misses
+system.cpu0.dtb.write_hits 6907876 # DTB write hits
+system.cpu0.dtb.write_misses 1048 # DTB write misses
+system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 9344441 # DTB read accesses
+system.cpu0.dtb.write_accesses 6908924 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 16247164 # DTB hits
+system.cpu0.dtb.misses 6201 # DTB misses
+system.cpu0.dtb.accesses 16253365 # DTB accesses
+system.cpu0.itb.inst_hits 34822552 # ITB inst hits
+system.cpu0.itb.inst_misses 2978 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses
+system.cpu0.itb.hits 34822552 # DTB hits
+system.cpu0.itb.misses 2978 # DTB misses
+system.cpu0.itb.accesses 34825530 # DTB accesses
+system.cpu0.numCycles 4823340800 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.num_insts 44975797 # Number of instructions executed
+system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses
+system.cpu0.num_func_calls 1311755 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4494669 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 39858123 # number of integer instructions
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+system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::0 0.013515 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.writebacks 13905 # number of writebacks
+system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.replacements 247434 # number of replacements
+system.cpu1.dcache.tagsinuse 444.903488 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 9876826 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 247805 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 39.857251 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 69253206000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::0 444.903488 # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0 0.868952 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::0 5955973 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 5955973 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::0 3777038 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 3777038 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::0 59593 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::0 60090 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::0 9733011 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 9733011 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::0 9733011 # number of overall hits
+system.cpu1.dcache.overall_hits::1 0 # number of overall hits
+system.cpu1.dcache.overall_hits::total 9733011 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::0 165799 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 165799 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::0 111467 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::0 10725 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::0 10198 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::0 277266 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 277266 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::0 277266 # number of overall misses
+system.cpu1.dcache.overall_misses::1 0 # number of overall misses
+system.cpu1.dcache.overall_misses::total 277266 # number of overall misses
+system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::0 6121772 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 6121772 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::0 3888505 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 3888505 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::0 70318 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::0 70288 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::0 10010277 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 10010277 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::0 10010277 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 10010277 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::0 0.027083 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::0 0.028666 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.152521 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::0 0.145089 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::0 0.027698 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::0 0.027698 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.writebacks 202201 # number of writebacks
+system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.replacements 0 # number of replacements
+system.iocache.tagsinuse 0 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.avg_refs no_value # Average number of references to valid blocks.
+system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.demand_hits::0 0 # number of demand (read+write) hits
+system.iocache.demand_hits::1 0 # number of demand (read+write) hits
+system.iocache.demand_hits::total 0 # number of demand (read+write) hits
+system.iocache.overall_hits::0 0 # number of overall hits
+system.iocache.overall_hits::1 0 # number of overall hits
+system.iocache.overall_hits::total 0 # number of overall hits
+system.iocache.demand_misses::0 0 # number of demand (read+write) misses
+system.iocache.demand_misses::1 0 # number of demand (read+write) misses
+system.iocache.demand_misses::total 0 # number of demand (read+write) misses
+system.iocache.overall_misses::0 0 # number of overall misses
+system.iocache.overall_misses::1 0 # number of overall misses
+system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
+system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
+system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks 0 # number of writebacks
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
new file mode 100644
index 000000000..10632c381
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
@@ -0,0 +1 @@
+build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
new file mode 100644
index 000000000..ac162c148
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
Binary files differ
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index c163a5ab4..f7597645c 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -7,19 +7,20 @@ time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
-children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
-boot_loader=
-boot_loader_mem=Null
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
-flags_addr=0
-gic_cpu_addr=0
+boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader_mem=system.nvmem
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+flags_addr=268435504
+gic_cpu_addr=520093952
init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
+kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
-midr_regval=890236928
+memories=system.nvmem system.physmem
+midr_regval=890224640
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@@ -35,7 +36,7 @@ work_item_id=-1
type=Bridge
delay=50000
filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:134217727
+filter_ranges_b=0:268435455
nack_delay=4000
req_size_a=16
req_size_b=16
@@ -45,6 +46,26 @@ write_ack=false
side_a=system.iobus.port[0]
side_b=system.membus.port[0]
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+read_only=true
+
[system.cpu]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts itb tracer
@@ -172,16 +193,6 @@ port=system.toL2Bus.port[3]
[system.cpu.tracer]
type=ExeTracer
-[system.diskmem]
-type=PhysicalMemory
-file=/chips/pd/randd/dist/disks/ael-arm.ext2
-latency=30000
-latency_var=0
-null=false
-range=134217728:268435455
-zero=false
-port=system.membus.port[1]
-
[system.intrctrl]
type=IntrControl
sys=system
@@ -198,7 +209,7 @@ port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.p
[system.iocache]
type=BaseCache
-addr_range=0:134217727
+addr_range=0:268435455
assoc=8
block_size=64
forward_snoops=false
@@ -226,7 +237,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[6]
+mem_side=system.membus.port[7]
[system.l2c]
type=BaseCache
@@ -258,7 +269,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[7]
+mem_side=system.membus.port[8]
[system.membus]
type=Bus
@@ -270,10 +281,11 @@ header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
+fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
@@ -288,6 +300,16 @@ update_data=false
warn_access=warn
pio=system.membus.default
+[system.nvmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.port[1]
+
[system.physmem]
type=PhysicalMemory
file=
@@ -300,8 +322,9 @@ port=system.membus.port[2]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
+pci_cfg_base=0
system=system
[system.realview.a9scu]
@@ -364,12 +387,12 @@ SubsystemVendorID=0
VendorID=32902
config_latency=20000
ctrl_offset=2
-disks=
+disks=system.cf0
io_shift=1
max_backoff_delay=10000000
min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
+pci_bus=2
+pci_dev=7
pci_func=0
pio_latency=1000
platform=system.realview
@@ -406,6 +429,7 @@ pio=system.iobus.port[9]
[system.realview.flash_fake]
type=IsaFake
+fake_mem=true
pio_addr=1073741824
pio_latency=1000
pio_size=536870912
@@ -492,6 +516,7 @@ pio=system.iobus.port[7]
[system.realview.l2x0_fake]
type=IsaFake
+fake_mem=false
pio_addr=520101888
pio_latency=1000
pio_size=4095
@@ -506,6 +531,18 @@ update_data=false
warn_access=
pio=system.membus.port[4]
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[6]
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
@@ -522,7 +559,8 @@ idreg=0
pio_addr=268435456
pio_latency=1000
platform=system.realview
-proc_id=201326592
+proc_id0=201326592
+proc_id1=201327138
system=system
pio=system.iobus.port[2]
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
index a758a5804..9a28ceb37 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
@@ -1,35 +1,17 @@
warn: Sockets disabled, not accepting vnc client connections
-For more information see: http://www.m5sim.org/warn/af6a84f6
warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: The clidr register always reports 0 caches.
-For more information see: http://www.m5sim.org/warn/23a3c326
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-For more information see: http://www.m5sim.org/warn/c0c486b8
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
warn: The ccsidr register isn't implemented and always reads as 0.
-For more information see: http://www.m5sim.org/warn/2c4acb9c
+warn: instruction 'mcr bpiallis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr dccmvau' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr icimvau' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
+warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-For more information see: http://www.m5sim.org/warn/7998f2ea
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index ccb811098..832aec59f 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -1,15 +1,12 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 2 2011 15:06:32
-M5 started May 2 2011 15:06:36
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic
+gem5 compiled Aug 18 2011 16:54:46
+gem5 started Aug 18 2011 17:16:56
+gem5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 26344863500 because m5_exit instruction encountered
+Exiting @ tick 2332316587000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 6eff135de..c4ace942b 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,415 +1,421 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2945797 # Simulator instruction rate (inst/s)
-host_mem_usage 382504 # Number of bytes of host memory used
-host_seconds 17.65 # Real time elapsed on the host
-host_tick_rate 1493029395 # Simulator tick rate (ticks/s)
+sim_seconds 2.332317 # Number of seconds simulated
+sim_ticks 2332316587000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 51978646 # Number of instructions simulated
-sim_seconds 0.026345 # Number of seconds simulated
-sim_ticks 26344863500 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0 100443 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 100443 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::0 95328 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 95328 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050924 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 5115 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 5115 # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::0 7808976 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 7808976 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::0 7572677 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7572677 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::0 0.030260 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 236299 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 236299 # number of ReadReq misses
-system.cpu.dcache.StoreCondReq_accesses::0 100442 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 100442 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0 100442 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 100442 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6664019 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6664019 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0 6491936 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6491936 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0 0.025823 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 172083 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 172083 # number of WriteReq misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 34.645976 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 14472995 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 14472995 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 14064613 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 14064613 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.028217 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 408382 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 408382 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 511.736581 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999486 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses::0 14472995 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 14472995 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 14064613 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 14064613 # number of overall hits
-system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.028217 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 408382 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 408382 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 411144 # number of replacements
-system.cpu.dcache.sampled_refs 411656 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.736581 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14262224 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 21760500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 380291 # number of writebacks
-system.cpu.dtb.accesses 15497629 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 2239 # Number of entries that have been flushed from TLB
+host_inst_rate 1407778 # Simulator instruction rate (inst/s)
+host_tick_rate 42901571145 # Simulator tick rate (ticks/s)
+host_mem_usage 417476 # Number of bytes of host memory used
+host_seconds 54.36 # Real time elapsed on the host
+sim_insts 76532931 # Number of instructions simulated
+system.l2c.replacements 116822 # number of replacements
+system.l2c.tagsinuse 24240.388378 # Cycle average of tags in use
+system.l2c.total_refs 1520830 # Total number of references to valid blocks.
+system.l2c.sampled_refs 146847 # Sample count of references to valid blocks.
+system.l2c.avg_refs 10.356562 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0 10591.091336 # Average occupied blocks per context
+system.l2c.occ_blocks::1 13649.297042 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.161607 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.208272 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0 1188216 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 10669 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits
+system.l2c.Writeback_hits::0 604613 # number of Writeback hits
+system.l2c.Writeback_hits::total 604613 # number of Writeback hits
+system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::0 105791 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 105791 # number of ReadExReq hits
+system.l2c.demand_hits::0 1294007 # number of demand (read+write) hits
+system.l2c.demand_hits::1 10669 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1304676 # number of demand (read+write) hits
+system.l2c.overall_hits::0 1294007 # number of overall hits
+system.l2c.overall_hits::1 10669 # number of overall hits
+system.l2c.overall_hits::total 1304676 # number of overall hits
+system.l2c.ReadReq_misses::0 31716 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 27 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0 2911 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0 141169 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 141169 # number of ReadExReq misses
+system.l2c.demand_misses::0 172885 # number of demand (read+write) misses
+system.l2c.demand_misses::1 27 # number of demand (read+write) misses
+system.l2c.demand_misses::total 172912 # number of demand (read+write) misses
+system.l2c.overall_misses::0 172885 # number of overall misses
+system.l2c.overall_misses::1 27 # number of overall misses
+system.l2c.overall_misses::total 172912 # number of overall misses
+system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency 0 # number of overall miss cycles
+system.l2c.ReadReq_accesses::0 1219932 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 10696 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1230628 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0 604613 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0 2937 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0 246960 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0 1466892 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 10696 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses
+system.l2c.overall_accesses::0 1466892 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 10696 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0 0.025998 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.002524 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.028522 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0 0.991147 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0 0.571627 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0 0.117858 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.002524 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.120382 # miss rate for demand accesses
+system.l2c.overall_miss_rate::0 0.117858 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.002524 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.120382 # miss rate for overall accesses
+system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks 102531 # number of writebacks
+system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
+system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
+system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 14940566 # DTB read hits
+system.cpu.dtb.read_misses 7288 # DTB read misses
+system.cpu.dtb.write_hits 11198205 # DTB write hits
+system.cpu.dtb.write_misses 2199 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 15491993 # DTB hits
+system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 14947854 # DTB read accesses
+system.cpu.dtb.write_accesses 11200404 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 5636 # DTB misses
-system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 787 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 8721338 # DTB read accesses
-system.cpu.dtb.read_hits 8716687 # DTB read hits
-system.cpu.dtb.read_misses 4651 # DTB read misses
-system.cpu.dtb.write_accesses 6776291 # DTB write accesses
-system.cpu.dtb.write_hits 6775306 # DTB write hits
-system.cpu.dtb.write_misses 985 # DTB write misses
-system.cpu.icache.ReadReq_accesses::0 41456992 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 41456992 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits::0 41024796 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 41024796 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate::0 0.010425 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0 432196 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 432196 # number of ReadReq misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 94.921959 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::0 41456992 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 41456992 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 41024796 # number of demand (read+write) hits
+system.cpu.dtb.hits 26138771 # DTB hits
+system.cpu.dtb.misses 9487 # DTB misses
+system.cpu.dtb.accesses 26148258 # DTB accesses
+system.cpu.itb.inst_hits 60273889 # ITB inst hits
+system.cpu.itb.inst_misses 4471 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 60278360 # ITB inst accesses
+system.cpu.itb.hits 60273889 # DTB hits
+system.cpu.itb.misses 4471 # DTB misses
+system.cpu.itb.accesses 60278360 # DTB accesses
+system.cpu.numCycles 4664556206 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 76532931 # Number of instructions executed
+system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
+system.cpu.num_func_calls 1971944 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 7572657 # number of instructions that are conditional controls
+system.cpu.num_int_insts 68161177 # number of integer instructions
+system.cpu.num_fp_insts 10269 # number of float instructions
+system.cpu.num_int_register_reads 345365607 # number of times the integer registers were read
+system.cpu.num_int_register_writes 72877692 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
+system.cpu.num_mem_refs 27310784 # number of memory refs
+system.cpu.num_load_insts 15607074 # Number of load instructions
+system.cpu.num_store_insts 11703710 # Number of store instructions
+system.cpu.num_idle_cycles 4586920150.977920 # Number of idle cycles
+system.cpu.num_busy_cycles 77636055.022080 # Number of busy cycles
+system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.983356 # Percentage of idle cycles
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed
+system.cpu.icache.replacements 847054 # number of replacements
+system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use
+system.cpu.icache.total_refs 59429083 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 70.117351 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 5705452000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 511.678552 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.999372 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::0 59429083 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 59429083 # number of ReadReq hits
+system.cpu.icache.demand_hits::0 59429083 # number of demand (read+write) hits
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 41024796 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 59429083 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::0 59429083 # number of overall hits
+system.cpu.icache.overall_hits::1 0 # number of overall hits
+system.cpu.icache.overall_hits::total 59429083 # number of overall hits
+system.cpu.icache.ReadReq_misses::0 847566 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses
+system.cpu.icache.demand_misses::0 847566 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::0 847566 # number of overall misses
+system.cpu.icache.overall_misses::1 0 # number of overall misses
+system.cpu.icache.overall_misses::total 847566 # number of overall misses
system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.010425 # miss rate for demand accesses
+system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::0 60276649 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 60276649 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::0 60276649 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 60276649 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::0 60276649 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 60276649 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::0 0.014061 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::0 0.014061 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 432196 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 432196 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 476.343594 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.930359 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses::0 41456992 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 41456992 # number of overall (read+write) accesses
+system.cpu.icache.overall_miss_rate::0 0.014061 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 41024796 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 41024796 # number of overall hits
-system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0 0.010425 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 432196 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 432196 # number of overall misses
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 44721 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 431683 # number of replacements
-system.cpu.icache.sampled_refs 432195 # Sample count of references to valid blocks.
+system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 476.343594 # Cycle average of tags in use
-system.cpu.icache.total_refs 41024796 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 4572561500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 33762 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 41458119 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 41455189 # DTB hits
-system.cpu.itb.inst_accesses 41458119 # ITB inst accesses
-system.cpu.itb.inst_hits 41455189 # ITB inst hits
-system.cpu.itb.inst_misses 2930 # ITB inst misses
-system.cpu.itb.misses 2930 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 52689728 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 52689728 # Number of busy cycles
-system.cpu.num_conditional_control_insts 7011782 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
-system.cpu.num_fp_insts 6058 # number of float instructions
-system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
-system.cpu.num_func_calls 1108496 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 51978646 # Number of instructions executed
-system.cpu.num_int_alu_accesses 42407849 # Number of integer alu accesses
-system.cpu.num_int_insts 42407849 # number of integer instructions
-system.cpu.num_int_register_reads 222699258 # number of times the integer registers were read
-system.cpu.num_int_register_writes 49674551 # number of times the integer registers were written
-system.cpu.num_load_insts 9176676 # Number of load instructions
-system.cpu.num_mem_refs 16251075 # number of memory refs
-system.cpu.num_store_insts 7074399 # Number of store instructions
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 622134 # number of replacements
+system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use
+system.cpu.dcache.total_refs 23580069 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 37.870747 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 511.997030 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.999994 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::0 13150366 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::0 9943631 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::0 235999 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::0 247136 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::0 23093997 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::0 23093997 # number of overall hits
+system.cpu.dcache.overall_hits::1 0 # number of overall hits
+system.cpu.dcache.overall_hits::total 23093997 # number of overall hits
+system.cpu.dcache.ReadReq_misses::0 364548 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::0 249897 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::0 11138 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::0 614445 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::0 614445 # number of overall misses
+system.cpu.dcache.overall_misses::1 0 # number of overall misses
+system.cpu.dcache.overall_misses::total 614445 # number of overall misses
+system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0 13514914 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0 10193528 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::0 247137 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0 247136 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0 23708442 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0 23708442 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0 0.026974 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0 0.024515 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.045068 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::0 0.025917 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::0 0.025917 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 559892 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.replacements 0 # number of replacements
+system.iocache.tagsinuse 0 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs no_value # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.iocache.overall_hits::0 0 # number of overall hits
+system.iocache.overall_hits::1 0 # number of overall hits
+system.iocache.overall_hits::total 0 # number of overall hits
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.overall_misses::0 0 # number of overall misses
+system.iocache.overall_misses::1 0 # number of overall misses
+system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks 0 # number of writebacks
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.replacements 0 # number of replacements
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 0 # number of writebacks
-system.l2c.ReadExReq_accesses::0 170242 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 170242 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits::0 60575 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 60575 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate::0 0.644183 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 109667 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 109667 # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0 671513 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 7076 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 678589 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0 650281 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 7045 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 657326 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0 0.031618 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.004381 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.035999 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 21232 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 31 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 21263 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0 1841 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1841 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_hits::0 19 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 19 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_rate::0 0.989680 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0 414053 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 414053 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 414053 # number of Writeback hits
-system.l2c.Writeback_hits::total 414053 # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 6.728889 # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 841755 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 7076 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 848831 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits::0 710856 # number of demand (read+write) hits
-system.l2c.demand_hits::1 7045 # number of demand (read+write) hits
-system.l2c.demand_hits::total 717901 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.155507 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.004381 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.159888 # miss rate for demand accesses
-system.l2c.demand_misses::0 130899 # number of demand (read+write) misses
-system.l2c.demand_misses::1 31 # number of demand (read+write) misses
-system.l2c.demand_misses::total 130930 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_blocks::0 5062.983429 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31189.392245 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.077255 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.475912 # Average percentage of cache occupancy
-system.l2c.overall_accesses::0 841755 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 7076 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 848831 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 710856 # number of overall hits
-system.l2c.overall_hits::1 7045 # number of overall hits
-system.l2c.overall_hits::total 717901 # number of overall hits
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.155507 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.004381 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.159888 # miss rate for overall accesses
-system.l2c.overall_misses::0 130899 # number of overall misses
-system.l2c.overall_misses::1 31 # number of overall misses
-system.l2c.overall_misses::total 130930 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 97110 # number of replacements
-system.l2c.sampled_refs 129685 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 36252.375674 # Cycle average of tags in use
-system.l2c.total_refs 872636 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 91105 # number of writebacks
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
index 53b01d583..586cb6b73 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
@@ -1 +1 @@
-build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
+build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
index 628fa9f5d..eabb40181 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
Binary files differ
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
new file mode 100644
index 000000000..7186b34ef
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -0,0 +1,840 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
+boot_cpu_frequency=500
+boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader_mem=system.nvmem
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+flags_addr=268435504
+gic_cpu_addr=520093952
+init_param=0
+kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+load_addr_mask=268435455
+machine_type=RealView_PBX
+mem_mode=timing
+memories=system.nvmem system.physmem
+midr_regval=890224640
+physmem=system.physmem
+readfile=tests/halt.sh
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+
+[system.bridge]
+type=Bridge
+delay=50000
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:268435455
+nack_delay=4000
+req_size_a=16
+req_size_b=16
+resp_size_a=16
+resp_size_b=16
+write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+read_only=true
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts itb tracer
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+system=system
+tracer=system.cpu0.tracer
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[4]
+
+[system.cpu0.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[3]
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts itb tracer
+checker=Null
+clock=500
+cpu_id=1
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+system=system
+tracer=system.cpu1.tracer
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.dcache_port
+mem_side=system.toL2Bus.port[6]
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[8]
+
+[system.cpu1.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
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+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.toL2Bus.port[5]
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[7]
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:268435455
+assoc=8
+block_size=64
+forward_snoops=false
+hash_delay=1
+is_top_level=false
+latency=50000
+max_miss_count=0
+mshrs=20
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[25]
+mem_side=system.membus.port[7]
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=2
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[8]
+
+[system.membus]
+type=Bus
+children=badaddr_responder
+block_size=64
+bus_id=1
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+default=system.membus.badaddr_responder.pio
+port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+fake_mem=false
+pio_addr=0
+pio_latency=1000
+pio_size=8
+platform=system.realview
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.nvmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.port[1]
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=true
+port=system.membus.port[2]
+
+[system.realview]
+type=RealView
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+intrctrl=system.intrctrl
+pci_cfg_base=0
+system=system
+
+[system.realview.a9scu]
+type=A9SCU
+pio_addr=520093696
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[5]
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268451840
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[21]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=402653184
+BAR0LegacyIO=true
+BAR0Size=16
+BAR1=402653440
+BAR1LegacyIO=true
+BAR1Size=1
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+config_latency=20000
+ctrl_offset=2
+disks=system.cf0
+io_shift=1
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=2
+pci_dev=7
+pci_func=0
+pio_latency=1000
+platform=system.realview
+system=system
+config=system.iobus.port[26]
+dma=system.iobus.port[27]
+pio=system.iobus.port[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clock=41667
+gic=system.realview.gic
+int_num=55
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pio_addr=268566528
+pio_latency=10000
+platform=system.realview
+system=system
+vnc=system.vncserver
+dma=system.iobus.port[28]
+pio=system.iobus.port[5]
+
+[system.realview.dmac_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268632064
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[9]
+
+[system.realview.flash_fake]
+type=IsaFake
+fake_mem=true
+pio_addr=1073741824
+pio_latency=1000
+pio_size=536870912
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[24]
+
+[system.realview.gic]
+type=Gic
+cpu_addr=520093952
+cpu_pio_delay=10000
+dist_addr=520097792
+dist_pio_delay=10000
+int_latency=10000
+it_lines=128
+platform=system.realview
+system=system
+pio=system.membus.port[3]
+
+[system.realview.gpio0_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268513280
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[16]
+
+[system.realview.gpio1_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268517376
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[17]
+
+[system.realview.gpio2_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268521472
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[18]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=1000000
+int_num=52
+is_mouse=false
+pio_addr=268460032
+pio_latency=1000
+platform=system.realview
+system=system
+vnc=system.vncserver
+pio=system.iobus.port[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=1000000
+int_num=53
+is_mouse=true
+pio_addr=268464128
+pio_latency=1000
+platform=system.realview
+system=system
+vnc=system.vncserver
+pio=system.iobus.port[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+fake_mem=false
+pio_addr=520101888
+pio_latency=1000
+pio_size=4095
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.port[4]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[6]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268455936
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[22]
+
+[system.realview.realview_io]
+type=RealViewCtrl
+idreg=0
+pio_addr=268435456
+pio_latency=1000
+platform=system.realview
+proc_id0=201326592
+proc_id1=201327138
+system=system
+pio=system.iobus.port[2]
+
+[system.realview.rtc_fake]
+type=AmbaFake
+amba_id=266289
+ignore_access=false
+pio_addr=268529664
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[23]
+
+[system.realview.sci_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268492800
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[20]
+
+[system.realview.smc_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=269357056
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[13]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=true
+pio_addr=268439552
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[14]
+
+[system.realview.ssp_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268488704
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[19]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=36
+int_num1=36
+pio_addr=268505088
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[3]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=37
+int_num1=37
+pio_addr=268509184
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[4]
+
+[system.realview.uart]
+type=Pl011
+end_on_eot=false
+gic=system.realview.gic
+int_delay=100000
+int_num=44
+pio_addr=268472320
+pio_latency=1000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.port[1]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268476416
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[10]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268480512
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[11]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268484608
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[12]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268500992
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[15]
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+number=0
+port=5900
+
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
new file mode 100755
index 000000000..04178bb32
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
@@ -0,0 +1,18 @@
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr bpiallis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr dccimvac' unimplemented
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
+warn: instruction 'mcr bpiallis' unimplemented
+warn: LCD dual screen mode not supported
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
new file mode 100755
index 000000000..d4218de20
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -0,0 +1,12 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Aug 18 2011 16:54:46
+gem5 started Aug 18 2011 17:16:56
+gem5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 2669611225000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
new file mode 100644
index 000000000..4e104d3a4
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -0,0 +1,868 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 2.669611 # Number of seconds simulated
+sim_ticks 2669611225000 # Number of ticks simulated
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 491804 # Simulator instruction rate (inst/s)
+host_tick_rate 16743499108 # Simulator tick rate (ticks/s)
+host_mem_usage 418920 # Number of bytes of host memory used
+host_seconds 159.44 # Real time elapsed on the host
+sim_insts 78413959 # Number of instructions simulated
+system.l2c.replacements 127749 # number of replacements
+system.l2c.tagsinuse 26172.513439 # Cycle average of tags in use
+system.l2c.total_refs 1540412 # Total number of references to valid blocks.
+system.l2c.sampled_refs 157158 # Sample count of references to valid blocks.
+system.l2c.avg_refs 9.801677 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0 6351.465954 # Average occupied blocks per context
+system.l2c.occ_blocks::1 4614.904109 # Average occupied blocks per context
+system.l2c.occ_blocks::2 15206.143377 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.096916 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.070418 # Average percentage of cache occupancy
+system.l2c.occ_percent::2 0.232027 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0 562859 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 656143 # number of ReadReq hits
+system.l2c.ReadReq_hits::2 11798 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1230800 # number of ReadReq hits
+system.l2c.Writeback_hits::0 589400 # number of Writeback hits
+system.l2c.Writeback_hits::total 589400 # number of Writeback hits
+system.l2c.UpgradeReq_hits::0 1143 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1 692 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 1835 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::0 168 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::1 186 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 354 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::0 42506 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1 58554 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 101060 # number of ReadExReq hits
+system.l2c.demand_hits::0 605365 # number of demand (read+write) hits
+system.l2c.demand_hits::1 714697 # number of demand (read+write) hits
+system.l2c.demand_hits::2 11798 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1331860 # number of demand (read+write) hits
+system.l2c.overall_hits::0 605365 # number of overall hits
+system.l2c.overall_hits::1 714697 # number of overall hits
+system.l2c.overall_hits::2 11798 # number of overall hits
+system.l2c.overall_hits::total 1331860 # number of overall hits
+system.l2c.ReadReq_misses::0 18655 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 16034 # number of ReadReq misses
+system.l2c.ReadReq_misses::2 50 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 34739 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0 3515 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1 5223 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 8738 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::0 546 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1 614 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1160 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::0 97324 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1 51524 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 148848 # number of ReadExReq misses
+system.l2c.demand_misses::0 115979 # number of demand (read+write) misses
+system.l2c.demand_misses::1 67558 # number of demand (read+write) misses
+system.l2c.demand_misses::2 50 # number of demand (read+write) misses
+system.l2c.demand_misses::total 183587 # number of demand (read+write) misses
+system.l2c.overall_misses::0 115979 # number of overall misses
+system.l2c.overall_misses::1 67558 # number of overall misses
+system.l2c.overall_misses::2 50 # number of overall misses
+system.l2c.overall_misses::total 183587 # number of overall misses
+system.l2c.ReadReq_miss_latency 1812504500 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency 56471000 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency 6300000 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency 7751543000 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency 9564047500 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency 9564047500 # number of overall miss cycles
+system.l2c.ReadReq_accesses::0 581514 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 672177 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::2 11848 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1265539 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0 589400 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0 4658 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1 5915 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 10573 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0 714 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1 800 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1514 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0 139830 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1 110078 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0 721344 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 782255 # number of demand (read+write) accesses
+system.l2c.demand_accesses::2 11848 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1515447 # number of demand (read+write) accesses
+system.l2c.overall_accesses::0 721344 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 782255 # number of overall (read+write) accesses
+system.l2c.overall_accesses::2 11848 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1515447 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0 0.032080 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.023854 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2 0.004220 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.060154 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0 0.754616 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1 0.883009 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::0 0.764706 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1 0.767500 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0 0.696017 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1 0.468068 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0 0.160782 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.086363 # miss rate for demand accesses
+system.l2c.demand_miss_rate::2 0.004220 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.251365 # miss rate for demand accesses
+system.l2c.overall_miss_rate::0 0.160782 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.086363 # miss rate for overall accesses
+system.l2c.overall_miss_rate::2 0.004220 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.251365 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0 97159.179845 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 113041.318448 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2 36250090 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 36460290.498293 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 16065.718350 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 10811.985449 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::0 11538.461538 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::1 10260.586319 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 79646.777773 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 150445.287633 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0 82463.614103 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 141567.949022 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 191280950 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 191504981.563124 # average overall miss latency
+system.l2c.overall_avg_miss_latency::0 82463.614103 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 141567.949022 # average overall miss latency
+system.l2c.overall_avg_miss_latency::2 191280950 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 191504981.563124 # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks 111955 # number of writebacks
+system.l2c.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits 9 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits 9 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses 34730 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 8738 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses 1160 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses 148848 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses 183578 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses 183578 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency 1395310000 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency 350593500 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency 46546000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency 5965367000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency 7360677000 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 7360677000 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency 131926671000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency 31372379500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency 163299050500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.059723 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 0.051668 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2 2.931296 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 3.042688 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 1.875912 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 1.477261 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.624650 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.450000 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0 1.064493 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1 1.352205 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::0 0.254494 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 0.234678 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2 15.494429 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 15.983602 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0 0.254494 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 0.234678 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2 15.494429 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 15.983602 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40175.928592 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40122.854200 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40125.862069 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40076.903956 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 7857580 # DTB read hits
+system.cpu0.dtb.read_misses 1898 # DTB read misses
+system.cpu0.dtb.write_hits 6224259 # DTB write hits
+system.cpu0.dtb.write_misses 1143 # DTB write misses
+system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 1404 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 79 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 191 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 7859478 # DTB read accesses
+system.cpu0.dtb.write_accesses 6225402 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 14081839 # DTB hits
+system.cpu0.dtb.misses 3041 # DTB misses
+system.cpu0.dtb.accesses 14084880 # DTB accesses
+system.cpu0.itb.inst_hits 35747911 # ITB inst hits
+system.cpu0.itb.inst_misses 1204 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 1262 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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+system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
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+system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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+system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12325.373855 # average ReadReq mshr miss latency
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+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency
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+system.cpu0.dcache.overall_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 7762496 # DTB read hits
+system.cpu1.dtb.read_misses 5432 # DTB read misses
+system.cpu1.dtb.write_hits 5411648 # DTB write hits
+system.cpu1.dtb.write_misses 1096 # DTB write misses
+system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 2346 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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+system.cpu1.dtb.accesses 13180672 # DTB accesses
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+system.cpu1.itb.accesses 26851434 # DTB accesses
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+system.cpu1.idle_fraction 0.927159 # Percentage of idle cycles
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+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 137931975000 # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.028812 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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+system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::0 0.027550 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::0 0.027550 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11496.470026 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26993.857869 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8397.508004 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5332.626263 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.replacements 0 # number of replacements
+system.iocache.tagsinuse 0 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.avg_refs no_value # Average number of references to valid blocks.
+system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.demand_hits::0 0 # number of demand (read+write) hits
+system.iocache.demand_hits::1 0 # number of demand (read+write) hits
+system.iocache.demand_hits::total 0 # number of demand (read+write) hits
+system.iocache.overall_hits::0 0 # number of overall hits
+system.iocache.overall_hits::1 0 # number of overall hits
+system.iocache.overall_hits::total 0 # number of overall hits
+system.iocache.demand_misses::0 0 # number of demand (read+write) misses
+system.iocache.demand_misses::1 0 # number of demand (read+write) misses
+system.iocache.demand_misses::total 0 # number of demand (read+write) misses
+system.iocache.overall_misses::0 0 # number of overall misses
+system.iocache.overall_misses::1 0 # number of overall misses
+system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
+system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
+system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks 0 # number of writebacks
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_uncacheable_latency 1342252853622 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency 1342252853622 # number of overall MSHR uncacheable cycles
+system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
new file mode 100644
index 000000000..9e24c3e8a
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
@@ -0,0 +1 @@
+build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
new file mode 100644
index 000000000..7e7f32a27
--- /dev/null
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
Binary files differ
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 8d1301d9c..8c21a92dd 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -7,19 +7,20 @@ time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
-children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
-boot_loader=
-boot_loader_mem=Null
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
-flags_addr=0
-gic_cpu_addr=0
+boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader_mem=system.nvmem
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+flags_addr=268435504
+gic_cpu_addr=520093952
init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
+kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
-midr_regval=890236928
+memories=system.nvmem system.physmem
+midr_regval=890224640
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@@ -35,7 +36,7 @@ work_item_id=-1
type=Bridge
delay=50000
filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:134217727
+filter_ranges_b=0:268435455
nack_delay=4000
req_size_a=16
req_size_b=16
@@ -45,6 +46,26 @@ write_ack=false
side_a=system.iobus.port[0]
side_b=system.membus.port[0]
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+read_only=true
+
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb tracer
@@ -169,16 +190,6 @@ port=system.toL2Bus.port[3]
[system.cpu.tracer]
type=ExeTracer
-[system.diskmem]
-type=PhysicalMemory
-file=/chips/pd/randd/dist/disks/ael-arm.ext2
-latency=30000
-latency_var=0
-null=false
-range=134217728:268435455
-zero=false
-port=system.membus.port[1]
-
[system.intrctrl]
type=IntrControl
sys=system
@@ -195,7 +206,7 @@ port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.p
[system.iocache]
type=BaseCache
-addr_range=0:134217727
+addr_range=0:268435455
assoc=8
block_size=64
forward_snoops=false
@@ -223,7 +234,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[6]
+mem_side=system.membus.port[7]
[system.l2c]
type=BaseCache
@@ -255,7 +266,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[7]
+mem_side=system.membus.port[8]
[system.membus]
type=Bus
@@ -267,10 +278,11 @@ header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
+fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
@@ -285,6 +297,16 @@ update_data=false
warn_access=warn
pio=system.membus.default
+[system.nvmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.port[1]
+
[system.physmem]
type=PhysicalMemory
file=
@@ -297,8 +319,9 @@ port=system.membus.port[2]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
+pci_cfg_base=0
system=system
[system.realview.a9scu]
@@ -361,12 +384,12 @@ SubsystemVendorID=0
VendorID=32902
config_latency=20000
ctrl_offset=2
-disks=
+disks=system.cf0
io_shift=1
max_backoff_delay=10000000
min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
+pci_bus=2
+pci_dev=7
pci_func=0
pio_latency=1000
platform=system.realview
@@ -403,6 +426,7 @@ pio=system.iobus.port[9]
[system.realview.flash_fake]
type=IsaFake
+fake_mem=true
pio_addr=1073741824
pio_latency=1000
pio_size=536870912
@@ -489,6 +513,7 @@ pio=system.iobus.port[7]
[system.realview.l2x0_fake]
type=IsaFake
+fake_mem=false
pio_addr=520101888
pio_latency=1000
pio_size=4095
@@ -503,6 +528,18 @@ update_data=false
warn_access=
pio=system.membus.port[4]
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[6]
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
@@ -519,7 +556,8 @@ idreg=0
pio_addr=268435456
pio_latency=1000
platform=system.realview
-proc_id=201326592
+proc_id0=201326592
+proc_id1=201327138
system=system
pio=system.iobus.port[2]
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
index a758a5804..9a28ceb37 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
@@ -1,35 +1,17 @@
warn: Sockets disabled, not accepting vnc client connections
-For more information see: http://www.m5sim.org/warn/af6a84f6
warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: The clidr register always reports 0 caches.
-For more information see: http://www.m5sim.org/warn/23a3c326
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-For more information see: http://www.m5sim.org/warn/c0c486b8
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
warn: The ccsidr register isn't implemented and always reads as 0.
-For more information see: http://www.m5sim.org/warn/2c4acb9c
+warn: instruction 'mcr bpiallis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr dccmvau' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr icimvau' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
+warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-For more information see: http://www.m5sim.org/warn/7998f2ea
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index e8aae375a..8eb08f81f 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -1,15 +1,12 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 2 2011 15:06:32
-M5 started May 2 2011 15:06:36
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing
+gem5 compiled Aug 18 2011 16:54:46
+gem5 started Aug 18 2011 17:16:56
+gem5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 114316622000 because m5_exit instruction encountered
+Exiting @ tick 2591441692000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 2a2d9df74..6e7850295 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,495 +1,503 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1455036 # Simulator instruction rate (inst/s)
-host_mem_usage 382532 # Number of bytes of host memory used
-host_seconds 35.16 # Real time elapsed on the host
-host_tick_rate 3251070052 # Simulator tick rate (ticks/s)
+sim_seconds 2.591442 # Number of seconds simulated
+sim_ticks 2591441692000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 51162775 # Number of instructions simulated
-sim_seconds 0.114317 # Number of seconds simulated
-sim_ticks 114316622000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0 100301 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 100301 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14594.610314 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11594.610314 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0 95143 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 95143 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 75279000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051425 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 5158 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 5158 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 59805000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051425 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 5158 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0 7815759 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 7815759 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15651.214184 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12650.891296 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 7577286 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7577286 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3732392000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.030512 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 238473 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 238473 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3016896000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030512 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 238473 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38196735000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0 100300 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 100300 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0 100300 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 100300 # number of StoreCondReq hits
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-system.cpu.dcache.WriteReq_accesses::total 6667481 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 40727.618008 # average WriteReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37727.411843 # average WriteReq mshr miss latency
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-system.cpu.dcache.WriteReq_hits::total 6495289 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 7012970000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0 0.025826 # miss rate for WriteReq accesses
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-system.cpu.dcache.WriteReq_misses::total 172192 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 6496358500 # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.dcache.demand_accesses::total 14483240 # number of demand (read+write) accesses
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-system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23165.486467 # average overall mshr miss latency
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-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 14072575 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10745362000 # number of demand (read+write) miss cycles
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-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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-system.cpu.dcache.demand_misses::total 410665 # number of demand (read+write) misses
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-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 509.189203 # Average occupied blocks per context
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-system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23165.486467 # average overall mshr miss latency
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-system.cpu.dcache.overall_hits::total 14072575 # number of overall hits
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-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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-system.cpu.dcache.sampled_refs 413984 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 509.189203 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14269857 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 382812 # number of writebacks
-system.cpu.dtb.accesses 15512082 # DTB accesses
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+host_inst_rate 610490 # Simulator instruction rate (inst/s)
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+host_mem_usage 417836 # Number of bytes of host memory used
+host_seconds 123.63 # Real time elapsed on the host
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+system.l2c.ReadReq_avg_miss_latency::1 44716648.648649 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 44768866.291066 # average ReadReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
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+system.l2c.demand_avg_miss_latency::total 243093245.086924 # average overall miss latency
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+system.l2c.overall_avg_miss_latency::1 243041148.648649 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 243093245.086924 # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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+system.l2c.ReadReq_mshr_uncacheable_latency 131817513000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency 31206766500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency 163024279500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.025789 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 2.531280 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 2.557069 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 0.991038 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
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+system.l2c.demand_mshr_miss_rate::1 13.776732 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 13.893589 # mshr miss rate for demand accesses
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+system.l2c.overall_mshr_miss_rate::1 13.776732 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 13.893589 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40156.484459 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40054.260870 # average UpgradeReq mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 15506431 # DTB hits
+system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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+system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 14977990 # DTB read accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 5651 # DTB misses
-system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 801 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 8731607 # DTB read accesses
-system.cpu.dtb.read_hits 8726923 # DTB read hits
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-system.cpu.dtb.write_accesses 6780475 # DTB write accesses
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-system.cpu.dtb.write_misses 967 # DTB write misses
-system.cpu.icache.ReadReq_accesses::0 41483736 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 41483736 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14791.732049 # average ReadReq miss latency
+system.cpu.dtb.hits 26186252 # DTB hits
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+system.cpu.dtb.accesses 26195803 # DTB accesses
+system.cpu.itb.inst_hits 60357722 # ITB inst hits
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+system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
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+system.cpu.icache.overall_hits::total 59504239 # number of overall hits
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system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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-system.cpu.icache.ReadReq_misses::total 433989 # number of ReadReq misses
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-system.cpu.icache.avg_refs 94.587068 # Average number of references to valid blocks.
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+system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.demand_accesses::total 41483736 # number of demand (read+write) accesses
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-system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
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-system.cpu.icache.demand_hits::total 41049747 # number of demand (read+write) hits
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-system.cpu.icache.demand_misses::0 433989 # number of demand (read+write) misses
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-system.cpu.icache.demand_misses::total 433989 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 5116910500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0.010462 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 853483 # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency 9984295500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 9984295500 # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_uncacheable_latency 350913000 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0 0.014140 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 433989 # number of demand (read+write) MSHR misses
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-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.icache.overall_accesses::total 41483736 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14791.732049 # average overall miss latency
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-system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11790.415195 # average overall mshr miss latency
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-system.cpu.icache.overall_hits::0 41049747 # number of overall hits
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-system.cpu.icache.overall_misses::0 433989 # number of overall misses
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system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 433989 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles
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-system.cpu.icache.replacements 433477 # number of replacements
-system.cpu.icache.sampled_refs 433989 # Sample count of references to valid blocks.
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+system.cpu.icache.overall_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 484.311851 # Cycle average of tags in use
-system.cpu.icache.total_refs 41049747 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 14247556000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 34328 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 41486666 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 41483736 # DTB hits
-system.cpu.itb.inst_accesses 41486666 # ITB inst accesses
-system.cpu.itb.inst_hits 41483736 # ITB inst hits
-system.cpu.itb.inst_misses 2930 # ITB inst misses
-system.cpu.itb.misses 2930 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
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-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 228633244 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 228633244 # Number of busy cycles
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-system.cpu.num_fp_insts 6058 # number of float instructions
-system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
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-system.cpu.num_int_alu_accesses 42435662 # Number of integer alu accesses
-system.cpu.num_int_insts 42435662 # number of integer instructions
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-system.cpu.num_load_insts 9182978 # Number of load instructions
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-system.cpu.num_store_insts 7078093 # Number of store instructions
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+system.cpu.dcache.LoadLockedReq_hits::0 236142 # number of LoadLockedReq hits
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+system.cpu.dcache.demand_misses::total 618865 # number of demand (read+write) misses
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+system.cpu.dcache.WriteReq_accesses::total 10208396 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::0 247593 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0 247592 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0 23747326 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 23747326 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0 23747326 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 23747326 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0 0.027222 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0 0.024519 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.046249 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::0 0.026060 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::0 0.026060 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::0 15864.036813 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 38158.586428 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16249.803511 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 24881.141283 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 24881.141283 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 564388 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 368563 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 250302 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses 11451 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 618865 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 618865 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 4741074500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 8800219500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 151723500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 13541294000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 13541294000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 146946835000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 40367455500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 187314290500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.027222 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024519 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.046249 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::0 0.026060 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::0 0.026060 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12863.674596 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35158.406645 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13249.803511 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.replacements 0 # number of replacements
+system.iocache.tagsinuse 0 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs no_value # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.iocache.overall_hits::0 0 # number of overall hits
+system.iocache.overall_hits::1 0 # number of overall hits
+system.iocache.overall_hits::total 0 # number of overall hits
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.overall_misses::0 0 # number of overall misses
+system.iocache.overall_misses::1 0 # number of overall misses
+system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks 0 # number of writebacks
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_uncacheable_latency 1341941439938 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency 1341941439938 # number of overall MSHR uncacheable cycles
+system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.replacements 0 # number of replacements
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 0 # number of writebacks
-system.l2c.ReadExReq_accesses::0 170353 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 170353 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0 62556 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 62556 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency 5605444000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 0.632786 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 107797 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 107797 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 4311880000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 0.632786 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 107797 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 675448 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 6192 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 681640 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 52063.722222 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 42597590.909091 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 42649654.631313 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0 657448 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 6170 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 663618 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 937147000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.026649 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.003553 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.030202 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 18000 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 22 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 18022 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 720880000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.026682 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 2.910530 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 2.937211 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 18022 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 29204423000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses::0 1839 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1839 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 313.940724 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 0.990756 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 72880000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.990756 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 1822 # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 743252000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 417140 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 417140 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 417140 # number of Writeback hits
-system.l2c.Writeback_hits::total 417140 # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 7.067586 # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 845801 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 6192 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 851993 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 52009.117864 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 297390500 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 297442509.117864 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.l2c.demand_hits::0 720004 # number of demand (read+write) hits
-system.l2c.demand_hits::1 6170 # number of demand (read+write) hits
-system.l2c.demand_hits::total 726174 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 6542591000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.148731 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.003553 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.152284 # miss rate for demand accesses
-system.l2c.demand_misses::0 125797 # number of demand (read+write) misses
-system.l2c.demand_misses::1 22 # number of demand (read+write) misses
-system.l2c.demand_misses::total 125819 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 5032760000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.148757 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 20.319606 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 20.468363 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 125819 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_blocks::0 5338.058091 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31318.757980 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.081452 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.477886 # Average percentage of cache occupancy
-system.l2c.overall_accesses::0 845801 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 6192 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 851993 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 52009.117864 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 297390500 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 297442509.117864 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 720004 # number of overall hits
-system.l2c.overall_hits::1 6170 # number of overall hits
-system.l2c.overall_hits::total 726174 # number of overall hits
-system.l2c.overall_miss_latency 6542591000 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.148731 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.003553 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.152284 # miss rate for overall accesses
-system.l2c.overall_misses::0 125797 # number of overall misses
-system.l2c.overall_misses::1 22 # number of overall misses
-system.l2c.overall_misses::total 125819 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 5032760000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.148757 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 20.319606 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 20.468363 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 125819 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 29947675000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 93111 # number of replacements
-system.l2c.sampled_refs 124568 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 36656.816071 # Cycle average of tags in use
-system.l2c.total_refs 880395 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 87350 # number of writebacks
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
index 624e9a5f7..8953751c2 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
@@ -1 +1 @@
-build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!
+build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
index d2aa844f8..33e436852 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
Binary files differ