diff options
| author | Steve Reinhardt <stever@gmail.com> | 2007-08-03 18:04:30 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2007-08-03 18:04:30 -0400 |
| commit | bb3f7dc83b9a4c7b20aeb893fea447854c855225 (patch) | |
| tree | 17d17b775e1155fa42725df488ddd22a3ce65af8 /tests/quick/10.linux-boot/ref | |
| parent | 851e3c852be4eb031293ed271502a0e14ca9273f (diff) | |
| download | gem5-bb3f7dc83b9a4c7b20aeb893fea447854c855225.tar.xz | |
tests: new ref outputs for new cache model
--HG--
extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
Diffstat (limited to 'tests/quick/10.linux-boot/ref')
16 files changed, 944 insertions, 1270 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 2d3b1a754..d3a9862e8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -35,7 +35,7 @@ side_b=system.membus.port[0] [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache itb +children=dcache dtb icache itb tracer clock=500 cpu_id=0 defer_registration=false @@ -55,18 +55,16 @@ profile=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu0.tracer width=1 dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -84,12 +82,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu0.dcache.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -98,23 +94,15 @@ write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.port[2] -[system.cpu0.dcache.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu0.dtb] type=AlphaDTB size=64 [system.cpu0.icache] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=1 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -132,12 +120,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu0.icache.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -146,18 +132,16 @@ write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.port[1] -[system.cpu0.icache.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu0.itb] type=AlphaITB size=48 +[system.cpu0.tracer] +type=ExeTracer + [system.cpu1] type=AtomicSimpleCPU -children=dcache dtb icache itb +children=dcache dtb icache itb tracer clock=500 cpu_id=1 defer_registration=false @@ -177,18 +161,16 @@ profile=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu1.tracer width=1 dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -206,12 +188,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu1.dcache.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -220,23 +200,15 @@ write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.port[4] -[system.cpu1.dcache.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu1.dtb] type=AlphaDTB size=64 [system.cpu1.icache] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=1 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -254,12 +226,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu1.icache.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -268,15 +238,13 @@ write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.port[3] -[system.cpu1.icache.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu1.itb] type=AlphaITB size=48 +[system.cpu1.tracer] +type=ExeTracer + [system.disk0] type=IdeDisk children=image @@ -331,11 +299,9 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.l2c] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=8 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=10000 lifo=false @@ -353,12 +319,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=4194304 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=16 trace_addr=0 @@ -922,7 +886,7 @@ pio_addr=8804615847936 pio_latency=1000 platform=system.tsunami system=system -time=2009 1 1 0 0 0 3 1 +time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami year_is_bcd=false pio=system.iobus.port[23] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 3458060ce..df780ee45 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,20 +1,29 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1418499 # Simulator instruction rate (inst/s) -host_seconds 44.50 # Real time elapsed on the host -host_tick_rate 42028043491 # Simulator tick rate (ticks/s) +host_inst_rate 1258571 # Simulator instruction rate (inst/s) +host_mem_usage 256444 # Number of bytes of host memory used +host_seconds 50.16 # Real time elapsed on the host +host_tick_rate 37289409683 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63125943 # Number of instructions simulated sim_seconds 1.870335 # Number of seconds simulated sim_ticks 1870335101500 # Number of ticks simulated -system.cpu0.dcache.ReadReq_accesses 9163941 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 7464198 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_rate 0.185482 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1699743 # number of ReadReq misses -system.cpu0.dcache.WriteReq_accesses 5933396 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 5646722 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate 0.048315 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 286674 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses +system.cpu0.dcache.ReadReq_accesses 8975658 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7292076 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.187572 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1683582 # number of ReadReq misses +system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_hits 159819 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_rate 0.146827 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 27504 # number of StoreCondReq misses +system.cpu0.dcache.WriteReq_accesses 5746073 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5372266 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 373807 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 6.625567 # Average number of references to valid blocks. @@ -23,13 +32,13 @@ system.cpu0.dcache.blocked_no_targets 0 # nu system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 15097337 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses 14721731 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.dcache.demand_hits 13110920 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits 12664342 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.131574 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 1986417 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate 0.139752 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 2057389 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -37,14 +46,14 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 15097337 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses 14721731 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 13110920 # number of overall hits +system.cpu0.dcache.overall_hits 12664342 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.131574 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 1986417 # number of overall misses +system.cpu0.dcache.overall_miss_rate 0.139752 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 2057389 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -60,39 +69,13 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu0.dcache.protocol.read_invalid 1699743 # read misses to invalid blocks -system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu0.dcache.protocol.snoop_inv_modified 2 # Invalidate snoops on modified blocks -system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu0.dcache.protocol.snoop_read_exclusive 689 # read snoops on exclusive blocks -system.cpu0.dcache.protocol.snoop_read_modified 4128 # read snoops on modified blocks -system.cpu0.dcache.protocol.snoop_read_owned 121 # read snoops on owned blocks -system.cpu0.dcache.protocol.snoop_read_shared 2691 # read snoops on shared blocks -system.cpu0.dcache.protocol.snoop_readex_exclusive 241 # readEx snoops on exclusive blocks -system.cpu0.dcache.protocol.snoop_readex_modified 227 # readEx snoops on modified blocks -system.cpu0.dcache.protocol.snoop_readex_owned 21 # readEx snoops on owned blocks -system.cpu0.dcache.protocol.snoop_readex_shared 14 # readEx snoops on shared blocks -system.cpu0.dcache.protocol.snoop_upgrade_owned 1359 # upgrade snoops on owned blocks -system.cpu0.dcache.protocol.snoop_upgrade_shared 725 # upgradee snoops on shared blocks -system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu0.dcache.protocol.write_invalid 282338 # write misses to invalid blocks -system.cpu0.dcache.protocol.write_owned 2517 # write misses to owned blocks -system.cpu0.dcache.protocol.write_shared 1819 # write misses to shared blocks system.cpu0.dcache.replacements 1978980 # number of replacements system.cpu0.dcache.sampled_refs 1979492 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.dcache.tagsinuse 504.827576 # Cycle average of tags in use system.cpu0.dcache.total_refs 13115256 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 0 # number of writebacks +system.cpu0.dcache.writebacks 396796 # number of writebacks system.cpu0.dtb.accesses 698037 # DTB accesses system.cpu0.dtb.acv 251 # DTB access violations system.cpu0.dtb.hits 15082969 # DTB hits @@ -154,32 +137,6 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu0.icache.protocol.read_invalid 884872 # read misses to invalid blocks -system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks -system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu0.icache.protocol.snoop_read_exclusive 25832 # read snoops on exclusive blocks -system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks -system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks -system.cpu0.icache.protocol.snoop_read_shared 13268 # read snoops on shared blocks -system.cpu0.icache.protocol.snoop_readex_exclusive 78 # readEx snoops on exclusive blocks -system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks -system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks -system.cpu0.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks -system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks -system.cpu0.icache.protocol.snoop_upgrade_shared 6 # upgradee snoops on shared blocks -system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks -system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks -system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks system.cpu0.icache.replacements 884276 # number of replacements system.cpu0.icache.sampled_refs 884788 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -285,14 +242,22 @@ system.cpu0.not_idle_fraction 0.015290 # Pe system.cpu0.numCycles 57193784 # number of cpu cycles simulated system.cpu0.num_insts 57190172 # Number of instructions executed system.cpu0.num_refs 15322419 # Number of memory references -system.cpu1.dcache.ReadReq_accesses 1167383 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_hits 1124444 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_rate 0.036782 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 42939 # number of ReadReq misses -system.cpu1.dcache.WriteReq_accesses 749650 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits 723062 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate 0.035467 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 26588 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses +system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses +system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses +system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 702800 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.041599 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 30505 # number of WriteReq misses system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks. @@ -301,13 +266,13 @@ system.cpu1.dcache.blocked_no_targets 0 # nu system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1917033 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1847506 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits 1812115 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.036268 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 69527 # number of demand (read+write) misses +system.cpu1.dcache.demand_miss_rate 0.038293 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 72155 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -315,14 +280,14 @@ system.cpu1.dcache.demand_mshr_misses 0 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1917033 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1847506 # number of overall hits +system.cpu1.dcache.overall_hits 1812115 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.036268 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 69527 # number of overall misses +system.cpu1.dcache.overall_miss_rate 0.038293 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 72155 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -338,39 +303,13 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu1.dcache.protocol.read_invalid 42939 # read misses to invalid blocks -system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks -system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu1.dcache.protocol.snoop_read_exclusive 939 # read snoops on exclusive blocks -system.cpu1.dcache.protocol.snoop_read_modified 2438 # read snoops on modified blocks -system.cpu1.dcache.protocol.snoop_read_owned 337 # read snoops on owned blocks -system.cpu1.dcache.protocol.snoop_read_shared 61772 # read snoops on shared blocks -system.cpu1.dcache.protocol.snoop_readex_exclusive 103 # readEx snoops on exclusive blocks -system.cpu1.dcache.protocol.snoop_readex_modified 275 # readEx snoops on modified blocks -system.cpu1.dcache.protocol.snoop_readex_owned 44 # readEx snoops on owned blocks -system.cpu1.dcache.protocol.snoop_readex_shared 39 # readEx snoops on shared blocks -system.cpu1.dcache.protocol.snoop_upgrade_owned 1538 # upgrade snoops on owned blocks -system.cpu1.dcache.protocol.snoop_upgrade_shared 2755 # upgradee snoops on shared blocks -system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu1.dcache.protocol.write_invalid 24475 # write misses to invalid blocks -system.cpu1.dcache.protocol.write_owned 641 # write misses to owned blocks -system.cpu1.dcache.protocol.write_shared 1472 # write misses to shared blocks system.cpu1.dcache.replacements 62341 # number of replacements system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1851266680500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 0 # number of writebacks +system.cpu1.dcache.writebacks 30850 # number of writebacks system.cpu1.dtb.accesses 323622 # DTB accesses system.cpu1.dtb.acv 116 # DTB access violations system.cpu1.dtb.hits 1914885 # DTB hits @@ -432,32 +371,6 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu1.icache.protocol.read_invalid 103636 # read misses to invalid blocks -system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks -system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu1.icache.protocol.snoop_read_exclusive 17317 # read snoops on exclusive blocks -system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks -system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks -system.cpu1.icache.protocol.snoop_read_shared 199395 # read snoops on shared blocks -system.cpu1.icache.protocol.snoop_readex_exclusive 25 # readEx snoops on exclusive blocks -system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks -system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks -system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks -system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks -system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks -system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks -system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks -system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks system.cpu1.icache.replacements 103097 # number of replacements system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -559,30 +472,33 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_hits 181108 # number of ReadExReq hits -system.l2c.ReadExReq_miss_rate 0.408619 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 125138 # number of ReadExReq misses +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 306246 # number of ReadExReq misses system.l2c.ReadReq_accesses 2724166 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1782863 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.345538 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 941303 # number of ReadReq misses -system.l2c.Writeback_accesses 427634 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 427634 # number of Writeback hits +system.l2c.ReadReq_hits 1625506 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.403301 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 1098660 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 125013 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 125013 # number of UpgradeReq misses +system.l2c.Writeback_accesses 427646 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses +system.l2c.Writeback_misses 427646 # number of Writeback misses system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 2.242879 # Average number of references to valid blocks. +system.l2c.avg_refs 1.720013 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2724166 # number of demand (read+write) accesses +system.l2c.demand_accesses 3030412 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1782863 # number of demand (read+write) hits +system.l2c.demand_hits 1625506 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.345538 # miss rate for demand accesses -system.l2c.demand_misses 941303 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.463602 # miss rate for demand accesses +system.l2c.demand_misses 1404906 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -590,14 +506,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3151800 # number of overall (read+write) accesses +system.l2c.overall_accesses 3030412 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 2210497 # number of overall hits +system.l2c.overall_hits 1625506 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.298656 # miss rate for overall accesses -system.l2c.overall_misses 941303 # number of overall misses +system.l2c.overall_miss_rate 0.463602 # miss rate for overall accesses +system.l2c.overall_misses 1404906 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -613,12 +529,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1000779 # number of replacements -system.l2c.sampled_refs 1066159 # Sample count of references to valid blocks. +system.l2c.replacements 947869 # number of replacements +system.l2c.sampled_refs 966791 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 65517.575356 # Cycle average of tags in use -system.l2c.total_refs 2391266 # Total number of references to valid blocks. -system.l2c.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. +system.l2c.tagsinuse 15587.342424 # Cycle average of tags in use +system.l2c.total_refs 1662893 # Total number of references to valid blocks. +system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 3e1cbc554..563ca3160 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,5 +1,5 @@ -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... warn: 97861500: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index e4b69d1d0..1298154d9 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 10 2007 14:10:03 -M5 started Mon Jun 11 01:04:58 2007 -M5 executing on iceaxe -command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +M5 compiled Aug 3 2007 04:02:11 +M5 started Fri Aug 3 04:22:43 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 1870335097000 because m5_exit instruction encountered +Exiting @ tick 1870335101500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 0347fbde9..3457f5f8f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -35,7 +35,7 @@ side_b=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dcache dtb icache itb +children=dcache dtb icache itb tracer clock=500 cpu_id=0 defer_registration=false @@ -55,18 +55,16 @@ profile=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu.tracer width=1 dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -84,12 +82,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu.dcache.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -98,23 +94,15 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.toL2Bus.port[2] -[system.cpu.dcache.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu.dtb] type=AlphaDTB size=64 [system.cpu.icache] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=1 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -132,12 +120,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu.icache.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -146,15 +132,13 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.toL2Bus.port[1] -[system.cpu.icache.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu.itb] type=AlphaITB size=48 +[system.cpu.tracer] +type=ExeTracer + [system.disk0] type=IdeDisk children=image @@ -209,11 +193,9 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.l2c] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=8 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=10000 lifo=false @@ -231,12 +213,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=4194304 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=16 trace_addr=0 @@ -800,7 +780,7 @@ pio_addr=8804615847936 pio_latency=1000 platform=system.tsunami system=system -time=2009 1 1 0 0 0 3 1 +time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami year_is_bcd=false pio=system.iobus.port[23] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index 722437701..cc91e4c90 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,35 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1403977 # Simulator instruction rate (inst/s) -host_seconds 42.74 # Real time elapsed on the host -host_tick_rate 42777462102 # Simulator tick rate (ticks/s) +host_inst_rate 1294756 # Simulator instruction rate (inst/s) +host_mem_usage 255900 # Number of bytes of host memory used +host_seconds 46.35 # Real time elapsed on the host +host_tick_rate 39449403667 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60007317 # Number of instructions simulated sim_seconds 1.828355 # Number of seconds simulated -sim_ticks 1828355486000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 9723333 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7984498 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate 0.178831 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1738835 # number of ReadReq misses -system.cpu.dcache.WriteReq_accesses 6349447 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits 6045093 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate 0.047934 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 304354 # number of WriteReq misses +sim_ticks 1828355476000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 183119 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17160 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses 9523054 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7801377 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.180790 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1721677 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 169392 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate 0.149886 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 29866 # number of StoreCondReq misses +system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 5750772 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.064944 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 399417 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.866566 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.866558 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 16072780 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 15673243 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 14029591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 13552149 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.127121 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2043189 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.135332 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2121094 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -37,14 +46,14 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 16072780 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 15673243 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 14029591 # number of overall hits +system.cpu.dcache.overall_hits 13552149 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.127121 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2043189 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.135332 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2121094 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -60,39 +69,13 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu.dcache.protocol.read_invalid 1738835 # read misses to invalid blocks -system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu.dcache.protocol.snoop_inv_modified 1 # Invalidate snoops on modified blocks -system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu.dcache.protocol.snoop_read_exclusive 10 # read snoops on exclusive blocks -system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks -system.cpu.dcache.protocol.snoop_read_owned 2 # read snoops on owned blocks -system.cpu.dcache.protocol.snoop_read_shared 124 # read snoops on shared blocks -system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks -system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks -system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks -system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks -system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks -system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks -system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu.dcache.protocol.write_invalid 304342 # write misses to invalid blocks -system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks -system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks -system.cpu.dcache.replacements 2042664 # number of replacements -system.cpu.dcache.sampled_refs 2043176 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2042666 # number of replacements +system.cpu.dcache.sampled_refs 2043178 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use -system.cpu.dcache.total_refs 14029603 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 14029601 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.writebacks 428885 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations system.cpu.dtb.hits 16053818 # DTB hits @@ -106,12 +89,12 @@ system.cpu.dtb.write_acv 157 # DT system.cpu.dtb.write_hits 6349968 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits 59087263 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 59087260 # number of ReadReq hits system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 920054 # number of ReadReq misses +system.cpu.icache.ReadReq_misses 920057 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 64.229545 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 64.229332 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -120,10 +103,10 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 59087263 # number of demand (read+write) hits +system.cpu.icache.demand_hits 59087260 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses -system.cpu.icache.demand_misses 920054 # number of demand (read+write) misses +system.cpu.icache.demand_misses 920057 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -135,10 +118,10 @@ system.cpu.icache.overall_accesses 60007317 # nu system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59087263 # number of overall hits +system.cpu.icache.overall_hits 59087260 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses -system.cpu.icache.overall_misses 920054 # number of overall misses +system.cpu.icache.overall_misses 920057 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -154,37 +137,11 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu.icache.protocol.read_invalid 920054 # read misses to invalid blocks -system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks -system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu.icache.protocol.snoop_read_exclusive 643 # read snoops on exclusive blocks -system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks -system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks -system.cpu.icache.protocol.snoop_read_shared 1039 # read snoops on shared blocks -system.cpu.icache.protocol.snoop_readex_exclusive 105 # readEx snoops on exclusive blocks -system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks -system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks -system.cpu.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks -system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks -system.cpu.icache.protocol.snoop_upgrade_shared 9 # upgradee snoops on shared blocks -system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks -system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks -system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks -system.cpu.icache.replacements 919427 # number of replacements -system.cpu.icache.sampled_refs 919939 # Sample count of references to valid blocks. +system.cpu.icache.replacements 919430 # number of replacements +system.cpu.icache.sampled_refs 919942 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use -system.cpu.icache.total_refs 59087263 # Total number of references to valid blocks. +system.cpu.icache.total_refs 59087260 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0.983588 # Percentage of idle cycles @@ -222,8 +179,8 @@ system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # nu system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1828355278500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1811087547500 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks 1828355268500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087537500 99.06% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl @@ -243,7 +200,7 @@ system.cpu.kern.mode_switch_good_user 1 # fr system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1800056182000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056172000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -293,30 +250,33 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_hits 187346 # number of ReadExReq hits -system.l2c.ReadExReq_miss_rate 0.384423 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 116996 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2658872 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1717828 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.353926 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 941044 # number of ReadReq misses +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 304342 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2658877 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1558398 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.413889 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 1100479 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 124941 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 124941 # number of UpgradeReq misses system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 428885 # number of Writeback hits +system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses +system.l2c.Writeback_misses 428885 # number of Writeback misses system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 2.205901 # Average number of references to valid blocks. +system.l2c.avg_refs 1.644070 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2658872 # number of demand (read+write) accesses +system.l2c.demand_accesses 2963219 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1717828 # number of demand (read+write) hits +system.l2c.demand_hits 1558398 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.353926 # miss rate for demand accesses -system.l2c.demand_misses 941044 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.474086 # miss rate for demand accesses +system.l2c.demand_misses 1404821 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -324,14 +284,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3087757 # number of overall (read+write) accesses +system.l2c.overall_accesses 2963219 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 2146713 # number of overall hits +system.l2c.overall_hits 1558398 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.304766 # miss rate for overall accesses -system.l2c.overall_misses 941044 # number of overall misses +system.l2c.overall_miss_rate 0.474086 # miss rate for overall accesses +system.l2c.overall_misses 1404821 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -347,12 +307,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 992432 # number of replacements -system.l2c.sampled_refs 1057820 # Sample count of references to valid blocks. +system.l2c.replacements 947436 # number of replacements +system.l2c.sampled_refs 965232 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 65517.661064 # Cycle average of tags in use -system.l2c.total_refs 2333446 # Total number of references to valid blocks. -system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.tagsinuse 15309.548937 # Cycle average of tags in use +system.l2c.total_refs 1586909 # Total number of references to valid blocks. +system.l2c.warmup_cycle 789998500 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index f34493a86..32120d9d6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,3 +1,3 @@ -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index 6a6b8d735..1f648aea1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 10 2007 14:10:03 -M5 started Mon Jun 11 00:55:45 2007 -M5 executing on iceaxe -command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +M5 compiled Aug 3 2007 04:02:11 +M5 started Fri Aug 3 04:21:55 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 1828355481500 because m5_exit instruction encountered +Exiting @ tick 1828355476000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 552344dcb..bbfd059cd 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -35,7 +35,7 @@ side_b=system.membus.port[0] [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache itb +children=dcache dtb icache itb tracer clock=500 cpu_id=0 defer_registration=false @@ -54,17 +54,15 @@ phase=0 profile=0 progress_interval=0 system=system +tracer=system.cpu0.tracer dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -82,12 +80,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu0.dcache.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -96,23 +92,15 @@ write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.port[2] -[system.cpu0.dcache.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu0.dtb] type=AlphaDTB size=64 [system.cpu0.icache] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=1 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -130,12 +118,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu0.icache.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -144,18 +130,16 @@ write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.port[1] -[system.cpu0.icache.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu0.itb] type=AlphaITB size=48 +[system.cpu0.tracer] +type=ExeTracer + [system.cpu1] type=TimingSimpleCPU -children=dcache dtb icache itb +children=dcache dtb icache itb tracer clock=500 cpu_id=1 defer_registration=false @@ -174,17 +158,15 @@ phase=0 profile=0 progress_interval=0 system=system +tracer=system.cpu1.tracer dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -202,12 +184,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu1.dcache.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -216,23 +196,15 @@ write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.port[4] -[system.cpu1.dcache.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu1.dtb] type=AlphaDTB size=64 [system.cpu1.icache] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=1 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -250,12 +222,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu1.icache.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -264,15 +234,13 @@ write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.port[3] -[system.cpu1.icache.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu1.itb] type=AlphaITB size=48 +[system.cpu1.tracer] +type=ExeTracer + [system.disk0] type=IdeDisk children=image @@ -327,11 +295,9 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.l2c] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=8 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=10000 lifo=false @@ -349,12 +315,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=4194304 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=16 trace_addr=0 @@ -918,7 +882,7 @@ pio_addr=8804615847936 pio_latency=1000 platform=system.tsunami system=system -time=2009 1 1 0 0 0 3 1 +time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami year_is_bcd=false pio=system.iobus.port[23] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 0e86983a6..b7e78eb06 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,74 +1,93 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 62524 # Simulator instruction rate (inst/s) -host_seconds 1011.60 # Real time elapsed on the host -host_tick_rate 1928760125 # Simulator tick rate (ticks/s) +host_inst_rate 608366 # Simulator instruction rate (inst/s) +host_mem_usage 227884 # Number of bytes of host memory used +host_seconds 106.58 # Real time elapsed on the host +host_tick_rate 18308931831 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 63248814 # Number of instructions simulated -sim_seconds 1.951129 # Number of seconds simulated -sim_ticks 1951129131000 # Number of ticks simulated -system.cpu0.dcache.ReadReq_accesses 9299202 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 13073.177688 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12073.152824 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 7589849 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 22346675500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.183817 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1709353 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 20637280000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.183817 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 1709353 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable 6873 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu0.dcache.ReadResp_mshr_uncacheable_latency 841915000 # number of ReadResp MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_accesses 6016348 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 12644.438594 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 11630.972878 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 5727689 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 3649931000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.047979 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 288659 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 3357385000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.047979 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 288659 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable 9698 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu0.dcache.WriteResp_mshr_uncacheable_latency 1186164500 # number of WriteResp MSHR uncacheable cycles +sim_insts 64839479 # Number of instructions simulated +sim_seconds 1.951367 # Number of seconds simulated +sim_ticks 1951367346000 # Number of ticks simulated +system.cpu0.dcache.LoadLockedReq_accesses 150248 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 10860.561606 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9860.561606 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 136751 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 146585000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.089831 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 13497 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 133088000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.089831 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 13497 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 7920707 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 13239.029006 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12239.003253 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_hits 6328668 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 21077050500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.200997 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1592039 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 19484970500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.200997 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1592039 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 846944000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 149727 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 12266.165876 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 11266.165876 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 126963 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 279227000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.152037 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 22764 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 256463000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.152037 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 22764 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 4824283 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 13877.297001 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 12877.297001 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_hits 4508382 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 4383852000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.065481 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 315901 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 4067951000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.065481 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 315901 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1297859000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.687909 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 6.121232 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 15315550 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 13011.236419 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 13317538 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 25996606500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.130456 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 1998012 # number of demand (read+write) misses +system.cpu0.dcache.demand_accesses 12744990 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 13344.708167 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 12344.686678 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 10837050 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 25460902500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.149701 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1907940 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 23994665000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.130456 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1998012 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_miss_latency 23552921500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.149701 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1907940 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 15315550 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 13011.236419 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 13317538 # number of overall hits -system.cpu0.dcache.overall_miss_latency 25996606500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.130456 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 1998012 # number of overall misses +system.cpu0.dcache.overall_accesses 12744990 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 13344.708167 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 12344.686678 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 10837050 # number of overall hits +system.cpu0.dcache.overall_miss_latency 25460902500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.149701 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1907940 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 23994665000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.130456 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1998012 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_misses 16571 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_miss_latency 23552921500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.149701 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1907940 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2144803000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -78,95 +97,69 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu0.dcache.protocol.read_invalid 1709421 # read misses to invalid blocks -system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu0.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks -system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu0.dcache.protocol.snoop_read_exclusive 908 # read snoops on exclusive blocks -system.cpu0.dcache.protocol.snoop_read_modified 3762 # read snoops on modified blocks -system.cpu0.dcache.protocol.snoop_read_owned 72 # read snoops on owned blocks -system.cpu0.dcache.protocol.snoop_read_shared 2297 # read snoops on shared blocks -system.cpu0.dcache.protocol.snoop_readex_exclusive 235 # readEx snoops on exclusive blocks -system.cpu0.dcache.protocol.snoop_readex_modified 207 # readEx snoops on modified blocks -system.cpu0.dcache.protocol.snoop_readex_owned 15 # readEx snoops on owned blocks -system.cpu0.dcache.protocol.snoop_readex_shared 7 # readEx snoops on shared blocks -system.cpu0.dcache.protocol.snoop_upgrade_owned 1074 # upgrade snoops on owned blocks -system.cpu0.dcache.protocol.snoop_upgrade_shared 726 # upgradee snoops on shared blocks -system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu0.dcache.protocol.write_invalid 284810 # write misses to invalid blocks -system.cpu0.dcache.protocol.write_owned 2533 # write misses to owned blocks -system.cpu0.dcache.protocol.write_shared 1354 # write misses to shared blocks -system.cpu0.dcache.replacements 1991354 # number of replacements -system.cpu0.dcache.sampled_refs 1991866 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1829212 # number of replacements +system.cpu0.dcache.sampled_refs 1829724 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 503.775443 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13321418 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 57953000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 401606 # number of writebacks -system.cpu0.dtb.accesses 719860 # DTB accesses -system.cpu0.dtb.acv 289 # DTB access violations -system.cpu0.dtb.hits 15299767 # DTB hits -system.cpu0.dtb.misses 8485 # DTB misses -system.cpu0.dtb.read_accesses 524201 # DTB read accesses -system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 9282693 # DTB read hits -system.cpu0.dtb.read_misses 7687 # DTB read misses -system.cpu0.dtb.write_accesses 195659 # DTB write accesses -system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 6017074 # DTB write hits -system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57872551 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 12029.752588 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11029.000057 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 56957639 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 11006165000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.015809 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 914912 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 10090564500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.015809 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 914912 # number of ReadReq MSHR misses +system.cpu0.dcache.tagsinuse 497.900810 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11200165 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 58293000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 322933 # number of writebacks +system.cpu0.dtb.accesses 725071 # DTB accesses +system.cpu0.dtb.acv 305 # DTB access violations +system.cpu0.dtb.hits 13035385 # DTB hits +system.cpu0.dtb.misses 8682 # DTB misses +system.cpu0.dtb.read_accesses 527638 # DTB read accesses +system.cpu0.dtb.read_acv 184 # DTB read access violations +system.cpu0.dtb.read_hits 8058540 # DTB read hits +system.cpu0.dtb.read_misses 7858 # DTB read misses +system.cpu0.dtb.write_accesses 197433 # DTB write accesses +system.cpu0.dtb.write_acv 121 # DTB write access violations +system.cpu0.dtb.write_hits 4976845 # DTB write hits +system.cpu0.dtb.write_misses 824 # DTB write misses +system.cpu0.icache.ReadReq_accesses 51081135 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 12048.344860 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11047.036239 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 50399501 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 8212561500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.013344 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 681634 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 7530035500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.013344 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 681634 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 62.632934 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 73.953888 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57872551 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 12029.752588 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency -system.cpu0.icache.demand_hits 56957639 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 11006165000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.015809 # miss rate for demand accesses -system.cpu0.icache.demand_misses 914912 # number of demand (read+write) misses +system.cpu0.icache.demand_accesses 51081135 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 12048.344860 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11047.036239 # average overall mshr miss latency +system.cpu0.icache.demand_hits 50399501 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 8212561500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.013344 # miss rate for demand accesses +system.cpu0.icache.demand_misses 681634 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 10090564500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.015809 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 914912 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_miss_latency 7530035500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.013344 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 681634 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57872551 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 12029.752588 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency +system.cpu0.icache.overall_accesses 51081135 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 12048.344860 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11047.036239 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 56957639 # number of overall hits -system.cpu0.icache.overall_miss_latency 11006165000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.015809 # miss rate for overall accesses -system.cpu0.icache.overall_misses 914912 # number of overall misses +system.cpu0.icache.overall_hits 50399501 # number of overall hits +system.cpu0.icache.overall_miss_latency 8212561500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.013344 # miss rate for overall accesses +system.cpu0.icache.overall_misses 681634 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 10090564500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.015809 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 914912 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_miss_latency 7530035500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.013344 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 681634 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -178,199 +171,191 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu0.icache.protocol.read_invalid 915158 # read misses to invalid blocks -system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks -system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu0.icache.protocol.snoop_read_exclusive 4652 # read snoops on exclusive blocks -system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks -system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks -system.cpu0.icache.protocol.snoop_read_shared 8768 # read snoops on shared blocks -system.cpu0.icache.protocol.snoop_readex_exclusive 121 # readEx snoops on exclusive blocks -system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks -system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks -system.cpu0.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks -system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks -system.cpu0.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks -system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks -system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks -system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks -system.cpu0.icache.replacements 908876 # number of replacements -system.cpu0.icache.sampled_refs 909388 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 680987 # number of replacements +system.cpu0.icache.sampled_refs 681499 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 508.806183 # Cycle average of tags in use -system.cpu0.icache.total_refs 56957639 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 34906249000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tagsinuse 508.821605 # Cycle average of tags in use +system.cpu0.icache.total_refs 50399501 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 35300494000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.943968 # Percentage of idle cycles -system.cpu0.itb.accesses 3944641 # ITB accesses -system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 3940800 # ITB hits -system.cpu0.itb.misses 3841 # ITB misses -system.cpu0.kern.callpal 187118 # number of callpals executed +system.cpu0.idle_fraction 0.949890 # Percentage of idle cycles +system.cpu0.itb.accesses 3593148 # ITB accesses +system.cpu0.itb.acv 161 # ITB acv +system.cpu0.itb.hits 3589202 # ITB hits +system.cpu0.itb.misses 3946 # ITB misses +system.cpu0.kern.callpal 145952 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 96 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3865 2.07% 2.12% # number of callpals executed -system.cpu0.kern.callpal_tbi 44 0.02% 2.14% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.15% # number of callpals executed -system.cpu0.kern.callpal_swpipl 171254 91.52% 93.67% # number of callpals executed -system.cpu0.kern.callpal_rdps 6635 3.55% 97.21% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 97.21% # number of callpals executed -system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_rti 4694 2.51% 99.73% # number of callpals executed -system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 536 0.37% 0.37% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.37% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.37% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.37% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3014 2.07% 2.44% # number of callpals executed +system.cpu0.kern.callpal_tbi 46 0.03% 2.47% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.47% # number of callpals executed +system.cpu0.kern.callpal_swpipl 131018 89.77% 92.24% # number of callpals executed +system.cpu0.kern.callpal_rdps 6493 4.45% 96.69% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal_wrusp 4 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal_rdusp 8 0.01% 96.70% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal_rti 4302 2.95% 99.65% # number of callpals executed +system.cpu0.kern.callpal_callsys 368 0.25% 99.90% # number of callpals executed +system.cpu0.kern.callpal_imb 149 0.10% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 201983 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6162 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 178054 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 72322 40.62% 40.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 131 0.07% 40.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1968 1.11% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 103627 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 144005 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 70953 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1968 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 70947 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1951128432000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1894864204500 97.12% 97.12% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 72482500 0.00% 97.12% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 564462000 0.03% 97.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 4114000 0.00% 97.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 55623169000 2.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.981071 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 161590 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6598 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 137863 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 55298 40.11% 40.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.10% 40.21% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1969 1.43% 41.63% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 442 0.32% 41.95% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 80023 58.05% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 111708 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 54804 49.06% 49.06% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1969 1.76% 50.94% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 442 0.40% 51.34% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 54362 48.66% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1951366621000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1898503749000 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 76310500 0.00% 97.29% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 547835000 0.03% 97.32% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 278789500 0.01% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 51959937000 2.66% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.991067 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684638 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1230 -system.cpu0.kern.mode_good_user 1231 +system.cpu0.kern.ipl_used_31 0.679330 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1275 +system.cpu0.kern.mode_good_user 1276 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7215 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1231 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 6846 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1276 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.170478 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.186240 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1947973402000 99.84% 99.84% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 3155028000 0.16% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1948118613000 99.83% 99.83% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3248006000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3866 # number of times the context was actually changed -system.cpu0.kern.syscall 224 # number of syscalls executed -system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed -system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed -system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed -system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed -system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed -system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed -system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed -system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed -system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed -system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed -system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed -system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed -system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed -system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed -system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed -system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed -system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed -system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed -system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed -system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed -system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed -system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.056032 # Percentage of non-idle cycles -system.cpu0.numCycles 1951129131000 # number of cpu cycles simulated -system.cpu0.num_insts 57872550 # Number of instructions executed -system.cpu0.num_refs 15541096 # Number of memory references -system.cpu1.dcache.ReadReq_accesses 1052558 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 11119.734481 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10119.576119 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 1014670 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 421304500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.035996 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 37888 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 383410500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035996 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 37888 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable 120 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu1.dcache.ReadResp_mshr_uncacheable_latency 14641500 # number of ReadResp MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_accesses 677186 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 11920.138166 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 10843.231096 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 653157 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 286429000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.035484 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 24029 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 260552000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.035484 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 24029 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable 2496 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu1.dcache.WriteResp_mshr_uncacheable_latency 304596500 # number of WriteResp MSHR uncacheable cycles +system.cpu0.kern.swap_context 3015 # number of times the context was actually changed +system.cpu0.kern.syscall 228 # number of syscalls executed +system.cpu0.kern.syscall_2 7 3.07% 3.07% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.33% 11.40% # number of syscalls executed +system.cpu0.kern.syscall_4 3 1.32% 12.72% # number of syscalls executed +system.cpu0.kern.syscall_6 31 13.60% 26.32% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.44% 26.75% # number of syscalls executed +system.cpu0.kern.syscall_15 1 0.44% 27.19% # number of syscalls executed +system.cpu0.kern.syscall_17 10 4.39% 31.58% # number of syscalls executed +system.cpu0.kern.syscall_19 6 2.63% 34.21% # number of syscalls executed +system.cpu0.kern.syscall_20 4 1.75% 35.96% # number of syscalls executed +system.cpu0.kern.syscall_23 2 0.88% 36.84% # number of syscalls executed +system.cpu0.kern.syscall_24 4 1.75% 38.60% # number of syscalls executed +system.cpu0.kern.syscall_33 8 3.51% 42.11% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.88% 42.98% # number of syscalls executed +system.cpu0.kern.syscall_45 39 17.11% 60.09% # number of syscalls executed +system.cpu0.kern.syscall_47 4 1.75% 61.84% # number of syscalls executed +system.cpu0.kern.syscall_48 8 3.51% 65.35% # number of syscalls executed +system.cpu0.kern.syscall_54 9 3.95% 69.30% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.44% 69.74% # number of syscalls executed +system.cpu0.kern.syscall_59 6 2.63% 72.37% # number of syscalls executed +system.cpu0.kern.syscall_71 32 14.04% 86.40% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.32% 87.72% # number of syscalls executed +system.cpu0.kern.syscall_74 9 3.95% 91.67% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.44% 92.11% # number of syscalls executed +system.cpu0.kern.syscall_90 2 0.88% 92.98% # number of syscalls executed +system.cpu0.kern.syscall_92 7 3.07% 96.05% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.88% 96.93% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.88% 97.81% # number of syscalls executed +system.cpu0.kern.syscall_132 2 0.88% 98.68% # number of syscalls executed +system.cpu0.kern.syscall_144 1 0.44% 99.12% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.050110 # Percentage of non-idle cycles +system.cpu0.numCycles 1951367346000 # number of cpu cycles simulated +system.cpu0.num_insts 51081134 # Number of instructions executed +system.cpu0.num_refs 13268864 # Number of memory references +system.cpu1.dcache.LoadLockedReq_accesses 61056 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 9095.192614 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8095.192614 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 51633 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 85704000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.154334 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 9423 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 76281000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.154334 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses 9423 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 2457845 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 11653.965886 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10653.909138 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_hits 2334493 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 1437540000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.050187 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 123352 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 1314181000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.050187 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 123352 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 16729500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses 60551 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 10960.125479 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9960.125479 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 46206 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 157223000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.236908 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 14345 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 142878000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.236908 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 14345 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 1792743 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 13398.121192 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 12398.121192 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_hits 1700344 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 1237973000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.051541 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 92399 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1145574000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.051541 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 92399 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 421374000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 29.876823 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 23.577992 # Average number of references to valid blocks. system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1729744 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 11430.358383 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1667827 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 707733500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.035795 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 61917 # number of demand (read+write) misses +system.cpu1.dcache.demand_accesses 4250588 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 12400.929776 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 11400.897331 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 4034837 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 2675513000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.050758 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 215751 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 643962500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.035795 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 61917 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_miss_latency 2459755000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.050758 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 215751 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1729744 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 11430.358383 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1667827 # number of overall hits -system.cpu1.dcache.overall_miss_latency 707733500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.035795 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 61917 # number of overall misses +system.cpu1.dcache.overall_accesses 4250588 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 12400.929776 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 11400.897331 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 4034837 # number of overall hits +system.cpu1.dcache.overall_miss_latency 2675513000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.050758 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 215751 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 643962500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.035795 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 61917 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_misses 2616 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_miss_latency 2459755000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.050758 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 215751 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 438103500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -380,95 +365,69 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu1.dcache.protocol.read_invalid 37951 # read misses to invalid blocks -system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks -system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu1.dcache.protocol.snoop_read_exclusive 906 # read snoops on exclusive blocks -system.cpu1.dcache.protocol.snoop_read_modified 1965 # read snoops on modified blocks -system.cpu1.dcache.protocol.snoop_read_owned 254 # read snoops on owned blocks -system.cpu1.dcache.protocol.snoop_read_shared 65869 # read snoops on shared blocks -system.cpu1.dcache.protocol.snoop_readex_exclusive 191 # readEx snoops on exclusive blocks -system.cpu1.dcache.protocol.snoop_readex_modified 198 # readEx snoops on modified blocks -system.cpu1.dcache.protocol.snoop_readex_owned 48 # readEx snoops on owned blocks -system.cpu1.dcache.protocol.snoop_readex_shared 42 # readEx snoops on shared blocks -system.cpu1.dcache.protocol.snoop_upgrade_owned 1132 # upgrade snoops on owned blocks -system.cpu1.dcache.protocol.snoop_upgrade_shared 2716 # upgradee snoops on shared blocks -system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu1.dcache.protocol.write_invalid 22206 # write misses to invalid blocks -system.cpu1.dcache.protocol.write_owned 601 # write misses to owned blocks -system.cpu1.dcache.protocol.write_shared 1247 # write misses to shared blocks -system.cpu1.dcache.replacements 55360 # number of replacements -system.cpu1.dcache.sampled_refs 55749 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 176474 # number of replacements +system.cpu1.dcache.sampled_refs 176909 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 388.749341 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1665603 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1935095598000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 27663 # number of writebacks -system.cpu1.dtb.accesses 302878 # DTB accesses -system.cpu1.dtb.acv 84 # DTB access violations -system.cpu1.dtb.hits 1728432 # DTB hits -system.cpu1.dtb.misses 3106 # DTB misses -system.cpu1.dtb.read_accesses 205838 # DTB read accesses -system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 1049360 # DTB read hits -system.cpu1.dtb.read_misses 2750 # DTB read misses -system.cpu1.dtb.write_accesses 97040 # DTB write accesses -system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_hits 679072 # DTB write hits -system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5376264 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 12045.939531 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11045.466957 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 5281041 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 1147050500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.017712 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 95223 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1051782500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.017712 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 95223 # number of ReadReq MSHR misses +system.cpu1.dcache.tagsinuse 471.274557 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4171159 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1917859097000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 93260 # number of writebacks +system.cpu1.dtb.accesses 296718 # DTB accesses +system.cpu1.dtb.acv 62 # DTB access violations +system.cpu1.dtb.hits 4358656 # DTB hits +system.cpu1.dtb.misses 2867 # DTB misses +system.cpu1.dtb.read_accesses 201817 # DTB read accesses +system.cpu1.dtb.read_acv 26 # DTB read access violations +system.cpu1.dtb.read_hits 2507309 # DTB read hits +system.cpu1.dtb.read_misses 2546 # DTB read misses +system.cpu1.dtb.write_accesses 94901 # DTB write accesses +system.cpu1.dtb.write_acv 36 # DTB write access violations +system.cpu1.dtb.write_hits 1851347 # DTB write hits +system.cpu1.dtb.write_misses 321 # DTB write misses +system.cpu1.icache.ReadReq_accesses 13758345 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 12026.498126 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11026.342473 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 13421057 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 4056393500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.024515 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 337288 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 3719053000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.024515 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 337288 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 57.662729 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 39.794511 # Average number of references to valid blocks. system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5376264 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 12045.939531 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency -system.cpu1.icache.demand_hits 5281041 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 1147050500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.017712 # miss rate for demand accesses -system.cpu1.icache.demand_misses 95223 # number of demand (read+write) misses +system.cpu1.icache.demand_accesses 13758345 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 12026.498126 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11026.342473 # average overall mshr miss latency +system.cpu1.icache.demand_hits 13421057 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 4056393500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.024515 # miss rate for demand accesses +system.cpu1.icache.demand_misses 337288 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 1051782500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.017712 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 95223 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_miss_latency 3719053000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.024515 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 337288 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5376264 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 12045.939531 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency +system.cpu1.icache.overall_accesses 13758345 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 12026.498126 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11026.342473 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5281041 # number of overall hits -system.cpu1.icache.overall_miss_latency 1147050500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.017712 # miss rate for overall accesses -system.cpu1.icache.overall_misses 95223 # number of overall misses +system.cpu1.icache.overall_hits 13421057 # number of overall hits +system.cpu1.icache.overall_miss_latency 4056393500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.024515 # miss rate for overall accesses +system.cpu1.icache.overall_misses 337288 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 1051782500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.017712 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 95223 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_miss_latency 3719053000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.024515 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 337288 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -480,124 +439,98 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu1.icache.protocol.read_invalid 97341 # read misses to invalid blocks -system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks -system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu1.icache.protocol.snoop_read_exclusive 39627 # read snoops on exclusive blocks -system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks -system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks -system.cpu1.icache.protocol.snoop_read_shared 214588 # read snoops on shared blocks -system.cpu1.icache.protocol.snoop_readex_exclusive 26 # readEx snoops on exclusive blocks -system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks -system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks -system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks -system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks -system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks -system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks -system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks -system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks -system.cpu1.icache.replacements 91073 # number of replacements -system.cpu1.icache.sampled_refs 91585 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 336747 # number of replacements +system.cpu1.icache.sampled_refs 337259 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 420.500398 # Cycle average of tags in use -system.cpu1.icache.total_refs 5281041 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1947911714000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 445.859240 # Cycle average of tags in use +system.cpu1.icache.total_refs 13421057 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1946103109000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.995322 # Percentage of idle cycles -system.cpu1.itb.accesses 1399877 # ITB accesses -system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 1398631 # ITB hits -system.cpu1.itb.misses 1246 # ITB misses -system.cpu1.kern.callpal 29847 # number of callpals executed +system.cpu1.idle_fraction 0.987201 # Percentage of idle cycles +system.cpu1.itb.accesses 1878768 # ITB accesses +system.cpu1.itb.acv 23 # ITB acv +system.cpu1.itb.hits 1877648 # ITB hits +system.cpu1.itb.misses 1120 # ITB misses +system.cpu1.kern.callpal 75334 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 375 1.26% 1.29% # number of callpals executed -system.cpu1.kern.callpal_tbi 10 0.03% 1.32% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.02% 1.34% # number of callpals executed -system.cpu1.kern.callpal_swpipl 24461 81.95% 83.30% # number of callpals executed -system.cpu1.kern.callpal_rdps 2201 7.37% 90.67% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 90.68% # number of callpals executed -system.cpu1.kern.callpal_wrusp 3 0.01% 90.69% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.01% 90.69% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 90.70% # number of callpals executed -system.cpu1.kern.callpal_rti 2582 8.65% 99.35% # number of callpals executed -system.cpu1.kern.callpal_callsys 161 0.54% 99.89% # number of callpals executed -system.cpu1.kern.callpal_imb 31 0.10% 100.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 442 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal_swpctx 2091 2.78% 3.37% # number of callpals executed +system.cpu1.kern.callpal_tbi 7 0.01% 3.38% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.01% 3.38% # number of callpals executed +system.cpu1.kern.callpal_swpipl 66409 88.15% 91.54% # number of callpals executed +system.cpu1.kern.callpal_rdps 2344 3.11% 94.65% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 94.65% # number of callpals executed +system.cpu1.kern.callpal_wrusp 3 0.00% 94.65% # number of callpals executed +system.cpu1.kern.callpal_rdusp 1 0.00% 94.66% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.00% 94.66% # number of callpals executed +system.cpu1.kern.callpal_rti 3844 5.10% 99.76% # number of callpals executed +system.cpu1.kern.callpal_callsys 147 0.20% 99.96% # number of callpals executed +system.cpu1.kern.callpal_imb 31 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 36385 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2332 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 29103 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 9344 32.11% 32.11% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1963 6.75% 38.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 96 0.33% 39.18% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 17700 60.82% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 20635 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 9336 45.24% 45.24% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1963 9.51% 54.76% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 96 0.47% 55.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 9240 44.78% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1950372731000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1911409272000 98.00% 98.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 494740000 0.03% 98.03% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 52316000 0.00% 98.03% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 38416403000 1.97% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.999144 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 81908 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 72754 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 28089 38.61% 38.61% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1964 2.70% 41.31% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 536 0.74% 42.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 42165 57.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 56376 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 27206 48.26% 48.26% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1964 3.48% 51.74% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 536 0.95% 52.69% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 26670 47.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1951174446000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1904796411500 97.62% 97.62% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 499877500 0.03% 97.65% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 327859000 0.02% 97.67% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 45550298000 2.33% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.968564 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.522034 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 538 -system.cpu1.kern.mode_good_user 517 -system.cpu1.kern.mode_good_idle 21 -system.cpu1.kern.mode_switch_kernel 884 # number of protection mode switches -system.cpu1.kern.mode_switch_user 517 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2075 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.618718 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.608597 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.632515 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 924 +system.cpu1.kern.mode_good_user 463 +system.cpu1.kern.mode_good_idle 461 +system.cpu1.kern.mode_switch_kernel 2120 # number of protection mode switches +system.cpu1.kern.mode_switch_user 463 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2943 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.592492 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.435849 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.010120 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 3563216000 0.18% 0.18% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1513259000 0.08% 0.26% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1945257297000 99.74% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 376 # number of times the context was actually changed -system.cpu1.kern.syscall 102 # number of syscalls executed -system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed -system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed -system.cpu1.kern.syscall_4 1 0.98% 13.73% # number of syscalls executed -system.cpu1.kern.syscall_6 12 11.76% 25.49% # number of syscalls executed -system.cpu1.kern.syscall_17 5 4.90% 30.39% # number of syscalls executed -system.cpu1.kern.syscall_19 4 3.92% 34.31% # number of syscalls executed -system.cpu1.kern.syscall_20 2 1.96% 36.27% # number of syscalls executed -system.cpu1.kern.syscall_23 2 1.96% 38.24% # number of syscalls executed -system.cpu1.kern.syscall_24 2 1.96% 40.20% # number of syscalls executed -system.cpu1.kern.syscall_33 3 2.94% 43.14% # number of syscalls executed -system.cpu1.kern.syscall_45 15 14.71% 57.84% # number of syscalls executed -system.cpu1.kern.syscall_47 2 1.96% 59.80% # number of syscalls executed -system.cpu1.kern.syscall_48 3 2.94% 62.75% # number of syscalls executed -system.cpu1.kern.syscall_54 1 0.98% 63.73% # number of syscalls executed -system.cpu1.kern.syscall_59 2 1.96% 65.69% # number of syscalls executed -system.cpu1.kern.syscall_71 22 21.57% 87.25% # number of syscalls executed -system.cpu1.kern.syscall_74 7 6.86% 94.12% # number of syscalls executed -system.cpu1.kern.syscall_90 1 0.98% 95.10% # number of syscalls executed -system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed -system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed -system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.004678 # Percentage of non-idle cycles -system.cpu1.numCycles 1950372761000 # number of cpu cycles simulated -system.cpu1.num_insts 5376264 # Number of instructions executed -system.cpu1.num_refs 1738417 # Number of memory references +system.cpu1.kern.mode_switch_good_idle 0.156643 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 18594859000 0.95% 0.95% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1499702000 0.08% 1.03% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1930131145000 98.97% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2092 # number of times the context was actually changed +system.cpu1.kern.syscall 98 # number of syscalls executed +system.cpu1.kern.syscall_2 1 1.02% 1.02% # number of syscalls executed +system.cpu1.kern.syscall_3 11 11.22% 12.24% # number of syscalls executed +system.cpu1.kern.syscall_4 1 1.02% 13.27% # number of syscalls executed +system.cpu1.kern.syscall_6 11 11.22% 24.49% # number of syscalls executed +system.cpu1.kern.syscall_17 5 5.10% 29.59% # number of syscalls executed +system.cpu1.kern.syscall_19 4 4.08% 33.67% # number of syscalls executed +system.cpu1.kern.syscall_20 2 2.04% 35.71% # number of syscalls executed +system.cpu1.kern.syscall_23 2 2.04% 37.76% # number of syscalls executed +system.cpu1.kern.syscall_24 2 2.04% 39.80% # number of syscalls executed +system.cpu1.kern.syscall_33 3 3.06% 42.86% # number of syscalls executed +system.cpu1.kern.syscall_45 15 15.31% 58.16% # number of syscalls executed +system.cpu1.kern.syscall_47 2 2.04% 60.20% # number of syscalls executed +system.cpu1.kern.syscall_48 2 2.04% 62.24% # number of syscalls executed +system.cpu1.kern.syscall_54 1 1.02% 63.27% # number of syscalls executed +system.cpu1.kern.syscall_59 1 1.02% 64.29% # number of syscalls executed +system.cpu1.kern.syscall_71 22 22.45% 86.73% # number of syscalls executed +system.cpu1.kern.syscall_74 7 7.14% 93.88% # number of syscalls executed +system.cpu1.kern.syscall_90 1 1.02% 94.90% # number of syscalls executed +system.cpu1.kern.syscall_92 2 2.04% 96.94% # number of syscalls executed +system.cpu1.kern.syscall_132 2 2.04% 98.98% # number of syscalls executed +system.cpu1.kern.syscall_144 1 1.02% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.012799 # Percentage of non-idle cycles +system.cpu1.numCycles 1951174476000 # number of cpu cycles simulated +system.cpu1.num_insts 13758345 # Number of instructions executed +system.cpu1.num_refs 4385954 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -610,75 +543,80 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.l2c.ReadExReq_accesses 306499 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 12998.029396 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 10997.988681 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits 183694 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 1596223000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 0.400670 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 122805 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 1350608000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 0.400670 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 122805 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2751323 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 12999.901707 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 10999.990968 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits 1810263 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 12233687500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.342039 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 941060 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 10351530500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.342035 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 941049 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable 6993 # number of ReadReq MSHR uncacheable -system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.l2c.ReadResp_mshr_uncacheable_latency 779629500 # number of ReadResp MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable 12194 # number of WriteReq MSHR uncacheable -system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.l2c.WriteResp_mshr_uncacheable_latency 1356619000 # number of WriteResp MSHR uncacheable cycles -system.l2c.Writeback_accesses 429269 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 429256 # number of Writeback hits -system.l2c.Writeback_miss_rate 0.000030 # miss rate for Writeback accesses -system.l2c.Writeback_misses 13 # number of Writeback misses -system.l2c.Writeback_mshr_miss_rate 0.000030 # mshr miss rate for Writeback accesses -system.l2c.Writeback_mshr_misses 13 # number of Writeback MSHR misses +system.l2c.ReadExReq_accesses 297979 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 12000.808782 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 11000.808782 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 3575989000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 297979 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 3278010000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 297979 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2726406 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 12000.355770 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 11000.235046 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits 1633004 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 13121213000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.401042 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 1093402 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12027679000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.401042 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 1093402 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 779744500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 125211 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 11388.943463 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 11003.410244 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 1426021000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 125211 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 1377748000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 125211 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 1551434500 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 416193 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses +system.l2c.Writeback_misses 416193 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 416193 # number of Writeback MSHR misses system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 2.277768 # Average number of references to valid blocks. +system.l2c.avg_refs 1.713697 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2751323 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 12999.901707 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency -system.l2c.demand_hits 1810263 # number of demand (read+write) hits -system.l2c.demand_miss_latency 12233687500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.342039 # miss rate for demand accesses -system.l2c.demand_misses 941060 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 10351530500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.342035 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 941049 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses 3024385 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 12000.452788 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 11000.357918 # average overall mshr miss latency +system.l2c.demand_hits 1633004 # number of demand (read+write) hits +system.l2c.demand_miss_latency 16697202000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.460054 # miss rate for demand accesses +system.l2c.demand_misses 1391381 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 15305689000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.460054 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 1391381 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3180592 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 12999.722126 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.l2c.overall_hits 2239519 # number of overall hits -system.l2c.overall_miss_latency 12233687500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.295880 # miss rate for overall accesses -system.l2c.overall_misses 941073 # number of overall misses -system.l2c.overall_mshr_hits 11 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 10351530500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.295872 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 941049 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 19187 # number of overall MSHR uncacheable misses +system.l2c.overall_accesses 3024385 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 12000.452788 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 11000.357918 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits 1633004 # number of overall hits +system.l2c.overall_miss_latency 16697202000 # number of overall miss cycles +system.l2c.overall_miss_rate 0.460054 # miss rate for overall accesses +system.l2c.overall_misses 1391381 # number of overall misses +system.l2c.overall_mshr_hits 12 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 15305689000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.460054 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 1391381 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2331179000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -688,13 +626,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 998318 # number of replacements -system.l2c.sampled_refs 1063854 # Sample count of references to valid blocks. +system.l2c.replacements 947502 # number of replacements +system.l2c.sampled_refs 965785 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 65469.787238 # Cycle average of tags in use -system.l2c.total_refs 2423213 # Total number of references to valid blocks. -system.l2c.warmup_cycle 3064127000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 79556 # number of writebacks +system.l2c.tagsinuse 16369.951624 # Cycle average of tags in use +system.l2c.total_refs 1655063 # Total number of references to valid blocks. +system.l2c.warmup_cycle 5421925000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index af0df3710..e6ad9b469 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,5 +1,5 @@ -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... -warn: 423901000: Trying to launch CPU number 1! +warn: 427086000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 68b58c461..99539f3ea 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 10 2007 14:10:03 -M5 started Mon Jun 11 01:30:38 2007 -M5 executing on iceaxe -command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +M5 compiled Aug 3 2007 04:02:11 +M5 started Fri Aug 3 04:25:10 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 1951129131000 because m5_exit instruction encountered +Exiting @ tick 1951367346000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index c726f11fe..1992f65a2 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -35,7 +35,7 @@ side_b=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb +children=dcache dtb icache itb tracer clock=500 cpu_id=0 defer_registration=false @@ -54,17 +54,15 @@ phase=0 profile=0 progress_interval=0 system=system +tracer=system.cpu.tracer dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -82,12 +80,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu.dcache.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -96,23 +92,15 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.toL2Bus.port[2] -[system.cpu.dcache.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu.dtb] type=AlphaDTB size=64 [system.cpu.icache] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=1 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -130,12 +118,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu.icache.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -144,15 +130,13 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.toL2Bus.port[1] -[system.cpu.icache.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu.itb] type=AlphaITB size=48 +[system.cpu.tracer] +type=ExeTracer + [system.disk0] type=IdeDisk children=image @@ -207,11 +191,9 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.l2c] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=8 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=10000 lifo=false @@ -229,12 +211,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=4194304 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=16 trace_addr=0 @@ -798,7 +778,7 @@ pio_addr=8804615847936 pio_latency=1000 platform=system.tsunami system=system -time=2009 1 1 0 0 0 3 1 +time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami year_is_bcd=false pio=system.iobus.port[23] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index f72789e4b..958246a30 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,74 +1,93 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 62427 # Simulator instruction rate (inst/s) -host_seconds 961.73 # Real time elapsed on the host -host_tick_rate 1983042717 # Simulator tick rate (ticks/s) +host_inst_rate 631972 # Simulator instruction rate (inst/s) +host_mem_usage 219140 # Number of bytes of host memory used +host_seconds 95.00 # Real time elapsed on the host +host_tick_rate 20109299069 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 60037406 # Number of instructions simulated -sim_seconds 1.907146 # Number of seconds simulated -sim_ticks 1907146437000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 9726331 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13065.219101 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12065.192690 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 7984648 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 22755470000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.179069 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1741683 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 21013741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.179069 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1741683 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu.dcache.ReadResp_mshr_uncacheable_latency 824099000 # number of ReadResp MSHR uncacheable cycles -system.cpu.dcache.WriteReq_accesses 6350552 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 12768.106941 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11768.067509 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6046235 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3885552000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.047920 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 304317 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3581223000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.047920 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 304317 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu.dcache.WriteResp_mshr_uncacheable_latency 1154484000 # number of WriteResp MSHR uncacheable cycles +sim_insts 60034774 # Number of instructions simulated +sim_seconds 1.910310 # Number of seconds simulated +sim_ticks 1910309711000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200211 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 13960.656682 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12960.656682 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 182851 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 242357000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.086709 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17360 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 224997000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086709 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17360 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 9525872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13240.454388 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12240.427719 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_hits 7801048 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 22837453500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.181067 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1724824 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 21112583500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.181067 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1724824 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 830826000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 199189 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 14000.798456 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 13000.798456 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 169131 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 420836000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.150902 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 30058 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 390778000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150902 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 30058 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6151132 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 14000.947966 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000.947966 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_hits 5750801 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5605013500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.065082 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 400331 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5204682500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.065082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 400331 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1164414500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.857760 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.854770 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 16076883 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 13021.027370 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency -system.cpu.dcache.demand_hits 14030883 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26641022000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.127263 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2046000 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 15677004 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13383.714129 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12383.692484 # average overall mshr miss latency +system.cpu.dcache.demand_hits 13551849 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 28442467000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.135559 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2125155 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 24594964000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.127263 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2046000 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 26317266000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.135559 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2125155 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 16076883 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 13021.027370 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 14030883 # number of overall hits -system.cpu.dcache.overall_miss_latency 26641022000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.127263 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2046000 # number of overall misses +system.cpu.dcache.overall_accesses 15677004 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13383.714129 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12383.692484 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 13551849 # number of overall hits +system.cpu.dcache.overall_miss_latency 28442467000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.135559 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2125155 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 24594964000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.127263 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2046000 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_miss_latency 26317266000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.135559 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2125155 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 1995240500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -78,95 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu.dcache.protocol.read_invalid 1741683 # read misses to invalid blocks -system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks -system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu.dcache.protocol.snoop_read_exclusive 9 # read snoops on exclusive blocks -system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks -system.cpu.dcache.protocol.snoop_read_owned 4 # read snoops on owned blocks -system.cpu.dcache.protocol.snoop_read_shared 92 # read snoops on shared blocks -system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks -system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks -system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks -system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks -system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks -system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks -system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu.dcache.protocol.write_invalid 304305 # write misses to invalid blocks -system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks -system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks -system.cpu.dcache.replacements 2045476 # number of replacements -system.cpu.dcache.sampled_refs 2045988 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2046194 # number of replacements +system.cpu.dcache.sampled_refs 2046706 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.987904 # Cycle average of tags in use -system.cpu.dcache.total_refs 14030895 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 57945000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 429989 # number of writebacks +system.cpu.dcache.tagsinuse 511.987834 # Cycle average of tags in use +system.cpu.dcache.total_refs 14029698 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 58297000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 429991 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16057425 # DTB hits +system.cpu.dtb.hits 16056951 # DTB hits system.cpu.dtb.misses 11471 # DTB misses system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9706740 # DTB read hits +system.cpu.dtb.read_hits 9706492 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6350685 # DTB write hits +system.cpu.dtb.write_hits 6350459 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60037407 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 12029.456206 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11028.713640 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 59110217 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 11153591500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.015444 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 927190 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10225713000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.015444 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 927190 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 60034775 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 12033.060657 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11032.326155 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 59106935 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 11164755000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.015455 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 927840 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10236233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.015455 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 927840 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 63.763003 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 63.714789 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60037407 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 12029.456206 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency -system.cpu.icache.demand_hits 59110217 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 11153591500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.015444 # miss rate for demand accesses -system.cpu.icache.demand_misses 927190 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 60034775 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 12033.060657 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11032.326155 # average overall mshr miss latency +system.cpu.icache.demand_hits 59106935 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 11164755000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015455 # miss rate for demand accesses +system.cpu.icache.demand_misses 927840 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10225713000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.015444 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 927190 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 10236233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.015455 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 927840 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60037407 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 12029.456206 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency +system.cpu.icache.overall_accesses 60034775 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 12033.060657 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11032.326155 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59110217 # number of overall hits -system.cpu.icache.overall_miss_latency 11153591500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.015444 # miss rate for overall accesses -system.cpu.icache.overall_misses 927190 # number of overall misses +system.cpu.icache.overall_hits 59106935 # number of overall hits +system.cpu.icache.overall_miss_latency 11164755000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015455 # miss rate for overall accesses +system.cpu.icache.overall_misses 927840 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10225713000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.015444 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 927190 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 10236233500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.015455 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 927840 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -178,45 +171,19 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu.icache.protocol.read_invalid 927190 # read misses to invalid blocks -system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks -system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu.icache.protocol.snoop_read_exclusive 644 # read snoops on exclusive blocks -system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks -system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks -system.cpu.icache.protocol.snoop_read_shared 1040 # read snoops on shared blocks -system.cpu.icache.protocol.snoop_readex_exclusive 146 # readEx snoops on exclusive blocks -system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks -system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks -system.cpu.icache.protocol.snoop_readex_shared 2 # readEx snoops on shared blocks -system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks -system.cpu.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks -system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks -system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks -system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks -system.cpu.icache.replacements 926519 # number of replacements -system.cpu.icache.sampled_refs 927030 # Sample count of references to valid blocks. +system.cpu.icache.replacements 927169 # number of replacements +system.cpu.icache.sampled_refs 927680 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 508.761542 # Cycle average of tags in use -system.cpu.icache.total_refs 59110217 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 34634685000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 508.749374 # Cycle average of tags in use +system.cpu.icache.total_refs 59106935 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 35000367000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.940784 # Percentage of idle cycles -system.cpu.itb.accesses 4977586 # ITB accesses +system.cpu.idle_fraction 0.939637 # Percentage of idle cycles +system.cpu.itb.accesses 4978395 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4972580 # ITB hits +system.cpu.itb.hits 4973389 # ITB hits system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192752 # number of callpals executed +system.cpu.kern.callpal 192813 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -224,50 +191,50 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 175824 91.22% 93.42% # number of callpals executed -system.cpu.kern.callpal_rdps 6824 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal_swpipl 175877 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal_rdps 6828 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal_rti 5148 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal_rti 5152 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211836 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211901 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6181 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183027 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74862 40.90% 40.90% # number of times we switched to this ipl +system.cpu.kern.ipl_count 183088 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74875 40.90% 40.90% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 131 0.07% 40.97% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1923 1.05% 42.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106111 57.98% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149044 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73495 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_22 1927 1.05% 42.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106155 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149074 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73508 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1923 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73495 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1907145727000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1851261210000 97.07% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 73754500 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 531976500 0.03% 97.10% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 55278786000 2.90% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981740 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good_22 1927 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73508 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1910308997000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1853401678500 97.02% 97.02% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 78202500 0.00% 97.03% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 538133000 0.03% 97.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 56290983000 2.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981743 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.692624 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1910 -system.cpu.kern.mode_good_user 1740 +system.cpu.kern.ipl_used_31 0.692459 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1908 +system.cpu.kern.mode_good_user 1738 system.cpu.kern.mode_good_idle 170 -system.cpu.kern.mode_switch_kernel 5894 # number of protection mode switches -system.cpu.kern.mode_switch_user 1740 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2096 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.405165 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.324058 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_kernel 5896 # number of protection mode switches +system.cpu.kern.mode_switch_user 1738 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2098 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.404639 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.323609 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 42657550000 2.24% 2.24% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 4648649000 0.24% 2.48% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1859839526000 97.52% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good_idle 0.081030 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 43115749000 2.26% 2.26% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 4716926000 0.25% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1862476320000 97.50% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -300,10 +267,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.059216 # Percentage of non-idle cycles -system.cpu.numCycles 1907146437000 # number of cpu cycles simulated -system.cpu.num_insts 60037406 # Number of instructions executed -system.cpu.num_refs 16305563 # Number of memory references +system.cpu.not_idle_fraction 0.060363 # Percentage of non-idle cycles +system.cpu.numCycles 1910309711000 # number of cpu cycles simulated +system.cpu.num_insts 60034774 # Number of instructions executed +system.cpu.num_refs 16305091 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -316,70 +283,79 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.l2c.ReadExReq_accesses 304305 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 13000.153945 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 11000.153945 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits 187380 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 1520043000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 0.384236 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 116925 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 1286193000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 0.384236 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 116925 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2668854 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 13000.065889 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 11000.065889 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits 1727874 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 12232802000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.352578 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 940980 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 10350842000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.352578 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 940980 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable -system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.l2c.ReadResp_mshr_uncacheable_latency 750102000 # number of ReadResp MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable -system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.l2c.WriteResp_mshr_uncacheable_latency 1050666000 # number of WriteResp MSHR uncacheable cycles -system.l2c.Writeback_accesses 429989 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 429989 # number of Writeback hits +system.l2c.ReadExReq_accesses 304522 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 12000.719160 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 11000.719160 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 3654483000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 304522 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 3349961000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 304522 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2670005 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 12000.233269 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 11000.233269 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits 1568273 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 13221041000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.412633 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 1101732 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 12119309000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.412633 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 1101732 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 750102000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 125867 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 11999.892744 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 11000.750793 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 1510390500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 125867 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 1384631500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 125867 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 1051110500 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 429991 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses +system.l2c.Writeback_misses 429991 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 429991 # number of Writeback MSHR misses system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 2.216875 # Average number of references to valid blocks. +system.l2c.avg_refs 1.660842 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2668854 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 13000.065889 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency -system.l2c.demand_hits 1727874 # number of demand (read+write) hits -system.l2c.demand_miss_latency 12232802000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.352578 # miss rate for demand accesses -system.l2c.demand_misses 940980 # number of demand (read+write) misses +system.l2c.demand_accesses 2974527 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 12000.338488 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 11000.338488 # average overall mshr miss latency +system.l2c.demand_hits 1568273 # number of demand (read+write) hits +system.l2c.demand_miss_latency 16875524000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.472766 # miss rate for demand accesses +system.l2c.demand_misses 1406254 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 10350842000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.352578 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 940980 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 15469270000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.472766 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 1406254 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3098843 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 13000.065889 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.l2c.overall_hits 2157863 # number of overall hits -system.l2c.overall_miss_latency 12232802000 # number of overall miss cycles -system.l2c.overall_miss_rate 0.303655 # miss rate for overall accesses -system.l2c.overall_misses 940980 # number of overall misses +system.l2c.overall_accesses 2974527 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 12000.338488 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 11000.338488 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits 1568273 # number of overall hits +system.l2c.overall_miss_latency 16875524000 # number of overall miss cycles +system.l2c.overall_miss_rate 0.472766 # miss rate for overall accesses +system.l2c.overall_misses 1406254 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 10350842000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.303655 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 940980 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_miss_latency 15469270000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.472766 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 1406254 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1801212500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -389,13 +365,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 992369 # number of replacements -system.l2c.sampled_refs 1057905 # Sample count of references to valid blocks. +system.l2c.replacements 947259 # number of replacements +system.l2c.sampled_refs 965538 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 65468.856552 # Cycle average of tags in use -system.l2c.total_refs 2345243 # Total number of references to valid blocks. -system.l2c.warmup_cycle 3045832000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 74072 # number of writebacks +system.l2c.tagsinuse 15874.904757 # Cycle average of tags in use +system.l2c.total_refs 1603606 # Total number of references to valid blocks. +system.l2c.warmup_cycle 4106790000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index f34493a86..32120d9d6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,3 +1,3 @@ -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index db9ad862d..69f3594a5 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 10 2007 14:10:03 -M5 started Mon Jun 11 01:14:34 2007 -M5 executing on iceaxe -command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +M5 compiled Aug 3 2007 04:02:11 +M5 started Fri Aug 3 04:23:34 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 1907146437000 because m5_exit instruction encountered +Exiting @ tick 1910309711000 because m5_exit instruction encountered |