diff options
| author | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
| commit | 374ba9bae359e68c1496f8db25c38a817af2da19 (patch) | |
| tree | 48fe4ae90f77f19aa6005fa5ec2426e836299bc9 /tests/quick/10.linux-boot | |
| parent | e0de2c34433be76eac7798e58e1ae02f5bffb732 (diff) | |
| download | gem5-374ba9bae359e68c1496f8db25c38a817af2da19.tar.xz | |
tests: update tests for TLB unification
Diffstat (limited to 'tests/quick/10.linux-boot')
12 files changed, 192 insertions, 96 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 56dec3815..ef33d965f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -97,7 +97,7 @@ cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.port[2] [system.cpu0.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu0.icache] @@ -136,7 +136,7 @@ mem_side=system.toL2Bus.port[1] type=AlphaInterrupts [system.cpu0.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu0.tracer] @@ -206,7 +206,7 @@ cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.port[4] [system.cpu1.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu1.icache] @@ -245,7 +245,7 @@ mem_side=system.toL2Bus.port[3] type=AlphaInterrupts [system.cpu1.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu1.tracer] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 8c40366bc..a95a79ffc 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:15:24 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:15:50 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +M5 compiled Apr 8 2009 12:30:02 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:30:04 +M5 executing on maize +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 8ed468432..a781e9d48 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2804596 # Simulator instruction rate (inst/s) -host_mem_usage 292704 # Number of bytes of host memory used -host_seconds 22.52 # Real time elapsed on the host -host_tick_rate 83058483755 # Simulator tick rate (ticks/s) +host_inst_rate 4473904 # Simulator instruction rate (inst/s) +host_mem_usage 294520 # Number of bytes of host memory used +host_seconds 14.12 # Real time elapsed on the host +host_tick_rate 132494065933 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated @@ -67,10 +67,14 @@ system.cpu0.dcache.tagsinuse 504.827058 # Cy system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 396793 # number of writebacks -system.cpu0.dtb.accesses 698037 # DTB accesses -system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15091429 # DTB hits -system.cpu0.dtb.misses 7805 # DTB misses +system.cpu0.dtb.data_accesses 698037 # DTB accesses +system.cpu0.dtb.data_acv 251 # DTB access violations +system.cpu0.dtb.data_hits 15091429 # DTB hits +system.cpu0.dtb.data_misses 7805 # DTB misses +system.cpu0.dtb.fetch_accesses 0 # ITB accesses +system.cpu0.dtb.fetch_acv 0 # ITB acv +system.cpu0.dtb.fetch_hits 0 # ITB hits +system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.read_accesses 508987 # DTB read accesses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_hits 9154530 # DTB read hits @@ -127,10 +131,22 @@ system.cpu0.icache.total_refs 56345132 # To system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles -system.cpu0.itb.accesses 3859041 # ITB accesses -system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3855556 # ITB hits -system.cpu0.itb.misses 3485 # ITB misses +system.cpu0.itb.data_accesses 0 # DTB accesses +system.cpu0.itb.data_acv 0 # DTB access violations +system.cpu0.itb.data_hits 0 # DTB hits +system.cpu0.itb.data_misses 0 # DTB misses +system.cpu0.itb.fetch_accesses 3859041 # ITB accesses +system.cpu0.itb.fetch_acv 127 # ITB acv +system.cpu0.itb.fetch_hits 3855556 # ITB hits +system.cpu0.itb.fetch_misses 3485 # ITB misses +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.read_acv 0 # DTB read access violations +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.write_acv 0 # DTB write access violations +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal 183291 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed @@ -283,10 +299,14 @@ system.cpu1.dcache.tagsinuse 391.951263 # Cy system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 30848 # number of writebacks -system.cpu1.dtb.accesses 323622 # DTB accesses -system.cpu1.dtb.acv 116 # DTB access violations -system.cpu1.dtb.hits 1914885 # DTB hits -system.cpu1.dtb.misses 3692 # DTB misses +system.cpu1.dtb.data_accesses 323622 # DTB accesses +system.cpu1.dtb.data_acv 116 # DTB access violations +system.cpu1.dtb.data_hits 1914885 # DTB hits +system.cpu1.dtb.data_misses 3692 # DTB misses +system.cpu1.dtb.fetch_accesses 0 # ITB accesses +system.cpu1.dtb.fetch_acv 0 # ITB acv +system.cpu1.dtb.fetch_hits 0 # ITB hits +system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.read_accesses 220342 # DTB read accesses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_hits 1163439 # DTB read hits @@ -343,10 +363,22 @@ system.cpu1.icache.total_refs 5832136 # To system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles -system.cpu1.itb.accesses 1469938 # ITB accesses -system.cpu1.itb.acv 57 # ITB acv -system.cpu1.itb.hits 1468399 # ITB hits -system.cpu1.itb.misses 1539 # ITB misses +system.cpu1.itb.data_accesses 0 # DTB accesses +system.cpu1.itb.data_acv 0 # DTB access violations +system.cpu1.itb.data_hits 0 # DTB hits +system.cpu1.itb.data_misses 0 # DTB misses +system.cpu1.itb.fetch_accesses 1469938 # ITB accesses +system.cpu1.itb.fetch_acv 57 # ITB acv +system.cpu1.itb.fetch_hits 1468399 # ITB hits +system.cpu1.itb.fetch_misses 1539 # ITB misses +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.read_acv 0 # DTB read access violations +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.write_acv 0 # DTB write access violations +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal 32131 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 15e3ec649..511baadf2 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -97,7 +97,7 @@ cpu_side=system.cpu.dcache_port mem_side=system.toL2Bus.port[2] [system.cpu.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu.icache] @@ -136,7 +136,7 @@ mem_side=system.toL2Bus.port[1] type=AlphaInterrupts [system.cpu.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu.tracer] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 778e7a3b4..b5820599c 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:15:24 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:15:52 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +M5 compiled Apr 8 2009 12:30:02 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:30:05 +M5 executing on maize +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 749efa0bc..9c2b9013b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2844723 # Simulator instruction rate (inst/s) -host_mem_usage 291452 # Number of bytes of host memory used -host_seconds 21.11 # Real time elapsed on the host -host_tick_rate 86676065750 # Simulator tick rate (ticks/s) +host_inst_rate 4520875 # Simulator instruction rate (inst/s) +host_mem_usage 293196 # Number of bytes of host memory used +host_seconds 13.28 # Real time elapsed on the host +host_tick_rate 137745560508 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated @@ -67,10 +67,14 @@ system.cpu.dcache.tagsinuse 511.997802 # Cy system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 428893 # number of writebacks -system.cpu.dtb.accesses 1020787 # DTB accesses -system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16062925 # DTB hits -system.cpu.dtb.misses 11471 # DTB misses +system.cpu.dtb.data_accesses 1020787 # DTB accesses +system.cpu.dtb.data_acv 367 # DTB access violations +system.cpu.dtb.data_hits 16062925 # DTB hits +system.cpu.dtb.data_misses 11471 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_hits 9710427 # DTB read hits @@ -127,10 +131,22 @@ system.cpu.icache.total_refs 59129922 # To system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0.983585 # Percentage of idle cycles -system.cpu.itb.accesses 4979654 # ITB accesses -system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974648 # ITB hits -system.cpu.itb.misses 5006 # ITB misses +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 4979654 # ITB accesses +system.cpu.itb.fetch_acv 184 # ITB acv +system.cpu.itb.fetch_hits 4974648 # ITB hits +system.cpu.itb.fetch_misses 5006 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses system.cpu.kern.callpal 192180 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index f8e47e1b8..97b65b05c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -94,7 +94,7 @@ cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.port[2] [system.cpu0.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu0.icache] @@ -133,7 +133,7 @@ mem_side=system.toL2Bus.port[1] type=AlphaInterrupts [system.cpu0.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu0.tracer] @@ -200,7 +200,7 @@ cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.port[4] [system.cpu1.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu1.icache] @@ -239,7 +239,7 @@ mem_side=system.toL2Bus.port[3] type=AlphaInterrupts [system.cpu1.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu1.tracer] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 6b56db972..3ba004aee 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:15:24 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:15:51 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +M5 compiled Apr 8 2009 12:30:02 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:30:05 +M5 executing on maize +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 4a6754053..fa370386c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1382701 # Simulator instruction rate (inst/s) -host_mem_usage 289788 # Number of bytes of host memory used -host_seconds 42.97 # Real time elapsed on the host -host_tick_rate 45890646030 # Simulator tick rate (ticks/s) +host_inst_rate 2075727 # Simulator instruction rate (inst/s) +host_mem_usage 291612 # Number of bytes of host memory used +host_seconds 28.63 # Real time elapsed on the host +host_tick_rate 68891569254 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59420593 # Number of instructions simulated sim_seconds 1.972135 # Number of seconds simulated @@ -95,10 +95,14 @@ system.cpu0.dcache.tagsinuse 503.609177 # Cy system.cpu0.dcache.total_refs 13378935 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 403520 # number of writebacks -system.cpu0.dtb.accesses 719860 # DTB accesses -system.cpu0.dtb.acv 289 # DTB access violations -system.cpu0.dtb.hits 14704826 # DTB hits -system.cpu0.dtb.misses 8485 # DTB misses +system.cpu0.dtb.data_accesses 719860 # DTB accesses +system.cpu0.dtb.data_acv 289 # DTB access violations +system.cpu0.dtb.data_hits 14704826 # DTB hits +system.cpu0.dtb.data_misses 8485 # DTB misses +system.cpu0.dtb.fetch_accesses 0 # ITB accesses +system.cpu0.dtb.fetch_acv 0 # ITB acv +system.cpu0.dtb.fetch_hits 0 # ITB hits +system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.read_accesses 524201 # DTB read accesses system.cpu0.dtb.read_acv 174 # DTB read access violations system.cpu0.dtb.read_hits 8664724 # DTB read hits @@ -161,10 +165,22 @@ system.cpu0.icache.total_refs 53248092 # To system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks system.cpu0.idle_fraction 0.933160 # Percentage of idle cycles -system.cpu0.itb.accesses 3953747 # ITB accesses -system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 3949906 # ITB hits -system.cpu0.itb.misses 3841 # ITB misses +system.cpu0.itb.data_accesses 0 # DTB accesses +system.cpu0.itb.data_acv 0 # DTB access violations +system.cpu0.itb.data_hits 0 # DTB hits +system.cpu0.itb.data_misses 0 # DTB misses +system.cpu0.itb.fetch_accesses 3953747 # ITB accesses +system.cpu0.itb.fetch_acv 143 # ITB acv +system.cpu0.itb.fetch_hits 3949906 # ITB hits +system.cpu0.itb.fetch_misses 3841 # ITB misses +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.read_acv 0 # DTB read access violations +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.write_acv 0 # DTB write access violations +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal 188012 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed @@ -345,10 +361,14 @@ system.cpu1.dcache.tagsinuse 388.878897 # Cy system.cpu1.dcache.total_refs 1631272 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1954643578000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 26831 # number of writebacks -system.cpu1.dtb.accesses 302878 # DTB accesses -system.cpu1.dtb.acv 84 # DTB access violations -system.cpu1.dtb.hits 1693851 # DTB hits -system.cpu1.dtb.misses 3106 # DTB misses +system.cpu1.dtb.data_accesses 302878 # DTB accesses +system.cpu1.dtb.data_acv 84 # DTB access violations +system.cpu1.dtb.data_hits 1693851 # DTB hits +system.cpu1.dtb.data_misses 3106 # DTB misses +system.cpu1.dtb.fetch_accesses 0 # ITB accesses +system.cpu1.dtb.fetch_acv 0 # ITB acv +system.cpu1.dtb.fetch_hits 0 # ITB hits +system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.read_accesses 205838 # DTB read accesses system.cpu1.dtb.read_acv 36 # DTB read access violations system.cpu1.dtb.read_hits 1029710 # DTB read hits @@ -411,10 +431,22 @@ system.cpu1.icache.total_refs 5180706 # To system.cpu1.icache.warmup_cycle 1967880295000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles -system.cpu1.itb.accesses 1397517 # ITB accesses -system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 1396271 # ITB hits -system.cpu1.itb.misses 1246 # ITB misses +system.cpu1.itb.data_accesses 0 # DTB accesses +system.cpu1.itb.data_acv 0 # DTB access violations +system.cpu1.itb.data_hits 0 # DTB hits +system.cpu1.itb.data_misses 0 # DTB misses +system.cpu1.itb.fetch_accesses 1397517 # ITB accesses +system.cpu1.itb.fetch_acv 41 # ITB acv +system.cpu1.itb.fetch_hits 1396271 # ITB hits +system.cpu1.itb.fetch_misses 1246 # ITB misses +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.read_acv 0 # DTB read access violations +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.write_acv 0 # DTB write access violations +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal 29503 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 468bf0248..a7d96b196 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -94,7 +94,7 @@ cpu_side=system.cpu.dcache_port mem_side=system.toL2Bus.port[2] [system.cpu.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu.icache] @@ -133,7 +133,7 @@ mem_side=system.toL2Bus.port[1] type=AlphaInterrupts [system.cpu.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu.tracer] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index ba86a45b9..0edc8e974 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:15:24 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:15:52 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +M5 compiled Apr 8 2009 12:30:02 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:30:04 +M5 executing on maize +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index cbf231e85..7b42fa0e8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1953289 # Simulator instruction rate (inst/s) -host_mem_usage 288556 # Number of bytes of host memory used -host_seconds 28.78 # Real time elapsed on the host -host_tick_rate 67077404616 # Simulator tick rate (ticks/s) +host_inst_rate 2046881 # Simulator instruction rate (inst/s) +host_mem_usage 290296 # Number of bytes of host memory used +host_seconds 27.46 # Real time elapsed on the host +host_tick_rate 70291420604 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56205703 # Number of instructions simulated sim_seconds 1.930165 # Number of seconds simulated @@ -95,10 +95,14 @@ system.cpu.dcache.tagsinuse 511.984142 # Cy system.cpu.dcache.total_refs 14056658 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 430459 # number of writebacks -system.cpu.dtb.accesses 1020784 # DTB accesses -system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 15429793 # DTB hits -system.cpu.dtb.misses 11466 # DTB misses +system.cpu.dtb.data_accesses 1020784 # DTB accesses +system.cpu.dtb.data_acv 367 # DTB access violations +system.cpu.dtb.data_hits 15429793 # DTB hits +system.cpu.dtb.data_misses 11466 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.read_accesses 728853 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_hits 9069700 # DTB read hits @@ -161,10 +165,22 @@ system.cpu.icache.total_refs 55286436 # To system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0.929209 # Percentage of idle cycles -system.cpu.itb.accesses 4982987 # ITB accesses -system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4977977 # ITB hits -system.cpu.itb.misses 5010 # ITB misses +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 4982987 # ITB accesses +system.cpu.itb.fetch_acv 184 # ITB acv +system.cpu.itb.fetch_hits 4977977 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses system.cpu.kern.callpal 193221 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed |