diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-04 20:38:28 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-04 20:38:28 -0500 |
| commit | fea2c26402894aa26de7b7d8e14fe71070b76296 (patch) | |
| tree | e0fda155959ce40d9528ef511c47ee851de516fb /tests/quick/10.linux-boot | |
| parent | cefd6960e5312c27b613dcb783c66539baa0307d (diff) | |
| download | gem5-fea2c26402894aa26de7b7d8e14fe71070b76296.tar.xz | |
ARM: Update ARM_FS stats for mp changes
Diffstat (limited to 'tests/quick/10.linux-boot')
8 files changed, 398 insertions, 380 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 22389fff7..c163a5ab4 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -9,12 +9,17 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 +boot_loader= +boot_loader_mem=Null boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0 +flags_addr=0 +gic_cpu_addr=0 init_param=0 kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic +midr_regval=890236928 physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -221,7 +226,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.port[25] -mem_side=system.membus.port[5] +mem_side=system.membus.port[6] [system.l2c] type=BaseCache @@ -253,7 +258,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.port[0] -mem_side=system.membus.port[6] +mem_side=system.membus.port[7] [system.membus] type=Bus @@ -265,7 +270,7 @@ header_cycles=1 use_default_range=false width=64 default=system.membus.badaddr_responder.pio -port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side +port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -295,10 +300,18 @@ port=system.membus.port[2] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system +[system.realview.a9scu] +type=A9SCU +pio_addr=520093696 +pio_latency=1000 +platform=system.realview +system=system +pio=system.membus.port[5] + [system.realview.aaci_fake] type=AmbaFake amba_id=0 @@ -395,7 +408,7 @@ pio=system.iobus.port[9] type=IsaFake pio_addr=1073741824 pio_latency=1000 -pio_size=67108864 +pio_size=536870912 platform=system.realview ret_bad_addr=false ret_data16=65535 @@ -413,6 +426,7 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +int_latency=10000 it_lines=128 platform=system.realview system=system @@ -504,6 +518,7 @@ pio=system.iobus.port[22] [system.realview.realview_io] type=RealViewCtrl +idreg=0 pio_addr=268435456 pio_latency=1000 platform=system.realview diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr index 63ac398c9..a758a5804 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr @@ -8,16 +8,12 @@ warn: The clidr register always reports 0 caches. For more information see: http://www.m5sim.org/warn/23a3c326 warn: The csselr register isn't implemented. For more information see: http://www.m5sim.org/warn/c0c486b8 -warn: Need to flush all TLBs in MP -For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: The ccsidr register isn't implemented and always reads as 0. For more information see: http://www.m5sim.org/warn/2c4acb9c warn: instruction 'mcr dccimvac' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb -warn: Need to flush all TLBs in MP -For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr dccmvau' unimplemented @@ -34,8 +30,6 @@ warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb -warn: Need to flush all TLBs in MP -For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 6553d17c6..ccb811098 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 1 2011 21:51:08 -M5 started May 1 2011 21:51:14 +M5 compiled May 2 2011 15:06:32 +M5 started May 2 2011 15:06:36 M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 26341084000 because m5_exit instruction encountered +Exiting @ tick 26344863500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 9bbce3daa..4bee82022 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1460315 # Simulator instruction rate (inst/s) -host_mem_usage 380976 # Number of bytes of host memory used -host_seconds 35.59 # Real time elapsed on the host -host_tick_rate 740141754 # Simulator tick rate (ticks/s) +host_inst_rate 2974441 # Simulator instruction rate (inst/s) +host_mem_usage 381360 # Number of bytes of host memory used +host_seconds 17.48 # Real time elapsed on the host +host_tick_rate 1507548482 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 51971087 # Number of instructions simulated -sim_seconds 0.026341 # Number of seconds simulated -sim_ticks 26341084000 # Number of ticks simulated +sim_insts 51978646 # Number of instructions simulated +sim_seconds 0.026345 # Number of seconds simulated +sim_ticks 26344863500 # Number of ticks simulated system.cpu.dcache.LoadLockedReq_accesses::0 100443 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 100443 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits::0 95328 # number of LoadLockedReq hits @@ -15,49 +15,49 @@ system.cpu.dcache.LoadLockedReq_hits::total 95328 # system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050924 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses::0 5115 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5115 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses::0 7807332 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7807332 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits::0 7570991 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7570991 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate::0 0.030272 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 236341 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 236341 # number of ReadReq misses +system.cpu.dcache.ReadReq_accesses::0 7808976 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7808976 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::0 7572677 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7572677 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate::0 0.030260 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 236299 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 236299 # number of ReadReq misses system.cpu.dcache.StoreCondReq_accesses::0 100442 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 100442 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_hits::0 100442 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 100442 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6662917 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6662917 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits::0 6490820 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6490820 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate::0 0.025829 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 172097 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 172097 # number of WriteReq misses +system.cpu.dcache.WriteReq_accesses::0 6664019 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6664019 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::0 6491936 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6491936 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.025823 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172083 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172083 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.634545 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.645976 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14470249 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14472995 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14470249 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 14472995 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14061811 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 14064613 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14061811 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 14064613 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028226 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.028217 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 408438 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 408382 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 408438 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 408382 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -67,26 +67,26 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 511.736543 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999485 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses::0 14470249 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 511.736581 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999486 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses::0 14472995 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14470249 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 14472995 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14061811 # number of overall hits +system.cpu.dcache.overall_hits::0 14064613 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14061811 # number of overall hits +system.cpu.dcache.overall_hits::total 14064613 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028226 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.028217 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 408438 # number of overall misses +system.cpu.dcache.overall_misses::0 408382 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 408438 # number of overall misses +system.cpu.dcache.overall_misses::total 408382 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -95,14 +95,14 @@ system.cpu.dcache.overall_mshr_miss_rate::total no_value system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 411199 # number of replacements -system.cpu.dcache.sampled_refs 411711 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 411144 # number of replacements +system.cpu.dcache.sampled_refs 411656 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.736543 # Cycle average of tags in use -system.cpu.dcache.total_refs 14259423 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.736581 # Cycle average of tags in use +system.cpu.dcache.total_refs 14262224 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21760500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 380342 # number of writebacks -system.cpu.dtb.accesses 15494791 # DTB accesses +system.cpu.dcache.writebacks 380291 # number of writebacks +system.cpu.dtb.accesses 15497629 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 2239 # Number of entries that have been flushed from TLB @@ -110,51 +110,51 @@ system.cpu.dtb.flush_tlb 2 # Nu system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15489154 # DTB hits +system.cpu.dtb.hits 15491993 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5637 # DTB misses +system.cpu.dtb.misses 5636 # DTB misses system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 787 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8719654 # DTB read accesses -system.cpu.dtb.read_hits 8715002 # DTB read hits -system.cpu.dtb.read_misses 4652 # DTB read misses -system.cpu.dtb.write_accesses 6775137 # DTB write accesses -system.cpu.dtb.write_hits 6774152 # DTB write hits +system.cpu.dtb.read_accesses 8721338 # DTB read accesses +system.cpu.dtb.read_hits 8716687 # DTB read hits +system.cpu.dtb.read_misses 4651 # DTB read misses +system.cpu.dtb.write_accesses 6776291 # DTB write accesses +system.cpu.dtb.write_hits 6775306 # DTB write hits system.cpu.dtb.write_misses 985 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41451981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41451981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits::0 41019813 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41019813 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate::0 0.010426 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 432168 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 432168 # number of ReadReq misses +system.cpu.icache.ReadReq_accesses::0 41456992 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41456992 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits::0 41024796 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41024796 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate::0 0.010425 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 432196 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 432196 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.916579 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.921959 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41451981 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41456992 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41451981 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41456992 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.demand_hits::0 41019813 # number of demand (read+write) hits +system.cpu.icache.demand_hits::0 41024796 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41019813 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41024796 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010426 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::0 0.010425 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 432168 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 432196 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 432168 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 432196 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -164,26 +164,26 @@ system.cpu.icache.demand_mshr_misses 0 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 476.338478 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.930349 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses::0 41451981 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 476.343594 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.930359 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses::0 41456992 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41451981 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41456992 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 41019813 # number of overall hits +system.cpu.icache.overall_hits::0 41024796 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 41019813 # number of overall hits +system.cpu.icache.overall_hits::total 41024796 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010426 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.010425 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 432168 # number of overall misses +system.cpu.icache.overall_misses::0 432196 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 432168 # number of overall misses +system.cpu.icache.overall_misses::total 432196 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -192,15 +192,15 @@ system.cpu.icache.overall_mshr_miss_rate::total no_value system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 431655 # number of replacements -system.cpu.icache.sampled_refs 432167 # Sample count of references to valid blocks. +system.cpu.icache.replacements 431683 # number of replacements +system.cpu.icache.sampled_refs 432195 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 476.338478 # Cycle average of tags in use -system.cpu.icache.total_refs 41019813 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 476.343594 # Cycle average of tags in use +system.cpu.icache.total_refs 41024796 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 4572561500 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 33762 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41453108 # DTB accesses +system.cpu.itb.accesses 41458119 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB @@ -208,9 +208,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41450178 # DTB hits -system.cpu.itb.inst_accesses 41453108 # ITB inst accesses -system.cpu.itb.inst_hits 41450178 # ITB inst hits +system.cpu.itb.hits 41455189 # DTB hits +system.cpu.itb.inst_accesses 41458119 # ITB inst accesses +system.cpu.itb.inst_hits 41455189 # ITB inst hits system.cpu.itb.inst_misses 2930 # ITB inst misses system.cpu.itb.misses 2930 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -224,25 +224,25 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 52682169 # number of cpu cycles simulated +system.cpu.numCycles 52689728 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 52682169 # Number of busy cycles -system.cpu.num_conditional_control_insts 7011337 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 52689728 # Number of busy cycles +system.cpu.num_conditional_control_insts 7011782 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses system.cpu.num_fp_insts 6058 # number of float instructions system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written -system.cpu.num_func_calls 1107940 # number of times a function call or return occured +system.cpu.num_func_calls 1108496 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 51971087 # Number of instructions executed -system.cpu.num_int_alu_accesses 42400620 # Number of integer alu accesses -system.cpu.num_int_insts 42400620 # number of integer instructions -system.cpu.num_int_register_reads 130759048 # number of times the integer registers were read -system.cpu.num_int_register_writes 34454879 # number of times the integer registers were written -system.cpu.num_load_insts 9174729 # Number of load instructions -system.cpu.num_mem_refs 16247961 # number of memory refs -system.cpu.num_store_insts 7073232 # Number of store instructions +system.cpu.num_insts 51978646 # Number of instructions executed +system.cpu.num_int_alu_accesses 42407849 # Number of integer alu accesses +system.cpu.num_int_insts 42407849 # number of integer instructions +system.cpu.num_int_register_reads 130779000 # number of times the integer registers were read +system.cpu.num_int_register_writes 34467088 # number of times the integer registers were written +system.cpu.num_load_insts 9176676 # Number of load instructions +system.cpu.num_mem_refs 16251075 # number of memory refs +system.cpu.num_store_insts 7074399 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -310,61 +310,61 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.ReadExReq_accesses::0 170255 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 170255 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_hits::0 60589 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60589 # number of ReadExReq hits -system.l2c.ReadExReq_miss_rate::0 0.644128 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 109666 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 109666 # number of ReadExReq misses -system.l2c.ReadReq_accesses::0 671527 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 7078 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 678605 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 650296 # number of ReadReq hits -system.l2c.ReadReq_hits::1 7047 # number of ReadReq hits -system.l2c.ReadReq_hits::total 657343 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.031616 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.004380 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.035996 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 21231 # number of ReadReq misses +system.l2c.ReadExReq_accesses::0 170242 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170242 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits::0 60575 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60575 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.644183 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 109667 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 109667 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 671513 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 7076 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 678589 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 650281 # number of ReadReq hits +system.l2c.ReadReq_hits::1 7045 # number of ReadReq hits +system.l2c.ReadReq_hits::total 657326 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.031618 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.004381 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.035999 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 21232 # number of ReadReq misses system.l2c.ReadReq_misses::1 31 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21262 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 1842 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1842 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadReq_misses::total 21263 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 1841 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1841 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_hits::0 19 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 19 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_rate::0 0.989685 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1823 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1823 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 414104 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 414104 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 414104 # number of Writeback hits -system.l2c.Writeback_hits::total 414104 # number of Writeback hits +system.l2c.UpgradeReq_miss_rate::0 0.989680 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 414053 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 414053 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 414053 # number of Writeback hits +system.l2c.Writeback_hits::total 414053 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.723520 # Average number of references to valid blocks. +system.l2c.avg_refs 6.728889 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 841782 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 7078 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 848860 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 841755 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 7076 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 848831 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 710885 # number of demand (read+write) hits -system.l2c.demand_hits::1 7047 # number of demand (read+write) hits -system.l2c.demand_hits::total 717932 # number of demand (read+write) hits +system.l2c.demand_hits::0 710856 # number of demand (read+write) hits +system.l2c.demand_hits::1 7045 # number of demand (read+write) hits +system.l2c.demand_hits::total 717901 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.155500 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.004380 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.159880 # miss rate for demand accesses -system.l2c.demand_misses::0 130897 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.155507 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.004381 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.159888 # miss rate for demand accesses +system.l2c.demand_misses::0 130899 # number of demand (read+write) misses system.l2c.demand_misses::1 31 # number of demand (read+write) misses -system.l2c.demand_misses::total 130928 # number of demand (read+write) misses +system.l2c.demand_misses::total 130930 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -374,28 +374,28 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 5062.788087 # Average occupied blocks per context -system.l2c.occ_blocks::1 31189.705520 # Average occupied blocks per context -system.l2c.occ_percent::0 0.077252 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.475917 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 841782 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 7078 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 848860 # number of overall (read+write) accesses +system.l2c.occ_blocks::0 5062.983429 # Average occupied blocks per context +system.l2c.occ_blocks::1 31189.392245 # Average occupied blocks per context +system.l2c.occ_percent::0 0.077255 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.475912 # Average percentage of cache occupancy +system.l2c.overall_accesses::0 841755 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 7076 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 848831 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 710885 # number of overall hits -system.l2c.overall_hits::1 7047 # number of overall hits -system.l2c.overall_hits::total 717932 # number of overall hits +system.l2c.overall_hits::0 710856 # number of overall hits +system.l2c.overall_hits::1 7045 # number of overall hits +system.l2c.overall_hits::total 717901 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.155500 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.004380 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.159880 # miss rate for overall accesses -system.l2c.overall_misses::0 130897 # number of overall misses +system.l2c.overall_miss_rate::0 0.155507 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.004381 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.159888 # miss rate for overall accesses +system.l2c.overall_misses::0 130899 # number of overall misses system.l2c.overall_misses::1 31 # number of overall misses -system.l2c.overall_misses::total 130928 # number of overall misses +system.l2c.overall_misses::total 130930 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -405,11 +405,11 @@ system.l2c.overall_mshr_misses 0 # nu system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 97110 # number of replacements -system.l2c.sampled_refs 129684 # Sample count of references to valid blocks. +system.l2c.sampled_refs 129685 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36252.493607 # Cycle average of tags in use -system.l2c.total_refs 871933 # Total number of references to valid blocks. +system.l2c.tagsinuse 36252.375674 # Cycle average of tags in use +system.l2c.total_refs 872636 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 91106 # number of writebacks +system.l2c.writebacks 91105 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 5e47cea73..8d1301d9c 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -9,12 +9,17 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 +boot_loader= +boot_loader_mem=Null boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0 +flags_addr=0 +gic_cpu_addr=0 init_param=0 kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing +midr_regval=890236928 physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -218,7 +223,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.port[25] -mem_side=system.membus.port[5] +mem_side=system.membus.port[6] [system.l2c] type=BaseCache @@ -250,7 +255,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.port[0] -mem_side=system.membus.port[6] +mem_side=system.membus.port[7] [system.membus] type=Bus @@ -262,7 +267,7 @@ header_cycles=1 use_default_range=false width=64 default=system.membus.badaddr_responder.pio -port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side +port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -292,10 +297,18 @@ port=system.membus.port[2] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system +[system.realview.a9scu] +type=A9SCU +pio_addr=520093696 +pio_latency=1000 +platform=system.realview +system=system +pio=system.membus.port[5] + [system.realview.aaci_fake] type=AmbaFake amba_id=0 @@ -392,7 +405,7 @@ pio=system.iobus.port[9] type=IsaFake pio_addr=1073741824 pio_latency=1000 -pio_size=67108864 +pio_size=536870912 platform=system.realview ret_bad_addr=false ret_data16=65535 @@ -410,6 +423,7 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +int_latency=10000 it_lines=128 platform=system.realview system=system @@ -501,6 +515,7 @@ pio=system.iobus.port[22] [system.realview.realview_io] type=RealViewCtrl +idreg=0 pio_addr=268435456 pio_latency=1000 platform=system.realview diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index 63ac398c9..a758a5804 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -8,16 +8,12 @@ warn: The clidr register always reports 0 caches. For more information see: http://www.m5sim.org/warn/23a3c326 warn: The csselr register isn't implemented. For more information see: http://www.m5sim.org/warn/c0c486b8 -warn: Need to flush all TLBs in MP -For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: The ccsidr register isn't implemented and always reads as 0. For more information see: http://www.m5sim.org/warn/2c4acb9c warn: instruction 'mcr dccimvac' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb -warn: Need to flush all TLBs in MP -For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr dccmvau' unimplemented @@ -34,8 +30,6 @@ warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb -warn: Need to flush all TLBs in MP -For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index c0358507b..e8aae375a 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 1 2011 21:51:08 -M5 started May 1 2011 21:51:14 +M5 compiled May 2 2011 15:06:32 +M5 started May 2 2011 15:06:36 M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 114293937000 because m5_exit instruction encountered +Exiting @ tick 114316622000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 1c9e3b842..5aad94f8d 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 703032 # Simulator instruction rate (inst/s) -host_mem_usage 381000 # Number of bytes of host memory used -host_seconds 72.76 # Real time elapsed on the host -host_tick_rate 1570917363 # Simulator tick rate (ticks/s) +host_inst_rate 1535776 # Simulator instruction rate (inst/s) +host_mem_usage 381388 # Number of bytes of host memory used +host_seconds 33.31 # Real time elapsed on the host +host_tick_rate 3431474709 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 51149744 # Number of instructions simulated -sim_seconds 0.114294 # Number of seconds simulated -sim_ticks 114293937000 # Number of ticks simulated +sim_insts 51162775 # Number of instructions simulated +sim_seconds 0.114317 # Number of seconds simulated +sim_ticks 114316622000 # Number of ticks simulated system.cpu.dcache.LoadLockedReq_accesses::0 100301 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 100301 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14594.610314 # average LoadLockedReq miss latency @@ -25,118 +25,118 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051425 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 5158 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 7812826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7812826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 15651.475503 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses::0 7815759 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7815759 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15651.214184 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12651.150503 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12650.891296 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7574365 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7574365 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3732266500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.030522 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 238461 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 238461 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3016806000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030522 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7577286 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7577286 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3732392000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.030512 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 238473 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 238473 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3016896000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030512 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 238461 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38192110000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_misses 238473 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38196735000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.StoreCondReq_accesses::0 100300 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 100300 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_hits::0 100300 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 100300 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6665523 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6665523 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 40729.480776 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses::0 6667481 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6667481 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 40727.618008 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37729.274596 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37727.411843 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 6493343 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493343 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7012802000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.025831 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 172180 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 172180 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 6496226500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025831 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 6495289 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6495289 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7012970000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.025826 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172192 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172192 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 6496358500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025826 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 172180 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_misses 172192 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 931126000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.459827 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.469586 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14478349 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14483240 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14478349 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26166.574940 # average overall miss latency +system.cpu.dcache.demand_accesses::total 14483240 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26165.760413 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23166.299761 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14067708 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23165.486467 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 14072575 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14067708 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10745068500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028362 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 14072575 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10745362000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028354 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 410641 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 410665 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 410641 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 410665 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9513032500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.028362 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 9513254500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.028354 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 410641 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 410665 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 509.188646 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994509 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses::0 14478349 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 509.189203 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994510 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses::0 14483240 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14478349 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26166.574940 # average overall miss latency +system.cpu.dcache.overall_accesses::total 14483240 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26165.760413 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23166.299761 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23165.486467 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14067708 # number of overall hits +system.cpu.dcache.overall_hits::0 14072575 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14067708 # number of overall hits -system.cpu.dcache.overall_miss_latency 10745068500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028362 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 14072575 # number of overall hits +system.cpu.dcache.overall_miss_latency 10745362000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028354 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 410641 # number of overall misses +system.cpu.dcache.overall_misses::0 410665 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 410641 # number of overall misses +system.cpu.dcache.overall_misses::total 410665 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9513032500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.028362 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 9513254500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.028354 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 410641 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39119916000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 410665 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39127861000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 413448 # number of replacements -system.cpu.dcache.sampled_refs 413960 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 413472 # number of replacements +system.cpu.dcache.sampled_refs 413984 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 509.188646 # Cycle average of tags in use -system.cpu.dcache.total_refs 14264990 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 509.189203 # Cycle average of tags in use +system.cpu.dcache.total_refs 14269857 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 382785 # number of writebacks -system.cpu.dtb.accesses 15507021 # DTB accesses +system.cpu.dcache.writebacks 382812 # number of writebacks +system.cpu.dtb.accesses 15512082 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 2208 # Number of entries that have been flushed from TLB @@ -144,109 +144,109 @@ system.cpu.dtb.flush_tlb 2 # Nu system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15501368 # DTB hits +system.cpu.dtb.hits 15506431 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5653 # DTB misses +system.cpu.dtb.misses 5651 # DTB misses system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 801 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8728602 # DTB read accesses -system.cpu.dtb.read_hits 8723916 # DTB read hits -system.cpu.dtb.read_misses 4686 # DTB read misses -system.cpu.dtb.write_accesses 6778419 # DTB write accesses -system.cpu.dtb.write_hits 6777452 # DTB write hits +system.cpu.dtb.read_accesses 8731607 # DTB read accesses +system.cpu.dtb.read_hits 8726923 # DTB read hits +system.cpu.dtb.read_misses 4684 # DTB read misses +system.cpu.dtb.write_accesses 6780475 # DTB write accesses +system.cpu.dtb.write_hits 6779508 # DTB write hits system.cpu.dtb.write_misses 967 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41474839 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41474839 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14791.660330 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses::0 41483736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41483736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14791.732049 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11790.344583 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11790.415195 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 41040865 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41040865 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6419196000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.010464 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 433974 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433974 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 5116703000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010464 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 41049747 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41049747 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6419449000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.010462 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 433989 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 433989 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 5116910500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010462 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 433974 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 433989 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.569871 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.587068 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41474839 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41483736 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41474839 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14791.660330 # average overall miss latency +system.cpu.icache.demand_accesses::total 41483736 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14791.732049 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11790.344583 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 41040865 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11790.415195 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 41049747 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41040865 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6419196000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010464 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 41049747 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6419449000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010462 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 433974 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 433989 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433974 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 433989 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 5116703000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.010464 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 5116910500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.010462 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 433974 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 433989 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 484.306355 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.945911 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses::0 41474839 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 484.311851 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.945922 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses::0 41483736 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41474839 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14791.660330 # average overall miss latency +system.cpu.icache.overall_accesses::total 41483736 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14791.732049 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11790.344583 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11790.415195 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 41040865 # number of overall hits +system.cpu.icache.overall_hits::0 41049747 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 41040865 # number of overall hits -system.cpu.icache.overall_miss_latency 6419196000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010464 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 41049747 # number of overall hits +system.cpu.icache.overall_miss_latency 6419449000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010462 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 433974 # number of overall misses +system.cpu.icache.overall_misses::0 433989 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 433974 # number of overall misses +system.cpu.icache.overall_misses::total 433989 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 5116703000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.010464 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 5116910500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.010462 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 433974 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 433989 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 433462 # number of replacements -system.cpu.icache.sampled_refs 433974 # Sample count of references to valid blocks. +system.cpu.icache.replacements 433477 # number of replacements +system.cpu.icache.sampled_refs 433989 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 484.306355 # Cycle average of tags in use -system.cpu.icache.total_refs 41040865 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 484.311851 # Cycle average of tags in use +system.cpu.icache.total_refs 41049747 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 14247556000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 34334 # number of writebacks +system.cpu.icache.writebacks 34328 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41477769 # DTB accesses +system.cpu.itb.accesses 41486666 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB @@ -254,9 +254,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41474839 # DTB hits -system.cpu.itb.inst_accesses 41477769 # ITB inst accesses -system.cpu.itb.inst_hits 41474839 # ITB inst hits +system.cpu.itb.hits 41483736 # DTB hits +system.cpu.itb.inst_accesses 41486666 # ITB inst accesses +system.cpu.itb.inst_hits 41483736 # ITB inst hits system.cpu.itb.inst_misses 2930 # ITB inst misses system.cpu.itb.misses 2930 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -270,25 +270,25 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 228587874 # number of cpu cycles simulated +system.cpu.numCycles 228633244 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 228587874 # Number of busy cycles -system.cpu.num_conditional_control_insts 7014796 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 228633244 # Number of busy cycles +system.cpu.num_conditional_control_insts 7015568 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses system.cpu.num_fp_insts 6058 # number of float instructions system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written -system.cpu.num_func_calls 1108768 # number of times a function call or return occured +system.cpu.num_func_calls 1109778 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 51149744 # Number of instructions executed -system.cpu.num_int_alu_accesses 42422684 # Number of integer alu accesses -system.cpu.num_int_insts 42422684 # number of integer instructions -system.cpu.num_int_register_reads 139100376 # number of times the integer registers were read -system.cpu.num_int_register_writes 34478872 # number of times the integer registers were written -system.cpu.num_load_insts 9179491 # Number of load instructions -system.cpu.num_mem_refs 16255504 # number of memory refs -system.cpu.num_store_insts 7076013 # Number of store instructions +system.cpu.num_insts 51162775 # Number of instructions executed +system.cpu.num_int_alu_accesses 42435662 # Number of integer alu accesses +system.cpu.num_int_insts 42435662 # number of integer instructions +system.cpu.num_int_register_reads 139138635 # number of times the integer registers were read +system.cpu.num_int_register_writes 34495190 # number of times the integer registers were written +system.cpu.num_load_insts 9182978 # Number of load instructions +system.cpu.num_mem_refs 16261071 # number of memory refs +system.cpu.num_store_insts 7078093 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -356,47 +356,47 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.ReadExReq_accesses::0 170341 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 170341 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 170353 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170353 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 62544 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 62544 # number of ReadExReq hits +system.l2c.ReadExReq_hits::0 62556 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 62556 # number of ReadExReq hits system.l2c.ReadExReq_miss_latency 5605444000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.632831 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::0 0.632786 # miss rate for ReadExReq accesses system.l2c.ReadExReq_misses::0 107797 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 107797 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 4311880000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.632831 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.632786 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 107797 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 675421 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 6188 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 681609 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::0 675448 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 6192 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 681640 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_avg_miss_latency::0 52063.722222 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 42597590.909091 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 42649654.631313 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 657421 # number of ReadReq hits -system.l2c.ReadReq_hits::1 6166 # number of ReadReq hits -system.l2c.ReadReq_hits::total 663587 # number of ReadReq hits +system.l2c.ReadReq_hits::0 657448 # number of ReadReq hits +system.l2c.ReadReq_hits::1 6170 # number of ReadReq hits +system.l2c.ReadReq_hits::total 663618 # number of ReadReq hits system.l2c.ReadReq_miss_latency 937147000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.026650 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.003555 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.030205 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::0 0.026649 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.003553 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.030202 # miss rate for ReadReq accesses system.l2c.ReadReq_misses::0 18000 # number of ReadReq misses system.l2c.ReadReq_misses::1 22 # number of ReadReq misses system.l2c.ReadReq_misses::total 18022 # number of ReadReq misses system.l2c.ReadReq_mshr_miss_latency 720880000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026683 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.912411 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 2.939094 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 0.026682 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.910530 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 2.937211 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 18022 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 29200759000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency 29204423000 # number of ReadReq MSHR uncacheable cycles system.l2c.UpgradeReq_accesses::0 1839 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 1839 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_avg_miss_latency::0 313.940724 # average UpgradeReq miss latency @@ -415,81 +415,81 @@ system.l2c.UpgradeReq_mshr_miss_rate::1 inf # ms system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 1822 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 741108000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 417119 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 417119 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 417119 # number of Writeback hits -system.l2c.Writeback_hits::total 417119 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 743252000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 417140 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 417140 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 417140 # number of Writeback hits +system.l2c.Writeback_hits::total 417140 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 7.066815 # Average number of references to valid blocks. +system.l2c.avg_refs 7.067586 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 845762 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 6188 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 851950 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 845801 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 6192 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 851993 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency::0 52009.117864 # average overall miss latency system.l2c.demand_avg_miss_latency::1 297390500 # average overall miss latency system.l2c.demand_avg_miss_latency::total 297442509.117864 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.l2c.demand_hits::0 719965 # number of demand (read+write) hits -system.l2c.demand_hits::1 6166 # number of demand (read+write) hits -system.l2c.demand_hits::total 726131 # number of demand (read+write) hits +system.l2c.demand_hits::0 720004 # number of demand (read+write) hits +system.l2c.demand_hits::1 6170 # number of demand (read+write) hits +system.l2c.demand_hits::total 726174 # number of demand (read+write) hits system.l2c.demand_miss_latency 6542591000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.148738 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.003555 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.152293 # miss rate for demand accesses +system.l2c.demand_miss_rate::0 0.148731 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.003553 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.152284 # miss rate for demand accesses system.l2c.demand_misses::0 125797 # number of demand (read+write) misses system.l2c.demand_misses::1 22 # number of demand (read+write) misses system.l2c.demand_misses::total 125819 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 5032760000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.148764 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 20.332741 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 20.481505 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.148757 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 20.319606 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 20.468363 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 125819 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 5338.149518 # Average occupied blocks per context -system.l2c.occ_blocks::1 31318.985652 # Average occupied blocks per context -system.l2c.occ_percent::0 0.081454 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.477890 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 845762 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 6188 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 851950 # number of overall (read+write) accesses +system.l2c.occ_blocks::0 5338.058091 # Average occupied blocks per context +system.l2c.occ_blocks::1 31318.757980 # Average occupied blocks per context +system.l2c.occ_percent::0 0.081452 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.477886 # Average percentage of cache occupancy +system.l2c.overall_accesses::0 845801 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 6192 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 851993 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency::0 52009.117864 # average overall miss latency system.l2c.overall_avg_miss_latency::1 297390500 # average overall miss latency system.l2c.overall_avg_miss_latency::total 297442509.117864 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 719965 # number of overall hits -system.l2c.overall_hits::1 6166 # number of overall hits -system.l2c.overall_hits::total 726131 # number of overall hits +system.l2c.overall_hits::0 720004 # number of overall hits +system.l2c.overall_hits::1 6170 # number of overall hits +system.l2c.overall_hits::total 726174 # number of overall hits system.l2c.overall_miss_latency 6542591000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.148738 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.003555 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.152293 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.148731 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.003553 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.152284 # miss rate for overall accesses system.l2c.overall_misses::0 125797 # number of overall misses system.l2c.overall_misses::1 22 # number of overall misses system.l2c.overall_misses::total 125819 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 5032760000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.148764 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 20.332741 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 20.481505 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.148757 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 20.319606 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 20.468363 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 125819 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29941867000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 29947675000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 93108 # number of replacements +system.l2c.replacements 93111 # number of replacements system.l2c.sampled_refs 124568 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36657.135171 # Cycle average of tags in use -system.l2c.total_refs 880299 # Total number of references to valid blocks. +system.l2c.tagsinuse 36656.816071 # Cycle average of tags in use +system.l2c.total_refs 880395 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87346 # number of writebacks +system.l2c.writebacks 87350 # number of writebacks ---------- End Simulation Statistics ---------- |